www.ietdl.org Published in IET Power Electronics Received on 25th March 2013 Revised on 25th June 2014 Accepted on 17th August 2014 doi: 10.1049/iet-pel.2013.0486 ISSN 1755-4535 Semi-Z-source inverter topology for grid-connected photovoltaic system Tofael Ahmed, Saad Mekhilef Power Electronics and Renewable Energy Research Laboratory (PEARL), Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia E-mail: saad@um.edu.my Abstract: Transformer-less inverters are necessary parts for grid-connected renewable energy resources. Owing to its cost effectiveness, downsize and less weight, great attention has been paid to these inverters development. With these aforementioned advantages, these inverters have limitations like the flow of leakage current through photovoltaic arrays, high total harmonic distortion (THD) at inverter’s output and DC current injection to the grid. This study presents coupled inductor-based single-phase transformer-less semi-Z-source inverter topology to lessen those limitations. Since the DC input and AC output voltage share a common ground, the presented inverter system is categorised under doubly grounded topologies. For the purpose of handling, the non-linearity of the voltage gain of semi-Z-source inverter, a non-linear sinusoidal pulse-width modulation technique has been employed. The prototype of the suggested inverter has been constructed. The performance and compatibility of modulation technique are verified under different loading conditions. The feasibility of the configuration is ensured based on the mitigated common-mode leakage current, the substantially lower THD as well as DC current injected to the grid. Moreover, the presence of coupled inductor significantly contributes in reducing input current ripple, installation area of the inverter and enhancing the efficiency. Finally, this topology exhibits appreciable performance to operate synchronously and transfer power to the grid. 1 Introduction Renewable energy resources (RERs), like wind turbine, solar photovoltaic (PV) and fuel cell are becoming more and more popular in recent era. This is because of the increasing demand of the clean energy, rapid development of rural area and the concern regarding environmental pollution around the world. As a result, power supplied to the utility grid, especially single-phase low-power systems (≤5 kW) from RER is demanding. These RERs are only capable of producing DC voltage at the output, while to connect these RER with grid, these require AC voltage at the output. Therefore inverters are required to place in between RER and grid to regulate power conversion and control optimisation [1, 2]. Isolated and non-isolated inverters are widely used for connecting RERs with utility grid. The problems of using these isolated inverters are not only the high system cost and larger system size but also reduced overall efficiency of the system. The reason behind these disadvantages is the presence of transformers in the system with line or high frequency for electrical isolation [3]. In contrast, use of non-isolated inverters reduces both cost and size along with improved system efficiency. Presently, the requirement of galvanic isolation is almost obsolete from low-voltage utility grid. Hence, transformerless inverters have turned into the market mainstream [4–6]. However, transformerless systems require some safety issues to be considered, like minimisation of connection effect between the input DC IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 source and the grid as well as DC current injection to the utility grid. If same ground is not shared by both the PV cell and the grid, a variable common mode voltage is developed. As a result, large common-mode leakage current may flow through the parasitic capacitor between PV array and the ground which in turns, reduces the current quality of the grid, rises the system losses and induces electromagnetic interference (conducted and radiated) [6–9]. Conventionally, half or full-bridge inverters have been used to mitigate the problem of common-mode leakage current using bipolar sinusoidal pulse-width modulation (SPWM). So that, no variable common mode voltage is generated. However, half-bridge inverter requires approximately more than 700 V of the DC voltage to produce 220 Vac at the output. Hence, series connections of large number of PV arrays or high conversion ratio DC–DC converter are required. On the other hand, the full-bridge inverter topology requires 50% of the input voltage than that of half-bridge topology (approximately greater than 350 V for 220 Vac) [9]. However, the disadvantages of full-bridge inverter topology are high-current ripple, lower efficiency and large filter inductor. Another way to solve the common-mode leakage current problem is to use doubly grounded topologies. The advantages of these topologies are simple circuit design, low investment cost and enhanced safety [6, 7, 10]. Hence, in this paper, preference has been given to the doubly grounded transformerless topology. On the contrary, some operational issues also need to be taken into consideration for transformerless grid connected 63 & The Institution of Engineering and Technology 2015 www.ietdl.org systems in order to maintain power quality. Such operational issues contain total harmonic distortion (THD), output current regulation and DC current injection. The IEEE and the IEC standards have provided some limit on the maximum range of THD and injected DC current [11, 12]. Acute attention is needed for the DC current injection because this may flow through distribution transformer, energy meters and residual current devices [13–15]. Otherwise, DC current cause saturation to distribution transformer, decrease the efficiency of the system, error in the measurement of energy meter and protective equipment starts malfunctioning. The standard values of DC current injection are different around the world. This limit varies from 5 mA to 1 A where 5 mA is for UK and 1 A for Germany [16, 17]. In contrast, the limit of DC current injection is 0.5% of the rated output current of the inverter for USA and 1% of the rated output current of the inverter for Japan [11, 12]. On the other hand, enhancement of the performance of these transformerless inverters is possible by designing the passive components of the inverter. Most importantly, inductor design is important to improve the performance. It is found that choosing of coupled inductor than separated inductor is best choice for the betterment of inverter performance [18–23]. Also, the role of coupled inductor is very significant in the modern high-frequency switching inverters topology. Since, coupled inductors have the ability to reduce the input current ripple, output voltage ripple and minimise the inverter size. Moreover, the inverter that contains coupled inductor can respond faster to load transient and can decrease the output decoupling capacitance. As coupled inductor minimises the ripple current, it can also minimise the core loss [18–23]. To improve the performance and lessen the cost, many transformerless inverter topologies based on traditional inverter and Z-source or quasi-Z-source inverters have been presented and analysed for renewable energy distributed generators especially for PV application in [14, 24–35]. Doubly grounded features are not included in most of these topologies. Recently, in [36], semi-Z-source inverter for single-phase PV system has been proposed, which shows the ground sharing option between grid and inverters. However, in [36], only the working principle of semi-Z-source inverter with respect to resistive load has been presented. Although, it is mentioned that, this inverter is applicable to incorporate solar PV to utility grid, but the results of grid tie application has not presented in [36]. In addition, the power quality issues during grid connected application like THD and DC current injection have not expressed. Also the features of coupled inductors technique have not illustrated. Another study in [37], discussed about three-switch three-state single-phase Z-source inverter topologies. However, the performance of the inverter under different loading conditions along with the analysis of THD and DC current injection has not included in [37]. A single-stage transformerless semi-Z-source inverter topology for grid connected application is presented in this paper by considering coupled inductor technique. The benefit of this semi-Z-source inverter topology over traditional single-phase full-bridge inverters and Z-source or quasi-Z-source inverters is, to generate sinusoidal voltage at the output of semi-Z-source inverter needs only two switches. Beside this, it contains Z-source network in AC side of the semi-Z-source network, which is different from conventional topology and results in size minimisation. The feasibility of the inverter topology has been analysed not only for static load like R, R–L but also for dynamic load like single-phase induction motor and grid. This inverter aims to minimise the common-mode leakage current with its ground sharing features. It also ensures less THD and DC current injections to the grid by utilising the coupled inductor techniques. In addition, the presented semi-Z-source inverter topology maintains appreciable DC to AC conversion efficiency compared with the conventional inverter and semi-Z-source inverter in [36] by utilising the coupled inductor techniques. On the contrary, the coupled inductor contributes in minimising size of the inverter. To generate sinusoidal voltage at the output, it uses the non-linear sinusoidal voltage gain curve as voltage reference. For this, a non-linear SPWM technique is used to obtain necessary control signal to generate sinusoidal voltage. Section 1 contains an introduction specifying the rational of the project described in this paper. Basic principles of the transformerless semi-Z-source inverters are briefly described in Section 2 followed by the modulation principles in Section 3. Section 4 provides required equations for design. Section 5 describes the important details of experimental setup as well as the results obtained and their discussion. Also this section shows the distortion factor enquiry followed by power losses and efficiency analysis. At last, Section 6 includes the conclusion drawn from all the above discussed section. 2 Basic principle of transformerless semi-Z-source inverter Fig. 1 Discontinuous voltage gain and Continuous voltage gain a, b Z-source and quasi-Z-source DC–DC converters c, d Z-source and quasi-Z-source DC–DC converters 64 & The Institution of Engineering and Technology 2015 Topologies of the DC–DC converters of Z-source and quasi-Z-source are shown in Fig. 1 with the ground sharing nature [30]. Discontinuous voltage gain curve for converters of Figs. 1a and b are shown in Fig. 2a. While, Fig. 2b shows the continuous voltage gain curve of the topologies shown in Figs. 1c and d. Alternating (positive and negative) voltage can be generated by all these topologies at the output when duty ratio varies in between 0 and 1. However, generation of positive and negative voltages at the output with continuous voltage gain curve can be done only by the topologies shown in Figs. 1c and d. Hence, with appropriate modulation strategy these two topologies can be used as inverter as like as the traditional full-bridge inverter. This inverter can generate voltages between –Vin to +Vin at IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 www.ietdl.org Fig. 2 Discontinuous voltage gain, continuous voltage gain curves and single-phase semi-Z-source inverters a Discontinuous voltage gain curve of Z-source and quasi-Z-source DC–DC converters b Continuous voltage gain curve of Z-source and quasi-Z-source DC–DC converters c, d Single-phase semi-Z-source inverters the output while the duty cycle changes remains in between 0 and 2/3. Based on the aforementioned discussions, topologies of the single-phase semi-Z-source inverters with coupled inductor are shown in Figs. 2c and d. From the duty cycle against voltage gain curve shown in Fig. 3a, it is clear that when the duty cycle of switch S1 varies from 0 to 1/2, the inverters can provide positive voltage at the output, whereas, from 1/2 to 2/3 the output voltage is negative [36]. For the duty cycle of 1/2, the inverter produces zero voltage at the output. Figs. 3b and c show the two states of operation, respectively. In state I, switch S1 conducts where input voltage source and capacitor C1 charge the two inductors. For state II, switch S2 conducts and two inductors have turned into sources. The direction of current references of the inductor and the voltage references of the capacitor are mentioned in Figs. 3b and c for the following steady-state equations. Details of the modes of DC operation are shown in [30]. The steady-state equations can be derived based on inductor voltage-second balance and capacitor charge balance principle. The steady-state equations are as follows Vo 1 − 2D = Vin 1−D VC1 = D V 1 − D in IL2 = −Io IL 1 = − D I 1−D o IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 (1) (2) (3) (4) If it is assumed that, inverter output voltage is (5) then the modulation index can be expressed as in (6). Equation (7) has been derived from (1), (5) and (6). D′ = 1–D, the duty cycle of switch S2, which can be expressed as (8) Vo = V sin vt (5) V Vin (6) D= 1 − M sin vt 2 − M sin vt (7) D′ = 1 2 − M sin vt (8) M= 3 Semi-Z-source inverters modulation principle Traditional full-bridge inverter has straight line relation between duty cycle and voltage gain. For this reason, to generate sinusoidal voltage at the output SPWM technique is used. However, there is a non-linear relation between voltage gain and duty cycles of semi-Z-source inverters. For this reason, a non-linear SPWM is used to generate sinusoidal wave as shown in Fig. 3d [36]. A derived reference voltage is shown in (8) to control the duty cycle of switch S2. To turn on switch S2, it is necessary the reference value should be greater than carrier value. Equation (7) shows the reference signal of S1, which is complementary of S2 and the range of the modulation index is between 0 and 1. Fig. 3d shows the switching signals of 65 & The Institution of Engineering and Technology 2015 www.ietdl.org Fig. 3 Semi-Z-source inverters a Voltage gain of single-phase semi-Z-source inverters b Modes of operation of semi-Z-source inverters at state I c Modes of operation of semi-Z-source inverters at state II d Modulation methods of semi-Z-source inverters the switches S1 and S2 at the time when the modulation index is 2/3. 4 Design and analysis of the circuit parameter Configuration of semi-Z-source inverter shown in Fig. 2d has been chosen to analyse various parameters and design consideration of the circuit component. Let the output current expressed in (9) is in phase with output voltage. Voltage across the switch during the OFF state and current through the switch during the ON state can be presented like (10) and (11). From (10) and (11), the maximum OFF state voltage across the switch and maximum ON state current through the switch can be calculated. For this inverter topology, although the switches need to withstand a high voltage it can be applied with high-voltage silicon carbide (SiC) switches [38, 39] Io = I sin vt 1 V = (2 − M sin vt)Vin VS = Vin + VC = 1 − D in IS = IL1 + IL2 = − 66 VC1 = IL1 = − D V = (1 − M sin vt)Vin 1 − D in D I = −( sin vt − M ( sin vt)2 )I 1−D o (12) (13) (9) (10) 1 I = −(2 sin vt − M ( sin vt)2 )I 1−D o (11) & The Institution of Engineering and Technology 2015 Voltage across capacitor C1 and current through inductor L1 can be stated by (12) and (13), which are derived from (2), (4), (7) and (9). Voltage ripple of the capacitor C1 and the current ripple of the inductor can be dictated by (14) and (15) considering L1 = L2. Now, from (12) and (14), the value of capacitance C1 and from (11) and (13), the value of inductance L1 can be selected considering the peak ripple requirement of the voltage and current, respectively. Owing to page limit, details of the design procedure has not provided here. For detail design procedure, one can go through [36] DVC1 = (1 − D)Ts IL1 C1 DIL1 = DIL2 = = − sin vt + M ( sin vt)2 Ts I (2 − M sin vt)C1 Vin Ts D Vin Ts (1 − M sin vt) = L1 L1 (2 − M sin vt) (14) (15) IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 www.ietdl.org 5 Experimental design For the purpose of experimental validation, a prototype rated 48-W, 50 Hz transformerless semi-Z-source inverter is constructed according to the diagram shown in Fig. 2d. The constructed laboratory prototype model of the transformerless semi-Z-source inverter system is shown in Fig. 4. The input voltage of this prototype is about 50 V and the output voltage is about 35.35 V. The switching frequency of this system is 50 kHz. Here, for the prototype, two MOSFETs (STP75NF20) are chosen as switches. The values of both the capacitors C1 and C2 are 4.7 µF considering voltage ripple is limited to 5.75% of the peak voltage across the capacitors. For the prototype, polyester film capacitors (MPE475 K) are chosen. Performance real-time target machine (SPEEDGOAT) has been used to produce the switching signals for the inverter. As mentioned earlier, the most essential components for semi-Z-source inverter are inductor that not only protect the input voltage source but also limit the input current ripple of the inverter. Inductor also serves the purpose of output filter. Two inductors (L1 and L2) used in semi-Z-source inverters can be placed in a single core or in two different cores. To minimise the input current ripple and to reduce the size, coupled inductor method is chosen for the prototype by ensuring identical current flow. For high frequency operation, ferrite materials have the low loss feature and for this, magnetic core of ferrite materials (45528EE) is chosen for this prototype. To prevent the inductor core from saturation under load, an air gap is used within the core structure because; the energy is being stored in air gap, which will prevent the core from saturation under load. The values of the inductor L1 is 400 µH considering current ripple limited to 1/3 of the peak current of the inductor. The values of the inductor L2 is also 400 µH that can be calculated by the same procedure. Finally, the THD of the output voltage and current has been analysed using YOKOGAWA WT 1800 precision power analyser. Experimental results of the laboratory prototype model of 48-W transformerless semi-Z-source inverter are shown in Figs. 5–10. The prototype has been tested under R load, R–L load and motor load. During the laboratory experiment, about 50 V input voltage has been applied and the modulation index has been fixed to 0.95. Around 27 Ω resistance and 285 mH inductance have been used as load. Also, a single-phase induction motor (1/4 Horse power, 50 Hz, 220 V, 2.84 A and RPM-1450) from Mitsubishi Electric has been used as load. Experimental results for R load are shown in Fig. 5. Fig. 5a shows the gate to source voltage VGS1 of switch S1, drain to source voltage VDS1 of switch S1, output voltage Vo and output current Io during R load condition. Zoomed version of Fig. 5a is depicted in Fig. 5b. VGS1 and VDS1 of switch S1 are operating in completely reverse according to the given figures. In addition, there is no phase difference between output voltage and output current. Moreover, output voltage polarity changes with the change of duty cycle of the switch, which satisfies the theoretical background. Drain to source voltage VDS1 of switch S1, drain to source voltage VDS2 of switch S2, output voltage Vo and output current Io are shown in Fig. 5c. Fig. 5d represents zoomed view of Fig. 5c. It can be said that, like the theoretical background these two switches are operating in complementary manner with 50 kHz switching frequency and maximum off state voltage across the switches are 150 V. Fig. 6 illustrates the experimental results for R–L load. When R–L have been considered as load, except for output current and voltage the remaining results are almost same like R load. It observed from Figs. 6a and c that the output current is lagging the output voltage and the magnitude of the output current decreases as the load increase. Waveforms of input voltage Vin, voltage across capacitor C1, output voltage Vo and output current Io for R and R–L loads are shown in Figs. 7a and b, respectively. These two figures illustrate that, peak capacitor voltage is twice the input voltage for both the R and R–L loads. Moreover, both the positive and negative peak values of the output voltage are equal to the input voltage. Furthermore, during experiment the input voltage has been measured between DC + terminal and ground for both the R and R–L loads. Fig. 4 Most important components of the experimental setup of semi-Z-source inverter IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 67 & The Institution of Engineering and Technology 2015 www.ietdl.org Fig. 5 Experimental waveforms for R load a Gate to source voltage, drain to source voltage, output voltage and output current b Zoomed in waveform of gate to source voltage, drain to source voltage, output voltage and output current c Drain to source voltage of two switches, output voltage and output current d Zoomed in waveform of drain to source voltage of two switches, output voltage and output current Figs. 7a and b display that for both the R and R–L loads condition, the input voltage Vin is almost constant and contains no high frequency variation. As a consequence, the generation of common mode voltage is minimised, which in turns results in reduction of common-mode leakage current. The voltage across capacitor C1, current through inductor L1, output voltage and output current of the inverter for both the R and R–L loads are shown in Figs. 7c and d, respectively. Both the figures notified, voltage developed across the capacitor C1 followed by the inductor current IL1 and inductor current is approximately twice the output current for both the load conditions. Fig. 8 illustrates the condition when a single-phase induction motor has been applied as load at the output of inverter. Fig. 8a shows the waveforms of input voltage Vin, output voltage Vo and output current Io at the starting condition of the motor. Meanwhile, Fig. 8b shows the same waveforms when the motor operates at one of the steady-state condition of motor. It is seen from these two figures that, motor draws high current during starting as single-phase induction motor requires high current density at the auxiliary winding during starting. For this reason, the 68 & The Institution of Engineering and Technology 2015 output voltage and current of the inverter have some distortion at the starting condition. Whereas, at steady-state condition it draws less current from inverter which in turns, reduce the distortion of output voltage and current. It can also be seen that, the output current is lagging the output voltage for both the starting and running conditions for the motor load. THD and harmonic spectrum of the output voltage and current for R, R–L and motor loads (starting and steady-state condition) are displayed in Figs. 9a–d, respectively. It can be depicted from Figs. 9a and b that, for R load the inverter produces RMS output voltage of 35.94 V with THD of 4.506% and RMS output current of 1.30 A with THD of 4.50%. While for R–L load the inverter produces RMS output voltage of 35.76 V with THD of 1.16% and RMS output current of 0.315 A with THD of 1.68%. In case of R load, the inverter supplies real power of 46.76 W at unity power factor. On the other hand, the inverter supplies real power of 3.68 W and reactive power of 10.62var for R–L load. In addition, for both the R and R–L loads condition, THD’s are within the limit (<5%), no occurrence of DC current component and percentage of IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 www.ietdl.org Fig. 6 Experimental waveforms for R–L load a Gate to source voltage, drain to source voltage, output voltage and output current b Zoomed in waveform of gate to source voltage, drain to source voltage, output voltage and output current c Drain to source voltage of two switches, output voltage and output current d Zoomed in waveform of drain to source voltage of two switches, output voltage and output current higher order harmonic components are very negligible at the output. On the contrary, Fig. 9c shows the THD and harmonic spectrum at the starting condition of motor load. Whereas, Fig. 9d shows the THD and harmonic spectrum when the motor load has been operated at one of the steady-state conditions of motor. At the starting of the motor, the inverter produces RMS output voltage of 32.26 V with THD of 9.93% and RMS output current of 2.65 A with THD of 10.49%. Whereas, at the steady-state condition the inverter produces RMS output voltage of 40.25 V with THD of 0.834% and RMS output current of 0.38 A with THD of 5.48%. At the starting of motor, the output voltage and current of inverter contains high THD because, motor stator winding of single-phase induction have high harmonic distortion during starting [40]. However, during the steady-state condition, the output voltage contains very less THD and current contains slightly greater than 5% as the motor does not run in rated speed here. It is also seen from these figures that, the inverter supplies real power of 68.70 W and reactive power of 50.91var at 0.80 power factor during starting of motor load. Furthermore, during the steady-state condition of motor, the inverter supplies IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 real power of 4.90 W and reactive power of 14.27var at 0.33 power factor. In addition, the inverter is capable of supplying not only real power but also reactive power at low power factor and output contains no DC components as well as higher order harmonics. Finally, the prototype of the inverter has interfaced with the low voltage utility grid to observe the power transfer in synchronous mode. During interfacing with the grid in laboratory condition the utility grid voltage has been taken 50 Vac with frequency of 50 Hz. Synchronous operation between grid voltage and inverter output voltage is shown in Fig. 10a. Fig. 10b shows the experimental waveforms of grid voltage and grid current during full-load condition. It shows that, there is no phase difference between the sinusoidal output current of inverter or grid current and the grid voltage. Experimental waveforms of input voltage Vin, voltage across capacitor C1 and output current Io of the inverter during grid interfacing are shown in Fig. 10c. This figure depicts that, during grid tied application input voltage is almost constant and contains no high frequency variation, which means that the generation of common mode voltage is minimised, which results in the generation of common 69 & The Institution of Engineering and Technology 2015 www.ietdl.org Fig. 7 Input DC voltage, capacitor C1 voltage a Output voltage and output current for R load b Output voltage and output current for R–L load c Inductor L1 current, output voltage and output current for R load d Inductor L1 current, output voltage and output current for R–L load Fig. 8 Input DC voltage, output voltage and output current at the a Starting condition of motor load b Steady-state condition of motor load 70 & The Institution of Engineering and Technology 2015 IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 www.ietdl.org Fig. 9 THD and harmonic spectrum of output voltage and current a For R load b For R–L load c At the starting condition of motor load d At the steady-state condition of motor load mode current. Also it shows that, peak values across the capacitor is double of input voltage and inverter output current or injected grid current is almost sinusoidal. THD and harmonic spectrum of the inverter output voltage and injected grid current during interfacing with the grid are shown in Fig. 10d. It can be seen from this figure that, the inverter transfers power of 44.19 W and injected grid current have THD of 4.58%. During this time, the inverter shows almost unity power factor. In addition, percentages of higher order harmonic components are very negligible and no occurrence of DC current during transferring power to the grid. Hence, it is observed that the inverter is capable of transferring power to the grid by maintaining the power quality issues. Because, the coupled inductors have the ability to reduce the input current ripple, output voltage ripple and can decrease the output decoupling capacitance, which results in the power quality issues improvement. The sum up of the above discussions is, the transformerless semi-Z-source inverter generates sinusoidal voltage at the output by utilising only two switches where this number is four for traditional single-phase full-bridge inverters and IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 Z-source or quasi-Z-source inverters, which minimises the cost. Also, this inverter is capable of working under static as well as dynamic load. For grid connected application, the designed transformerless semi-Z-source inverter injects less voltage as well as current harmonics (<5%) and no DC current component to the grid, which follows the IEEE and IEC standards as stated in [11, 12]. Moreover, this transformerless topology is rarely affected by the higher order harmonics. Furthermore, this inverter can exhibits stable operation for supplying both the real and reactive power till violation of maximum rating of the semiconductor devices and passive components. Finally, utilisation of coupled inductor techniques and the Z-source network in AC side rather than DC side ensures the total size minimisation of the presented semi-Z-source inverter. 5.1 Distortion factor (DF) DF refers to the total distortion of any waveform considering all the harmonics and noise contents of that waveform. Voltage distortion factor (VDF) and current distortion (IDF) 71 & The Institution of Engineering and Technology 2015 www.ietdl.org Fig. 10 Experimental waveforms of a Inverter output voltage and grid voltage b Grid voltage and grid current c Input DC voltage, capacitor C1 voltage and output current during interfacing with grid d THD and harmonic spectrum of output voltage and current during interfacing with grid 5.2 factor can be defined as the following equations 2 2 2 2 Vh02 + Vh03 + Vh04 + · · · + Vhn VDF (%) = × 100% 2 Vrms 2 2 Vrms − Vh01 × 100% (16) = 2 Vrms 2 2 2 I 2 + Ih03 + Ih04 + · · · + Ihn IDF (%) = h02 × 100% 2 Irms I2 − I2 = rms 2 h01 × 100% Irms (17) where Vh01, Vh02, Vh03, ..., Vhn are the amplitude of fundamental, 2nd, 3rd, …, nth harmonics of voltage and Ih01, Ih02, Ih03, …, Ihn are the amplitude of fundamental, 2nd, 3rd, …, nth harmonics of current. By using (16) and (17), DF can be calculated and Table 1 shows the values of DF for different load conditions. 72 & The Institution of Engineering and Technology 2015 Power losses and efficiency Power loss and efficiency are very important factors for inverter design. Generally, two types of power losses associated with semi-Z-source inverter topology like power losses in semiconductor devices and power losses in inductor. 5.2.1 Semiconductor devices power losses of semi-Z-source inverter: Power losses analysis for transformerless inverter efficiency evaluation has been shown in [6, 41–44]. Equations (18) and (19) show the first-order conduction voltage drop model for MOSFET and diode, respectively vds (t) = i(t)Rds (18) vak (t) = Vf + i(t)Rak (19) where vds, Rds, Vf and Rak are the MOSFET drain–source voltage drop, MOSFET drain–source on resistance, diode equivalent voltage drop under zero current condition and diode on resistance, respectively. Here, i(t) is the inverter output current as shown in (9). As stated earlier, the two IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 www.ietdl.org switches of the semi-Z-source inverter are working in complementary mode and the duty ratios of the switchs S1 and S2 are shown in (7) and (8), respectively. Equation (20)–(23) show the conduction losses for switches S1, S2, source–drain diode conduction losses of S1 and source–drain diode conduction losses of S2, respectively applied switching frequency by calculating the peak-to-peak flux density by the following equation p where ΔB, V, t, N and Ae are flux density in Tesla, applied voltage to the winding in volts, time of applying voltage in seconds and cross-section area of core in square metre. The conducting losses for DC and AC resistance of the inductors L1 and L2 can be calculated by using (28)–(31), respectively Ps1 Ps2 PSource PSource MOSFET MOSFET 1 = 2p = Drain Diode S1 Drain Diode S2 1 2p = i(t)vds (t)D(t) dvt (20) i(t)vds (t)D′ (t) dvt (21) 0 p 0 1 2p 1 = 2p p i(t)vak (t)D(t) dvt (22) p ′ i(t)vak (t)D (t) dvt MOSFET EonD = tr +tf 0 Psw 2 = Idc1 Rdc1 = IL21 Rdc1 (28) PDC L2 2 = Idc2 Rdc2 = IL22 Rdc2 (29) 0 where td(on),td(off), fsw and Coss are turn-on delay time, turn-off delay time, switching frequency and output capacitance, respectively. Another important loss is the diode switching loss, which is induced for reverse recovery energy of diode (EonD). (EonD) and the diode switching losses can be calculated from (25) and (26), respectively. By substituting the values from datasheet [46], the power losses of the two semiconductor (MOSFET) switches have been calculated 1 vak (t)i(t) dvt ≃ Qrr Vds 4 Source Drain Diode = EonD fsw PAC PAC where tr, tf and Qrr are rise time, fall time and reverse recovery charge, respectively. 5.2.2 Inductor power losses of semi-Z-source inverter: Power losses across inductor take place because of core losses and winding losses. Semi-Z-source inverter winding losses includes the conduction losses of DC resistance RDC and AC resistance RAC. Core losses of the inductor can be calculated from the data sheet [47] at L1 2 = IAC1 RAC1 = L2 2 = IAC2 RAC2 = DIL21 R 12 AC1 DIL22 12 RAC2 (30) (31) To calculate the power loss of semi-Z-source inductor, DC and AC resistances have been measured by LCR meter (PINTEK LCR-900). The values of the DC resistance of the two inductors are RDC1 = 0.10 Ω and RDC2 = 0.09 Ω, respectively. AC resistance of the inductors have been measured at switching frequency and the values are RAC1 = 0.14 Ω and RAC2 = 0.135 Ω, respectively. After calculating the inductor power losses, total power losses of semi-Z-source inverter topology can be calculated by summing semiconductor devices power losses and inductor power losses. 5.2.3 Efficiency: After calculating the total losses of semi-Z-source inverter topology, the relative efficiency can be calculated based on the following equation Efficiency(%) = (25) (26) (27) L1 (23) 1 1 = IVds (td(on) + td(off ) )fsw + Coss Vds2 fsw (24) 2 2 Vt NAe PDC 0 Most of the losses occur during drain-to-source switching transition of the MOSFET switch. Discharging of the junction capacitor Coss of MOSFETs causes the capacitive turn-on loss, which in turns, cause the switching loss. As in [45], the switching losses can be calculated from the following equation PSW DB = Pout Pout + Ploss × 100% (32) Also, for the prototype, the efficiency can be measured based on the following equation Efficiency(%) = Pout Pin × 100% (33) During the measurement of efficiency all kind of losses like, core and copper loss of the inductor, gate drive loss, switching loss (turn on, turn off and diode reverse recovery interval) have been considered. Table 1 Values of DF for different load Load type R load R–L load motor load (starting condition) motor load (steady-state condition) Voltage distortion factor VDF, % Current distortion factor IDF, % Voltage, V Current, A VTHD, % ITHD, % Real power, W Reactive power, VAR 5.27 3.73 13.09 5.68 10.38 18.85 35.941 35.759 32.281 1.30 0.314 2.65 4.50 1.162 9.93 4.50 1.681 10.50 46.76 3.68 68.70 0.52 10.63 50.91 6.06 16.59 40.244 0.375 0.834 5.489 4.90 14.266 IET Power Electron., 2015, Vol. 8, Iss. 1, pp. 63–75 doi: 10.1049/iet-pel.2013.0486 73 & The Institution of Engineering and Technology 2015 www.ietdl.org Table 2 Comparison of the loss mechanism in the traditional full-bridge inverter [47] and the semi-Z-source inverter topology power loss (Ploss), W efficiency, % Traditional full-bridge inverter [48] Semi-Z-source inverter [36] Semi-Z-source inverter (calculated) Semi-Z-source inverter (measured) 3.59 4.58 2.169 2.42 92.68 90.45 Table 2 shows the comparison of the power losses and efficiency between semi-Z-source inverter, traditional full-bridge inverter topology of [48] and semi-Z-source inverter in [36] for the instance when both the inverters have same output power ratings. It can be said the, the prototype of the presented semi-Z-source inverter have a lesser amount of losses, which increases the efficiency compared with the traditional single-phase full-bridge inverter and semi-Z-source inverter in [36]. 6 Conclusions This paper describes a transformerless semi-Z-source inverter topology. This inverter topology is acceptable for interfacing RERs especially for solar PV with utility grid and supplying standalone PV power conditioner. By utilising semi Z-source network; this topology employs only two active switches and a non-linear SPWM technique to generate required sinusoidal voltage at the output. Coupled inductor techniques are included in the topology to limit the input current ripple output, output voltage ripple and decrease the output decoupling capacitance as well as to minimise the inverter size and enhance the efficiency. As the input and output terminals share the same ground, the leakage current flows through both grid and RERs obtain minimised. In addition to those, this low cost-compact inverter configuration could ensure the reduced THD of output voltage and current without any filter and suppress DC current component injection to the utility AC grid line in spite of the transformerless inter connection PV-conditioner by utilising the benefit of coupled inductor techniques. Also, for the designed prototype the calculated and measured power losses are 2.169 and 2.48 W, respectively, which helps to maintain appreciable efficiency compared with the traditional full-bridge inverter during DC to AC conversion. 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