June 2004 | Issue
Business & Technical News
from Unaxis Wafer Processing
LLS EVO II Re-design
Compatible High Performance
with Unaxis Products:
CLUSTERLINE®
VERSALINE™
VLSI 10 BEST Award
5th Year Running
14
Unaxis Insights
Introducing Unaxis Wafer Processing
2
Exceeding Customer Expectations
3
The new
CLUSTERLINE®
series features
significant
improvements
and innovations.
Technical Training
An investment into the future
6
Feature
Thin Wafers – Big Performance
7
Advanced Packaging
APiA’s new Virtual Process Line
Taking process integration a step further
10
Wafer Level CSP at
National Semiconductor
12
Advanced Silicon
Re-launch of the CLUSTERLINE ®
Towards zero handling defects
14
23
Unbeatable RAM: Reliability, Availability,
Maintainability
The Unaxis CLUSTERLINE® at Philips Boeblingen
16
LLS EVO II, the new
batch sputtering
system from Unaxis:
quicker assembly
and installation,
shorter service times,
and easier handling.
Power Semiconductors from Infineon
contents
contents
Backside metallization by Unaxis
18
Photomask
The Unaxis MASK ETCHER® IV
Keeps its Promises
20
Compound Semi&Microtechnology
The new LLS EVO II
New customer benefits
23
GaAs Manufacturing
Optimization of low stress PECVD silicon nitride
28
High Performance Oxide Etch
on the new VERSALINE™ platform
32
Pressure Control in DSE Processes
36
DSE: Notch Reduction for SOI
39
28
Unaxis solutions for
PECVD silicon nitride
are used extensively
in the production of
GaAs devices.
www.waferprocessing.unaxis.com
Unaxis Insights
Front Cover
Backside metallization
on a 300 mm wafer
Kenneth T. Barry
President, Unaxis Wafer Processing
Editor in Chief
Juerg Steinmann,
Global Communications
Manager Unaxis
Wafer Processing
Executive Editor
Marion Turner,
U.S. Marketing
Communications Manager
Unaxis Wafer Processing
Design / Layout
Cactus AG
Photography
Michael Reinhard
and Unaxis, unless
stated otherwise
Published by
Unaxis Wafer Processing
P.O. Box 1000
FL-9496 Balzers
Liechtenstein
Printed by
Südostschweiz Print AG
If you have any
questions or comments,
please contact us at
chip@unaxis.com or
fax back the reply card
provided in this magazine.
Chip, the Business &
Technical News from
Unaxis Wafer Processing,
is also available online at:
www.waferprocessing.unaxis.com
editorial
editorial
Managing Editor
Veronika Schreyer,
is design
Welcome to Chip 10!
In our continued quest to meet and anticipate customer expectations we are
very pleased to report a positive balance half way through the year 2004. Again,
for the fifth year running, we have been awarded a place among the 10 BEST
semiconductor equipment suppliers. Responsible for this success are all Unaxis
employees and partners, who share our commitment to business excellence.
Another step on the quality ladder is the full compliance with ISO 9001 and
ISO 14001 standards in both Wafer Processing technology centers St.Peterburg,
Florida, and Truebbach, Switzerland (page 3).
On the product side we can now announce the re-design of our industry-proven
CLUSTERLINE® with significant improvements and innovations. We consider
this project an extremely important contribution to our customers' product and
process requirements. On page 14 you find a first article on the details of the
re-design. The continued success of the CLUSTERLINE® is demonstrated at our
customers' production sites though consistently out-performing our competitors
by far. Performance data from Philips Boeblingen can be found in the article on
page 16. Also, the VERSALINE™, which was launched at Semicon West last
year, has been developed further to provide our customers with a flexible, and
modular extention of production capacity. Process modules of VERSALINE™ and
CLUSTERLINE® are now compatible. Read more about this highly advantgeous
feature in the articles about DSE processes on pages 36 – 39.
In our last edition of Chip we introduced the improved MASK ETCHER® IV.
The system is living up to all expectations under market conditions and shows
excellent results on many different applications (page 20).
The batch sputtering system LLS EVO II is yet another new product from Unaxis
Wafer Processing that extends and improves existing functionality. Fully compatible
with the well-known strengths of the LLS EVO, the new system provides quicker
installation, shorter service times, and easier handling. Details about the LLS EVO II
can be found on page 23.
I hope you will enjoy reading this edition of Chip, and that we can either answer
some of your questions or leave you wanting to know more about Unaxis Wafer
Processing and our products. Please contact us, we are looking forward to hearing
from you.
Sincerely,
Kenneth T. Barry
Unaxis Chip
Introducing Unaxis’ New
“Semiconductor Equipment”
Segment
Vacuum
Solutions
Components and
Special Systems
Space Technology
Display Technology
Assembly & Packaging
Coating
Services
Optics
Data
Storage
Solutions
Semiconductor
Equipment
Wafer Processing
Unaxis Insights
Unaxis Insights
Unaxis Insights
Fredéric van Mullem
Vice President Human Resources
In September 2003, Unaxis announced
its intention to acquire full ownership of
the ESEC Corporation.This decision was
confirmed by the ESEC shareholders in
October 2003. On March 12, 2004, the
courts in Switzerland granted Unaxis and
ESEC its final approval, and theintegration
of ESEC into Unaxis could proceed
according to plan. With this acquisition,
Unaxis and ESEC together achieve the
necessary size and scale to successfully
compete in the semiconductor capital
equipment industry. The company now
ranks amongst the world’s ten leading
process solutions and global equipment
providers.
Consequently, Unaxis introduced its
new segment “Unaxis Semiconductor
Equipment”, which combines its
Semiconductors Back End (ESEC),
Semiconductors Front End and Displays
businesses; these divisions have been
renamed as follows:
J Unaxis Semiconductors Front End
becomes the “Wafer Processing”
Division
J Unaxis Displays becomes the “Displays
Technology” Division
J ESEC (Semiconductors Back End)
becomes Unaxis’ “Assembly &
Packaging” Division
The diagram illustrates our new
organizational structure.
2 | Chip Unaxis
New Unaxis organizational structure
Capitalizing on synergies
Unaxis has held a majority interest in
ESEC since the year 2000. The complete
integration of the two companies
strengthens Unaxis’ position in chip
assembly equipment and processing
techniques for the semiconductor industry.
This portfolio reorganization will allow
us to leverage our unified Unaxis/ESEC
brand structure while maintaining each
business’s specific identity and history.
Clearly, our intention is also to capitalize
on the synergies that exist between
the three businesses, with common
characteristics in markets, technologies
and operations.
We are currently in the process of
integrating and aligning the Segment’s
management and legal structure in the
countries where we operate, particularly
in Asia. This process should be completed
before the end of 2004.
At the same time, we are actively
looking at more operational synergies,
where and when these make good
business sense for Unaxis and for its
customers. For instance, a common
approach to supply chain (manufacturing,
purchasing) and customer support
(e.g. spare parts management) will result
in enhanced efficiency and better service.
Customers who are common to several
divisions will benefit from a more
comprehensive consideration of their
needs and working practices.
Future plans
The “Unaxis Semiconductor Equipment”
segment will continue to focus its efforts
on selected growth markets in the
semiconductor and displays industries.
By combining its core capabilities in the
fields of thin-film and chip-assembly
technologies with its global footprint in
sales, service, and support, Unaxis is
now best positioned to satisfy customer
needs to an even greater extent and
to participate more extensively in future
market developments.
Each division’s strategy and
operational goals remain unchanged.
This reorganization will not affect or
alter the working relationship with our
customers – assuring continuation of all
current customer contacts with Unaxis.
For more information please contact:
frederic.vanmullem@unaxis.com
Jim Coughlin
Division Business Excellence Manager
Previous issues of “Chip” kept you up to
date with quality standards development at
Unaxis Wafer Processing. In 2004, we are
proud to announce full compliance with
ISO 9001:2000 and ISO 14001 at both
our manufacturing sites, St. Petersburg,
USA, and Truebbach, Switzerland.
Ecological aspects and sustainability
have always played important roles in
Unaxis’ production processes. Unaxis
Wafer Processing is a leader in the field
of new production technologies which
reduce the consumable materials during
chip production, as well as in the finished
product itself. New technologies and
materials like silicon-germanium enable
the production of faster and more
energy-efficient chips.
Attaining the ISO 14001 certification
represents a significant milestone for
Unaxis Wafer Processing to continue as
a world class leader in thin film production
solutions.
Another award underlining the
payback of our continued dedication
to quality: for the fifth time running, Unaxis
Wafer Processing has been awarded
a place among the VLSI “10 BEST”
semiconductor equipment suppliers.
From quality standards to business
excellence
To fully understand the direction that
Unaxis Wafer Processing is taking
in expanding its capability of fulfilling
customer expectations, it is essential
to understand the process by which the
Division is managed. The strategy is the
three-year vision of where the Division is
going and what actions it must take to
fulfill customer expectations.
Unaxis Wafer Processing set out to
fully integrate the Business Excellence
Strategy (BEx) into the overall Divisional
Strategy. Senior managers representing
all business aspects within the Division –
Global Sales, Marketing and
Communications, Innovation and
Technology, the Strategic Business
Units, Operations, Customer Support,
Business Excellence and Finance –
converge quarterly to discuss strategic
direction. Following a comprehensive
review, in which the managers question
and evaluate all areas of the division’s
business, the new Divisional Strategy is
validated. It has become the roadmap
for the Division’s direction; addressing BEx
goals in a broad fashion, in a sense
providing a vision for everyone to follow.
To ensure continual viability, the
strategy is under annual review based
on changes in the marketplace and
customer expectations.
Unaxis Chip | 3
Unaxis Insights
Exceeding Customer Expectations
With Business Excellence
Unaxis Insights
Unaxis Insights
Tactical Business Plan =
Implementation
Business
Risk
Vision
Mission
SWOT
Strategic
Direction
Applied “BEx”
The primary goal of our BEx Strategy
is to ensure that each planning process
considers health, safety, the environment,
risk mitigation, product liability concerns,
business process effectiveness, and
design and product assurance. From
an operational standpoint, some BEx
objectives are already captured in many
areas of our daily working practice.
“Business Excellence simply means living our vision and
mission, translating them into real business and production
processes for everyday working life. Our Division’s Business
Excellence Strategy is based on input from all global
operations, from customers worldwide, from Unaxis
employees, and technology market analysts.”
Ken Barry, Division President
4 | Chip Unaxis
Customers
Financials
Resources /
Capabilities /
Innovation
Balanced Score Card
Processes
E
An xte
al rna
ys l
is
I
An nter
al na
ys l
is
Effective implementation
The annual Tactical Business Plan of the
Division contains individual commitments
by members of the Global Management
Team; it establishes the specific tasks
required to implement the goals defined
in the strategy. Internal and external
benchmarks are set, which enables
measurable process improvement and a
performance exceeding expectations.
The quarterly joint reviews ensure a
dynamic exchange of essential information
about the collective progress in meeting
targets and challenges faced by all
aspects of the organization. Goals are
disseminated to all Unaxis employees and
business partners. Effectively, everyone
participates in fulfilling the BEx objectives
as reflected in the Division’s Strategy and
Tactical Business Plans.
The first direct result of implementing
the new BEx Strategy is a marked
improvement of the Unaxis Wafer
Processing complaint management
system. We have learned to better listen
to our customers and are now able to
act efficiently and effectively worldwide.
Health and Safety: The primary objective
is to ensure a safe and healthy working
environment for all employees. This has
long been part of Unaxis policy and is also
supported by all our business partners.
The Environment: The Division’s
ISO 14001 certification demonstrates
our commitment to sustainable and
environment-friendly production covering
the complete life-cycle of our product.
Risk Management: Risks managed
by the Division on a daily basis include
a wide array ranging from those posed by
nature, man, the marketplace, currency
markets, international laws, competitors,
and customer expectations. Unaxis
Wafer Processing reviews up to sixty-five
different risks, prioritizes them, and
develops specific action plans to control
or mitigate these risks.
Product Liability: All Unaxis products
are designed and manufactured to
operate safely. New products are subject
to independent design verification and
testing by recognized third party testing
agencies as well as to a combination of
national and international safety
standards.
Our product liability control program
also informs our customers about the
safe use of our products. Due to the
large number of environmental health
and safety regulations and laws that
exist throughout the world, we advise
our customers on how to fulfill their
responsibility to comply with local
requirements and provide training
wherever necessary.
Product Assurance: We make certain
that Unaxis products meet all specification
requirements, that they are adequately
tested prior to delivery to the customer,
and that each product performs reliably.
All of these issues directly relate to our
customers’ cost-of-product ownership.
The test of any business excellence
program is the way it is put into practice,
how it relates to operational reality
throughout the Division worldwide and
to customer expectations. We are
confident Business Excellence is
becoming an integral part of our working
lives at Unaxis Wafer Processing
resulting in better products, better
processes, and better customer relations;
it is an investment into our future.
For more information please contact:
jim.coughlin@unaxis.com
Unaxis Vision
Unaxis creates outstanding benefits
for its customers.
J Sustainable above-average growth and
profitability are key to strengthening the
market position of Unaxis and investing in
new products and applications.
J Unaxis fosters a corporate culture that
encourages entrepreneurship, team spirit,
and personal growth.
J Unaxis contributes to society and
environmental improvement.
Unaxis Mission
Unaxis is a global leader in technologies,
manufacturing solutions, components
and services in selected growth markets.
J The activities of Unaxis span the segments:
Semiconductor Equipment
Production systems for semiconductors
and flat panel displays
Data Storage Solutions
Production systems for data storage
devices
Coating Services
Coating of tools and components
Vacuum Solutions
Vacuum technology
Components and Special Systems
Optical components and aerospace
technology
J Unaxis creates integrated solutions by
leveraging its core competencies in thin film,
vacuum and precision technology.
J In long-term partnership with its customers,
Unaxis develops unique solutions, providing
them with a competitive edge.
Unaxis Chip | 5
Unaxis Insights
Unaxis Insights
Technical Training:
A Proactive Investment
David Hartel
Customer Support Manager
Unaxis Wafer Processing has two
independent training departments to fulfill
the training requirements of its internal
and external customers. One is located
in Trübbach, Switzerland; the other in
St. Petersburg, Florida. Both offer
technical programs on products that are
manufactured at their respective locations.
In addition, training is still provided on
products which have been discontinued.
All training programs have been
developed around the PerformanceBased Equipment Training model, or
(PBET). The instructors in each location
have been certified to develop training
packages in this format. Programs
developed prior to this standard have
been redefined to meet the PBET
objective. They focus on the actual
needs of the student, as it pertains to
the performance requirements of the
individual when they are on the job.
The training programs are offered at
customer sites, as well as respective
Unaxis training centers.
Programs are developed to meet
the needs of the equipment operator,
maintenance engineer, as well as Unaxis
customer support engineers. In addition
to our standard equipment programs,
we also provide specialized programs
for our customer support engineers.
They include programs in RF, vacuum
applications, and software. All courses
are individualized to meet specific
needs of our many customers.
6 | Chip Unaxis
With respect to Unaxis’ internal training
program, a semi-annual evaluation of
customer support engineer capabilities
is performed and compared to present
and future needs. Their competencies are
identified in a skills matrix, showing
strengths along with areas where additional
training is needed. The matrix also assists
management in choosing the most
qualified person for the job. It helps map
areas to be developed for each engineer
to achieve the next step in their career.
The training departments are also
actively involved with new product
development. Rather than wait for
products to reach completion, we are
actively developing our own training
platforms to address the needs of the
customer support engineer. The engineer
who is responsible for the installation and
maintenance of new systems, is fully
prepared before the system is ready to
ship. Aside from classroom training the
customer support engineer receives, they
work closely with manufacturing to
acquire troubleshooting skills and real
world experience to prove them
successful in the field.
Alternate methods of training are also
being explored. Virtual Training online
is becoming a necessity in the age of
“greater value for less cost.” We are also
exploring the integration of manufacturing
software currently being used in the
design of new products into training
packages. This software allows the user
to view the assembly construction, with
the added capability of rotating the
assembly and viewing it from many
angles. These training packages can
be adapted to meet specific customer
needs, and we anticipate this reducing
customer training cost. In developing
new programs, we anticipate packaging
these so customers can utilize them
in-house. As a self-paced training
package, customers can train their
personnel at their own pace. At Unaxis
Wafer Processing we continually strive
to improve our training methodology,
anticipating future customer requirements.
Current available training classes
can be viewed online at:
http://waferprocessing.unaxis.com/
en/welcom_413.asp.
For training enquiries please contact our
local sales and service office.
www.waferprocessing.unaxis.com
Feature
Overview of features driving the need
for power semiconductor innovation
J Packaging which allows for more
functionality and power dissipation in
smaller packages
Thin Wafers –
Big Performance
Figure 1: Thinner
wafers reduce power
consumption of
consumer electronics
Source: Infineon
Technologies Company
Presentation 2004,
CeBIT Hanover
J Advances in trench processes have pushed
the contact resistance RDS(on) to new lows
J Need for high-voltage MOSFETS aimed at
automotive switching applications
It is hard to believe that by simply making a silicon chip
a few microns thinner, new, super-efficient components and
systems can be built. They have the potential to reduce fuel
consumption of cars by 50 percent, cut energy needs of
household appliances by 30 percent, and slash the electricity
used by telecommunications equipment, computers, and
TVs in standby mode to zero.
But this is exactly what power
semiconductor manufacturers, such
as Infineon and Philips Semiconductors,
to name two, are proving. They are
part of a growing number of analog
semiconductor vendors that are exploiting
an innovative thin wafer process, enabled
by Unaxis’ CLUSTERLINE® system.
Manufacturers of 150 mm wafers
are pushing wafer thicknesses below
100 µm, with 65 µm wafers in
development. Slightly thinner than a
piece of paper, these wafers have a
metalized coating on the backside.
In bipolar transistors, electrical resistance
is a function of chip-thickness: thinner
Power consumption per household
Power consumption with conventional power supplies
Power consumption with innovative switched power supplies
J TV-set
J Analog phone
J Radio/CR
J VCR
J PC
J Monitor
J TV-set
J Dect phone
J Radio/CR
J VCR
J PC
J Monitor
J Handy
J Active speaker
J Dect phone
J VCR
J PC
J TV-set
J Dect phone
J Radio/CR
J VCR
J PC
J Monitor
J Handy
J PDA
J Notebook PC
J Monitor
J Handy
J PDA
J MP3 Player
J DSL adapter
J Active speaker
J DVD player
J Set-top box
1995
2000
2005
J MP3 player
J DSL adapter
J Active speaker
J DVD player
J Flat TV-set
J Beamer
J Home Cinema
J Set-top box
J Boost in alternator output in the automotive
industry from power conversion devices
J Start-up sequencing of multiple converters
to meet system requirements
J Programmable output switching regulators
J Tighter specifications for fuel gauging and
battery charging
J Lower quiescent currents
Source: VDC
chips offer less resistance and a
maximizing of current throughput.
Market segments
When thin wafer dies are used in
discretes and semiconductors for power
supply and power management, terrific
leaps in efficient power use are achieved.
These devices are making their way into
white goods, such as washing machines,
refrigerators, as well as climate controls,
pumps, and low-power industrial tooling.
The chips are also found inside adapters
and chargers for mobile phones, PDAs,
notebook PCs, and toys. An emerging
market is in new third generation base
station equipment for RF power devices.
Even higher voltage and high-frequency
applications, such as transformers for
electric welding equipment, uninterruptible
power supplies, as well as switch mode
power supplies and high-voltage
converters for microwave and medical
equipment, are target applications.
Thin wafer dies are highly conductive,
switch faster, and can be packaged
in such a way using insulators so they
cool themselves. This means that
transformers are no longer required in
power modules.
2010
Unaxis Chip | 7
Feature
Valerie Thomson
Technical Journalist
Zurich
J Sophisticated drive schemes to power
white LEDs
Figure 2: Worldwide shipment
forecast for power supply and
power management integrated
circuits (published 12 /12 /03)
Source: Venture Development
Corporation (VDC)
8,000
6,984.0
7,000
6,515.2
5,875.4
6,000
8 | Chip Unaxis
M$
5,000
4,000
3,000
2,000
1,000
0
2002
2003
2004
2005
2006
12,000.0
10,000.0
8,000.0
M$
Feature
A growing market
Chip manufacturers who have adopted
the thin wafer processes are seeing
increased demand, particularly in the
automotive and white goods sectors,
according to Dr. Reinhard Benz,
Product Marketing Manager PVD
at Unaxis Wafer Processing. “Our
customers tell us that sales of power
semiconductors are outperforming the
overall semiconductor sector. The total
market for semiconductors is growing
at CAGR (cumulative average growth
rate) of 10 to 15 percent, while power
chips are experiencing 15 to 20 percent
growth,” said Benz, adding that some
customers are predicting even higher
growth rates.
Market research firms unfortunately
do not track the impact of thin wafer
processes on the power semiconductor
market. Their reports on the power
semiconductor market lump standard
chips with thin chips. Furthermore,
market research firms tend to group
power management chips with power
semiconductors.
With this in mind, the market forecasts
are nevertheless impressive. Worldwide
shipments of power supply and power
management integrated circuits were
over 5 billion in 2003, and are expected
to increase at an annual growth rate of
8.8%, reaching close to 7 billion by 2006,
according to Venture Development
Corporation, a market research firm,
in a report published in January 2003.
Analysts at Intex Marketing Services,
supported by World Semiconductors
Trade Statistics and the Semiconductor
Industry Analyst, forecast 9% in 2004
and a growth rate of 12% for power
semiconductors next year.
5,456.6
5,088.1
6,000.0
4,000.0
2,000.0
–
1999
2000
Figure 3: Total available power
semiconductors market
worldwide
Source: World Semiconductors
Trade Statistics (WSTS) 2003
2001
2002
2003
2004
2005
2006
Table 1: Thin wafers
provide the technology
base for emerging bipolar
transistor IC applications.
Battery charging and management
New battery chemistries affect the charge control and
protection requirements. In addition, there is a need for
better fuel gauging and data collection on battery voltage,
current, and temperature. These drive demand for better
control ICs fabricated on thin wafers.
Telecommunications
The emergence of 2.5 and 3 G mobile telephones and
base stations. These mobile standards require more
power management content – in the form of battery
management and charging ICs – as well as improved RF
power devices, enabled by ultra-thin wafer technology.
Automotive
A modern mid-size car might contain up to 50 ICs. The
trend to greater electronic content is pushing the move
toward 42V power systems, creating a new higher margin
business line for chip-makers, especially those using thin
wafer processes.
Market drivers
Power semiconductors convert and control
the electrical current that powers virtually
every electronic device, from automotive
systems, consumer electronics, computer
motherboard and peripherals, electronic
office equipment, and industrial products
to telecommunication and networking
equipment.
According to a recent article in Solid
State Technology (Oct. 2003), the power
segment has performed better than
other areas due to improvements in the
resistance of the transistor in its on-state.
This value needs to be as low as possible
to improve current carrying capability
and to minimize power consumption.
A thinner wafer is one way to achieve
this. For integrated circuit manufacturers,
control of lower quiescent currents with
tighter tolerances plus integration of
multiple voltage output functions onto
one chip are the drivers of the adoption
of a new process in power semiconductor
manufacturing.
Table 1 shows where thin wafers can
help meet demands for emerging bipolar
transistor IC applications.
Early adopters
So who are the early adopters of thin
wafer processing? Power semiconductor
suppliers who ship diodes, IGBTs
(Insulated Gate Bipolar Transistors),
and MOSFETs made from thin wafer
dies, such as Fairchild Semiconductors,
Infineon AG, International Rectifier Corp.,
Agere (a spinoff of Lucent Corp), Royal
Philips Semiconductors, Ixys, and
ST Microelectronics.
These vendors do not say publicly
whether or not growth in sales is being
driven by product features enabled by
J A year ago, Agere Systems announced a new line of RF power transistors
made using a thin wafer process targeted at the mobile communications
base station market segment. The RF transistor is the key active building
block on power amplifier circuit boards. The transistor boosts signals of
voice, data, and video in various frequency ranges before the signals are
delivered to wireless subscribers.
J Agere describes the new line as the “World’s Coolest Wireless Power
Transistors.” It also said that the chips could save “billions of dollars
annually for wireless service providers.”
J Its customers apparently agree because Agere has made progress in
winning new contracts. In January of this year, Agere announced it is
delivering the high-performance RF power transistors to NEC for use in
the company’s third-generation wireless base station equipment. “These
devices enable NEC’s base station amplifiers to remain cooler, thereby
simplifying product design and improving its reliability,” said Agere in a
statement.
J “The use of Agere transistors in our base stations will accelerate our
company’s 3 G wireless equipment deployment during the next few
years,” said Dr. Nobuhiro Endo, general manager of NEC’s Mobile and
Wireless Division in the same release.
J According to Carlos Garcia, vice president and general manager with
Agere Systems, “NEC’s selection of our products validates Agere’s ability
to produce and deliver high-performance RF transistors to an industry
leader in deployment of operational 3 G base station equipment.”
J A second customer win was announced in the same month. Agere said
that Sewon Teletech, Inc., the largest supplier of power amplifiers to
wireless and repeater original equipment manufacturers in Korea, was
also adopting the RF devices.
thin wafer processes, partly because they
do not want to let the competitors know,
but also because the factors influencing
market demand are complex.
According to Andreas Sperner of Ixys
Corporation, whose firm has gradually
introduced this process over the last one
and a half years for a certain type of diode
product range, it is difficult for power
semiconductor suppliers to say whether
or not recent growth has been spurred by
the use of thin wafer dies, because there
is an overall upswing in the market.
“The last boom ended about two and
a half years ago, followed by a market
recession. For the past 8 or 9 months we
Valerie Thompson
MSc., has been a
freelance business
and high-tech writer
for more than 10 years.
A Canadian based
in Zurich, she tracks
the trends and
developments of
Europe’s purveyors
of advanced
technology.
Analog semiconductors
vendor ranking
1. Texas Instruments
2. STMicroelectronics
3. Infineon
4. Analog Devices
5. National Semiconductor
6. Philips Semiconductors
7. Freescale Semiconductor
8. Toshiba
9. Maxim
10. Fairchild / Intersil
Source: Databeans
see a strong general market increase,
but how much new thin wafer products
contribute to the increase is very difficult
to say. However, I can say we are seeing
continuous growth for this product
range,” commented Sperner.
Analog chip vendors might be keeping
the sales impact of thin wafers secret,
but their adoption of the process in the
fab speaks loudly in favour of it. Moreover,
announcements of plans to try to produce
even thinner wafers suggest that the
semiconductor industry is convinced of
the benefits in terms of cost savings and
performance boosts afforded by the
process.
Unaxis Chip | 9
Feature
Cool Base Stations
Advanced Packaging
APiA’s new
Virtual Process Line
Advanced Packaging
Dr. Christian Linder
PVD Process Technology Manager
Wolfgang Radloff
Marketing Manager
Since the foundation of the APiA – Advanced Packaging and Interconnect
Alliance – back in December 2001, both the consortium and the individual
member companies have increased the momentum towards comprehensive
and risk-free packaging solutions. By introducing the “Virtual Process Line,”
the APiA is now moving forward with the worldwide commercially available
process integration.
Goals and benefits
Advances in the semiconductor
packaging industry require productionproven high-volume manufacturing
solutions within a certain framework of
standardized processes. APiA’s answer
to this is the “Virtual Process Line”
featuring the following objectives:
J Demonstrate individual tools
J Demonstrate multiple technologies
J Provide a commercial offering for each
process
J Provide a platform with flexibility for
integrated process developments and
equipment evaluation aiming at
manufacturing solutions
J Appropriate IP protection of all
technologies involved
The APiA “Virtual Process Line” offers the
process sequence in a partly distributed
setup. Process steps with a strong
interdependence are clustered in single
locations for process integration and
quick response. This setup ensures the
most recent tool and process features
will be deployed.
In Figure 1 a simplified process flow
is shown with the corresponding single
fab locations of the APiA members.
Process technology portfolio
The introduction of wafer-level packaging
(WLP) has mainly been driven by form-
10 | Chip Unaxis
factor needs. During the last years, this
development spread along the dimension
of device type, from work station MPU, PC
MPU, certain chip sets, graphics devices
to high end ASICs and DSP chips. Volume
being the second dimension for growth,
it is expected to develop very quickly.
An estimated 10% of today’s 130 nm
products uses WLP solutions, growing
to a predicted rate of more than 80% at
the 90 nm node.
Wafer bumping for flip chip applications
is a key technology in the field of WLP.
Passivation layer
& pad opening
Two major bumping processes being used
in the “Virtual Process Line” are solder
plating and solder printing. In both cases
the under-bump metallization (UBM)
based on sputter deposition is an
essential step in the process flow.
Typical UBMs for plating are film stacks
such as Ti-Cu or TiW-Cu, while in case
of printing Al-NiV-Cu or Ti-NiV-Cu are
often employed.
In addition to the traditional solder
bump, the “Virtual Process Line” will also
cover lead-free bumping technology.
Metal patterning
Polyimide coating
& pad opening
Clean etch &
redistribution metal
Clean etch &
under-bump metal
UBM deposition
Stress buffer cure bake
X-Ray inspection
Switzerland
MN, USA (Optional)
CT, USA
Photopolymer,
coat / bake /develop,
stepper photolithography
PR strip & clean,
UBM wet etch
Bump shear inspection
United Kingdom
MN, USA
CA, USA
Die-bonding for flip-chip
Inspection after develop,
solder deposit, bump
height
Austria
Solder plating
Figure 1: Equipment
lab locations of the
“APiA Virtual Process
Line” (sequence
depending upon
process type). APiA
executive members
are: August, Ebara,
Steag Hamatech,
Ultratech, and Unaxis.
MN, USA
De-scum
Solder screen-printing
(Alternative option)
CA, USA
D-Tek Technology Co., LTD
Solder re-flow
Taiwan
NJ, USA
Typical lead-free material combinations
are Sn /3.5 Ag or Sn /3.8 Ag /0.7 Cu.
Regarding the UBM, it is possible to
utilize well-established film stacks like
Ti-NiV-Cu with minor adaptations such
as increased film thickness for the
NiV-Cu part.
A further focus of the “Virtual Process
Line” is the post-passivation layer (PPL)
technology comprising dielectric and
metal films and structures above the
standard IC process. Examples of
such WLP applications include the
redistribution layer (RDL) technology,
on-chip passives, or thick metal lanes.
RDL technology is used for re-routing
of the bumps from the perimeter to other
locations of the chip surface allowing
a more relaxed pitch. The process
involves a first passivating organic layer
(e.g. polyimide (PI) or BCB) with openings
to the peripheral bond pads, followed
by a metal deposition (e.g. sputtering
of Ti-Al or Ti-Cu) and etch, and finally
second passivation on top with openings
to the bump pads. Figure 2 shows a
redistribution layer and solder bumping
process flow; for each step the
corresponding APiA member is also listed.
Above-chip passive components
are used, for instance, in capacitors
consisting of thick dielectric layers with
top and bottom metal electrode films.
Cu layers patterned as planar (spiral)
inductors are another example.
Thick Al or Cu films ranging up to
several microns are gaining interest for
reliable high current flow as for instance
needed in on-chip power distribution.
Such metal lanes can be fabricated
either by a sputter seed followed by a
plating step (e.g. for Cu) or in one sputter
deposition step (e.g. for Cu or Al with
a thickness range of 3 – 5 µm).
Advanced Packaging
Japan
For more information please contact:
christian.linder@unaxis.com
Figure 2:
Redistribution layer
and solder bumping
process flow
(cross sections
not to scale)
Thick photoresist
& pad opening
Solder electroplating
Thick photoresist removal
& under-bump metal etching
Solder reflow
Bump inspection
Unaxis Chip | 11
Advanced Silicon
Towards Zero Handling Defects
®
With Unaxis CLUSTERLINE
Unaxis launches a new generation of CLUSTERLINE® PVD systems.
Alex Nef
®
Product Manager CLUSTERLINE
Based on the successful CLUSTERLINE ® 200 and 300 systems, the new series
maintains all the strengths of the current systems – proven and reliable processes,
high throughput – while featuring significant improvements and innovations in the
areas of wafer handling, accessibility, integration, and serviceability.
New CLUSTERLINE® handling system
Inspection
Buffer
Advanced Silicon
Pre-Heat
Our new generation now offers a number
of benefits for our customers:
J Higher uptime, lower scheduled
maintenance time
J Increased reliability and extremely safe
wafer handling
J Higher throughput
J Shorter delivery
J Faster installation and ramp-up to
production
J Easier serviceability
All above improvements result in lower
cost of ownership (CoO).
Degas
Aligner
Cooler
Figure 1: Pre and post
processing units are
freely configurable.
14 | Chip Unaxis
The CLUSTERLINE® 200 and
CLUSTERLINE® 300 are high volume
production systems, one for wafer sizes
of 150 to 200 mm, the other for 200 and
300 mm wafers. They are the leading
production solution for wafer level
packaging (WLP), thin wafer processing,
RF MEMS (BAW), and Interconnect
applications.
The main new features
New transfer chamber
J Unaxis introduces the first
vacuumcluster system featuring in situ
auto-teaching and auto-calibration,
about 10 times more accurate than
operator teaching and about 100 times
faster than all handling systems
available today. The functions can be
called off the menu in a simple automatic
task. Just imagine a system without a
teaching panel, no teaching wafers, and
not having to open the sputter module
for teaching at all. The system performs
these tasks automatically under
vacuum conditions.
J On-the-fly realign: every wafer motion
to or from any process module is
checked and the wafer is automatically
centered on each chuck. Smart software
New load lock
J Wafer mapping and automatic home
position detection: the wafer mapping
detects critical situations in the loadlock
like cross-slotted wafers, excessive wafer
bow, and double-loaded wafers.
Mechanical tolerances are completely
compensated.
J Ergonomic load lock for 200 mm
cassettes for easy and reliable loading
of cassettes.
J Safe load lock door design, CE compliant
without any interlocking.
New support system
J Latest state-of-the-art components,
like CTI IS 8F, are used on the Unaxis
CLUSTERLINE ® systems. This ensures
best availability and global support.
J The media distribution is designed into
the handler base, resulting in easy
Figure 2: The new
®
CLUSTERLINE
handling system,
showing the interface
to process modules.
installation, simple service, good
access, and easy system expansion
capability (Figure 2).
J Modular design leads to fewer individual
parts, the smart modules use distributed
I/O functions and a powerful Ethernet
bus to simplify the system, increasing
uptime and productivity.
J The functional and expandable
architecture of the system results in
faster delivery times and reduced ramp
up-time to production.
J Layout and installation distances are
greatly relaxed, and the footprint of the
system is reduced.
J The system is designed to meet the
newest ISO 14001 environmental
standards, conserving water usage
and energy.
It is highly exciting to see the many
features performing on our lab tool.
These innovative functions provide a
Advanced Silicon
anticipates arising problems and
prevents a transfer which could damage
a wafer. Wafer breakage is dramatically
reduced.
J The transfer chamber accepts six
process modules and additionally up
to six pre- and post-processing units
as plug-ins (Figure 1). Available plug-in
units are: buffer, aligner, cooler, pre-heat,
degas, and inspection. Double
configurations for increased throughput
are possible. The transport module is
prepared for new advanced features like
APC (Advanced Process Control)
inspection.
J Wafer size conversion is now an easy
task – changing the cassette size and end
effector is simple, the autoteaching does
the rest with just one click in the menu.
J On-the-fly wafer transfer verification
increases the handling throughput.
safer level of wafer handling, protecting
the high value of our customers’ wafers.
Customers will also benefit from higher
productivity, higher throughput, reduced
maintenance time and, increasingly
important, a faster and easier support
of their installed systems. The new
CLUSTERLINE ® system is setting new
standards.
The combination of new features
eliminates some complex tasks like
teaching and calibration of robots. This
and many other improvements make
the CLUSTERLINE ® systems easier and
better to work with.
Good partnerships and close
collaboration with our suppliers result in
an extremely short time-to-market for this
project – stay with us, there will be more
great news in the next Chip magazine.
For more information please contact:
alex.nef@unaxis.com
Unaxis Chip | 15
Advanced Silicon
Power Semiconductors
from Infineon
Backside Metallization by Unaxis
Advanced Silicon
Facts and figures about
Infineon Technologies
Austria AG
The Unaxis CLUSTERLINE ® 200 is the only
industry-proven high volume production tool for
backside metallization of ultra-thin wafers.
Dr. Reinhard Benz
Product Marketing Manager PVD
Villach may be just a small town in
Austria, but it is home to the world
leading competence center for power
semiconductors, where thin wafer
processing is the key technology.
Infineon established the facility in 1970,
and together with their production facilities
in Munich and Regensburg, Germany, it
forms a manufacturing cluster, called the
“PowerFab.” What makes Villach special
is the combination of production and
development at one location.
18 | Chip Unaxis
Infineon Austria develops and
produces semiconductors for
the Automotive & Industrial (AI),
Secure Mobile Solutions (SMS)
and Wireline Communications
(COM) business groups.
Additional R&D facilities are
provided by the Infineon
subsidiaries DICE and
COMNEON.
Total surface area:
158,000 m2
The relationship between Unaxis and
Infineon for backside metallization goes
back quite some time. Over ten years
ago, the collaboration started when
Infineon began to use Balzers
evaporators. Today, the processes on
ultra-thin wafers are transferred to several
6” and 8” Unaxis CLUSTERLINEs, which
are the “work horses” for backside
production.
Workforce:
2,600
(including 600 employed in R&D)
Sales /year:
EUR 533 million
(including DICE and COMNEON)
Production volume:
10.4 billion chips/year
R&D expenditure:
EUR 132 million
Ultra-thin wafer
(thickness 25 µm)
Technology and
photograph by
Fraunhofer IZM
Edgar Speidel
Director Module Management, Infineon
special attention to stress control of the
metal stack on the backside.
The Unaxis CLUSTERLINE® is the only
industry-proven production tool with
outstanding throughput performance on
8” wafers of more than 600 wafers per day.
The tools for wafer thickness below 100 µm
run with permanent high uptime of over
90%. The special Cluster Tool integration
allows us to add necessary pre- and
post-treatment steps like wafer cleaning
and the annealing to the Si backside,
which still results in typical throughput
figures of 35 – 40 wafers per hour.
Keeping ahead
The current collaboration with Infineon
is focused on the implementation of next
generation thin wafers.
An extremely wide range of different
products requires full flexibility for
backside metals with or without carrier
support to help manage the production.
The CLUSTERLINE® covers the full
range of wafer thickness from 700 micron
to the latest thin wafer generation.
For more Information please contact:
reinhard.benz@unaxis.com
“Infineon – as a major supplier to the highly demanding
automotive industry – knows the challenge thin wafers
pose between yield, throughput, and production
reliability. With the CLUSTERLINE ® Unaxis offers a
reliable solution enabling us to stay on the leading
edge of technology.”
Edgar Speidel, Director Module Management, Infineon
Infineon is a leading innovator in the international
semiconductor industry. We design, develop,
manufacture, and market a broad range of
semiconductors and complete system solutions
targeted at selected industries. Our products serve
applications in the wireless and wireline communications, automotive, industrial, computer, security,
and chip card markets. Our product portfolio
consists of both memory and logic products and
includes digital, mixed-signal, and analogue
integrated circuits, or ICs as well as discrete
semiconductor products and system solutions.
In Villach one of the main applications are Power
and Automotive Products. In this business the
needs of the customers are the driving power for
product development. In a modern car the number
of electronic components has been increasing at
accelerated speed, mainly for comfort and security.
Air-condition, Global Positioning System (GPS),
Airbags, Antilock Brake System (ABS), fuel injection
as well as infotainment systems have become
standard or will be in a few years.
Therefore, the reliability, the speed, and the power
consumption of each individual component are,
alongside cost and time to market, crucial for
success. To stay at the leading edge co-operations
with strong partners are vital. One of the challenges
is the trend to larger substrate diameters with
reduced substrate thickness. Handling of these
wafers and processes with excellent stress control
are key to success.
Infineon Technologies Austria AG has a long history
of working together with first Balzers and now
Unaxis for backside metallization. Unaxis has a
strong technological background on metallization
equipment and materials.The CLUSTERLINE® is
a production tool offering good solutions to the
production challenges. Infineon and Unaxis together
develop the tools to meet current and future
challenges.
Unaxis Chip | 19
Advanced Silicon
The CLUSTERLINE® at Infineon’s
“PowerFab”
The product range at Infineon Villach
covers all types of discrete devices based
on IGBTs, MOSFETs, or bipolar transistors
for products like drivers, converters,
transceivers, or switches typically used
for power management in power supply
or automotive systems.
Especially the power semiconductor
technology out of Villach’s “PowerFab”
is always one step ahead of the market,
adding more features, performance, and
functionality to devices while reducing
manufacturing costs, i.e. eliminating the
costly EPI layer to form the back
metal electrode.
Regardless of whether the next
generation of power devices is driven
by cost or technology for higher
performance, wafers will have
thicknesses of around 100 µm and even
below. This is where Unaxis comes into
the picture and sets a clear milestone
in the cost of ownership for wafer
breakage, throughput, and process
capabilities. Backside metallization of
ultra-thin wafers below 200 µm requires
a dedicated handling system and
Advanced Silicon
Unbeatable RAM: Reliability –
Availability – Maintainability
The CLUSTERLINE® 200 wins the day at Philips Semiconductors Boeblingen
The relationship between Unaxis and
Philips Semiconductors Boeblingen goes
back many years. Since 1989, a first
generation CLUSTERLINE® has been
operating at Philips and five old “Balzers”
CLUSTERLINE® 9000 systems are
still going strong. What better
recommendation than a consistent,
reliable and cost-effective performance
for over 15 years!
Meanwhile, several competitor systems
were added to increase metallization
capacity, and – since the year 2000 –
Figure 1: The actual
availability of both
CLUSTERLINE® 200
systems (CLC 1 and
CLC 2) is permanently
between 90 and 95%.
two new Unaxis CLUSTERLINE® 200
systems.
In 2002, Unaxis started a reliability
improvement program to exhaust the
full potential of the tool, exploring the limits
of its performance capabilities. Philips
supported this project, since they were
also convinced their production costs
could be lowered significantly with all the
advantages of the CLUSTERLINE® 200.
In a benchmark test comprised of
reliability performance, throughput, process
results, and maintenance costs, a clear and
Maintenance availability Unaxis
100%
90%
80%
70%
60%
CLC 1
50%
CLC 2
40%
Plan
30%
20%
10%
0%
May Jun
Figure 2: Excellent
MTBFp rate for both
CLUSTERLINE® 200
systems, showing
a consistent
performance of
0 – 2 failures per
month.
Jul
Aug Sep Oct Nov Dec Jan Feb Mar Apr
MTBFp Unaxis
300
250
200
Hours
Advanced Silicon
Dr. Reinhard Benz
Product Marketing Manager PVD
The Unaxis CLUSTERLINE ® 200 helps our customers cut costs with
better reliability and throughput. Tests performed at Philips Semiconductors
in Boeblingen, Germany, showed that the Unaxis CLUSTERLINE ® 200
outperformed even the market leader’s product by far.
CLC 1
CLC 2
150
Plan
100
50
0
May Jun
16 | Chip Unaxis
Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr
measurable cost of ownership (CoO)
advantage for the CLUSTERLINE® emerged:
J System availability ranges consistently
between 90 and 95% (Figure 1).
J Excellent average MTBFp (mean time
between failures of productive time)
rate (Figure 2).
J 25 – 50% higher throughput over the
competition and quicker production
ramp-up after maintenance – resulting
in more than 700 wafers/day (Figure 3).
J Maintenance consumable costs for
electrostatic clamping, as well as ionized
sputtering are 80% less than the
competitor product.
J Process results are identical on
all benchmarked systems in terms of
film properties, defects, and device yield
compared to the competition.
The great success of the Unaxis
CLUSTERLINE® in Boeblingen has been
made possible by the outstanding
cooperation and close relationship
between all key players. Success was
insured thanks to Marco Padrun as Unaxis
Technical Project Manager and Wolfgang
Breyer as Unaxis on-site Service Engineer
and their extended and highly motivated
team comprising process, engineering,
and assembly. Also, special thanks to the
Unaxis service crew in Munich.
We are confident these superb data,
together with our impressive track record at
Philips Semiconductor Boeblingen, will
open new doors in the CMOS world.
Dr. Uwe Zimmermann,
Technical Team Leader CVD
+ PVD, Mico MIP, Philips
Semiconductors GmbH,
talks about the relationship
between Philips Böblingen
and Unaxis.
Mr. Zimmermann, Unaxis and Philips
Semiconductors Boeblingen have
worked together for many years.
What do you particularly appreciate
about the cooperation with Unaxis?
We appreciate the close partnership
and personal connection which has
developed over the years. Our colleagues
at Unaxis know our particular situation
very well and are therefore able to
respond to any problems which may
arise quickly and efficiently and meet
our exact requirements.
Philips Semiconductors GmbH Boeblingen
Originally IBM’s first semiconductor fab in
Germany (1968), Philips Semiconductors
GmbH Boeblingen has an impressive portfolio
of semiconductor know-how.
In 1988, the location is the first European
200 mm wafer fab, producing 4 MB memory
chips. In 1995, IBM enters a joint venture with
Philips (51% Philips / 49% IBM). 1998 saw
the last production of memory chips (16 MB),
and a year later Boeblingen became a 100%
daughter of Royal Philips Electronics, when
the portfolio was changed from memory to
logic products. In 2002, the Hamburg and
Boeblingen locations were joined in Philips
Semiconductors GmbH Deutschland.
Where do you see the main technical
advantages of the CLUSTERLINE®
compared to other systems?
It is a clear and simple piece of equipment,
concentrating on the technical essentials
without unnecessary frills. This means
low repair times and, of course, very
good uptime. The technical feature that
particularly stands out is the Leap-Frog
Robot on the handling system, which
speeds up operation significantly and gives
us continuously high throughput rates.
Semiconductors production:
CMOS IC production on 200 mm production
systems:
J Standard CMOS processes with structural
widths of 0.8 – 0.3 µm
J Medium voltage/high voltage CMOS
processes for LC/TFT displays
J LCOS (Liquid Crystal on Silicon)
J Embedded DRAM technology
Capacity: 300 million ICs per year
What feedback do you receive from
your operators and maintenance
engineers regarding the handling
of our system?
Our staff love the CLUSTERLINE® for its
reliability during high throughput and its
simplicity. Maintenance engineers are
very happy with the clean technical
solutions, but also point out that in some
areas the software could be improved.
Over the years, Unaxis and Philips
Boeblingen have realized many
projects together. Can you give us
a glimpse of future developments
and possible co-operations?
Together with Unaxis, we will install a beta
I-PVD module on the CLUSTERLINE®
here in Boeblingen in 2004. We are
looking forward to this project and the
easy cooperation of a tried and tested
partnership.
And beyond I-PVD?
A project on backside metallization
is in the planning stages, however, no
decisions have been made yet.
Throughput comparison CLUSTERLINE® 200 / competition
25
e.g. Ti-only
X
–
cooler
–
TiN
X
Ti-hot
e.g. Al metal
sec/wafer
590 25
32
X
118
AlCu
Ti
Competition
softech
Process
degas
Application
49
CL200
wafer/hour
sec/wafer
Difference
wafer/hour
%
30,5
93
wafer/hour
38,7
8,2
26,9
X
138
26,1
65
55,4
29,3
112,3
Figure 3: Throughput
comparison representing
typical liner and metal
interconnect layers. The
average throughput of
the CLUSTERLINE® 200
is 25% higher than that
of the competition.
Source: Philips
Unaxis Chip | 17
Advanced Silicon
Interview
How do these technical features help
you reach your own targets?
We can rely on the CLUSTERLINE® to
maintain high throughput rates at all times.
The average wafer throughput per month
is nearly 25% higher than the tool of a
large competitor. This is essential to reach
our production targets, which is also a
contributing factor towards reaching our
financial goals – as are the reasonable
prices for spare parts.
Photomasks
®
The Unaxis MASK ETCHER IV
Keeps its Promises
Emmanuel Rausa
Technical Marketing Manager
Some of you may remember reading in our previous issue, Chip 9 (Sept ’03),
an article entitled “65 nm Dry Etch: the Future of Photomask Has Arrived.”
It introduced notions which are particular to photomask applications. This article
presented progress made by Unaxis Wafer Processing for photomask Cr etching
from 1995 to date. Improvements from one generation to the next were most
impressive. The progress achieved for each single node has allowed Unaxis to
take and keep the well-deserved number one position in the photomask market.
Cr etch results update
In Chip 9, we presented unmatched etch
results of 32 nm bias and non-uniformity
of 12 nm, 3 σ on the very demanding
one window Ybor test masks. The Ybor
masks were designed to be extremely
challenging. There is nothing quite like it
in the industry. Unaxis knew this, but
wanted to make sure it could deal with
the worst-case scenario, and indeed it
Photomasks
Figure 1: Typical
®
MASK ETCHER IV
etch signature for
Cr layer on a gate
level photomask
worked. When it was time to revert back
to the customers’ real mask, all our hard
work paid off. Unaxis again demonstrated
great results! This was achieved on many
different applications such as masks
for memory, chip manufacturers,
merchants, and foundries. The Unaxis
MASK ETCHER ® IV has shown the
following results: for memory, an etch
bias of 7 nm with non-uniformity of 4.4 nm;
Gate level
etch contribution
iso clear feature
deviation from average
30.00
15.00
7.50
–15.00
–30.00
Average: 12.56
3 Sigma:
3.04
Max:
14.60
Min:
8.60
Range:
6.00
20 | Chip Unaxis
for gate level chip manufacturer mask
products, the etch bias is 13 nm with a
uniformity of 3 nm (Figure 1). These results
have been demonstrated on customersupplied parts and are representative of
the Unaxis MASK ETCHER ® IV typical
loads for these customers. Meanwhile,
other etch parameters have been kept
constant or improved.
Specification in question
Unaxis often hears machine specifications
are too loose to compare to results
actually achieved on production
photomasks. Why does Unaxis not sell
the MASK ETCHER ® IV with such low
specification numbers? Surely, this can
only help the sale process? The three
major reasons for this will be discussed
in the following paragraphs.
Customers send very challenging parts
which may not be representative of their
production for demonstrations of Unaxis’
equipment performance. By overstressing
a problem, they can be assured their
production will run smoothly. Other
customers, specifically merchants, have
a variety of masks to produce which do not
have typical plates for them. The diversity
of products for merchant customers is
so great, some of them have the need to
create their own internal standards.
Etched quartz
(180° out of phase)
Quartz (clear)
Reticle
Quartz
Reticle
Chrome
Chrome (opaque)
Phase
(Energy)
Phase
(Energy)
+
–
Intensity
(Energy 2 )
Resist threshold
Intensity
(Energy 2 )
Resist threshold
Wafer
Remaining resist
after develop
Wafer
Remaining resist
after develop
Source: ASML
contribution, due to process or hardware
contributions. In turn, this is used to
our customers’ benefit because we can
match every tool before shipping. This
helps us identify possible hardware issues
before tool acceptance, and minimizes
customer cost in process integration
when placing repeat orders.
Current limitations of binary masks
Dimensions on the photomask surface are
four times those of the wafer dimensions
to be printed. This magnification helps
ease manufacturing constraints. The
current technology is still using the
magnification, however the use of OPC
(Optical Proximity Correction) is now
necessary due to light diffraction in feature
sizes smaller than stepper wavelengths.
OPCs are nothing more than known
diffraction features. They are carefully
designed and placed to restore the image
of the main features which the chip
designer intended to have on the wafer.
The introduction of these OPCs is the
reason behind an acceleration in
photomask roadmap requirements and,
eventually, in the price of the mask set.
But OPCs are not enough anymore.
There is need for a more sharply defined
image at the wafer level. In other words,
improved contrast is needed at the feature
edge. This can only be achieved by
playing on the phase of the light. Phase
Shift Masks or PSMs do just that. Figure 2
demonstrates the schematic of the
phase change on the photomasks. There
are several types of PSMs which can be
attenuated or alternated, requiring etching
of a Cr layer first.
Photomasks
The second reason for Unaxis not
to exaggerate performance is because
measured results are not just etch
contributions. Built into these results are
many variables, errors and noise which
cannot be easily separated from the
manufacturing process itself. For
example, the noise of the CD SEM
(Critical Dimension SEM) metrology tool
is embedded in these results. Another
issue unaccounted for is the resist profile
distribution across the plate. If the resist
is more sloped at the center of the plate
than it is at the edge, this will affect the
final Cr results and could be interpreted
by customers as a contribution from the
MASK ETCHER®.
Last, but not least, having a Unaxis
standard yet challenging plate helps
us build an extensive database on etch
Figure 2: Light phase
shift through binary
Cr mask and
alternated aperture
phase shift mask.
Unaxis Chip | 21
Figure 4: SEM cross
sections showing the
profile of quartz etch
®
on MASK ETCHER IV.
To the left, with Cr intact
on top of quartz, a one
micron feature. To the
right, quartz only, a
feature size of 350 nm.
Quartz etch in the industry
Alternated PSMs combined with
immersion lithography have the potential
to extend current photomask technology
usage down to less than 30 nm at the
wafer resist level. However, due to
manufacturing and inspection issues
and therefore yield and costs, the
industry has been using PSMs with great
reluctance so far. Despite these issues,
quartz etch is the only current solution
to the technical challenges.
Photomasks
Specific challenges in etching quartz
Quartz etching has challenges of its own
which are not encountered with Cr or
MoSi layers. For quartz, one etches
directly in the mask substrate. Feature
sizes on each mask surface must be
controlled, along with the etch depth of
the quartz features. This adds a third
dimension to etch control. Challenges
such as etch depth linearity and
uniformity must be addressed. Both
are important to control the phase of
light passing through the mask during
wafer exposure in the stepper. In order
to get the same phase change at the
mask, the etch depth into the quartz
substrate needs to be independent of
two parameters.
Etching depth uniformity and linearity
First, the depth of quartz needs to be
the same regardless of the location on
the plate. This is commonly referred to
as uniformity. Second, the depth of the
trenches in the quartz must also be the
same, regardless of their dimension or the
shape of the feature. This is called etch
depth linearity and is a critical parameter,
conversely a lack of depth linearity is called
“RIE lag” and is undesirable. It is particularly difficult to get a process which
delivers depth linearity in the semiconductor industry. In everyday words,
it is easy to understand: one wants to etch
to the same depth in the same time,
regardless of the volume of material to
remove. Of course, the quality of the trench
Figure 3: Quartz etch
imperfections
Quartz bump
Sloped side wall
Surface
roughness
RIE lag
Micro-trenching
needs to be constant. There should be
straight sidewalls with no micro-trenching
surface roughness. Please see Figure 3
for unwanted features on quartz etch.
Etch results on the MASK ETCHER ® IV
Unaxis’ MASK ETCHER ® IV has proven
to be an excellent tool to solve these
challenges and has demonstrated linearity
results below its internal metrology
capabilities. Unaxis process engineers
have been using an Atomic Force
Microscope (AFM) and have measured the
etch depth linearity to be within the noise
of the AFM instument itself. As shown in
Figure 4, the etched features are very clean
and straight. Roughness is below 1 nm
RMS, and there is no visiblemicrotrenching.
What next?
The Unaxis MASK ETCHER ® IV was
developed for photomask etching with
the latest technology needed to improve
the process window. Ongoing process
work continues to provide our customers
with the latest process improvements
for their production needs.
For more information please contact:
emmanuel.rausa@unaxis.com
22 | Chip Unaxis
Compound Semi & Microtechnology
Figure 1: LLS EVO II
More Customer Benefits
from the new LLS EVO II
Batch sputtering system for advanced packaging and compound semiconductor
to-cassette auto handling, the LLS covers
an extremely wide range of applications at
customer sites around the world.
Continuous product evolution
Over the past five years, a lot of
information has been collected from our
customers, but also from our application
and service engineers, regarding potential
improvements to the existing LLS EVO.
The resulting wealth of experience and
ideas, plus the requirement to optimize
the LLS EVO II (Figure 1) for supply chain
aspects were the key drivers for this
re-design. Proven modules like the
vacuum chamber, the sputter sources,
degas, RF etch and ion milling have not
been touched to maintain process
compatibility with the LLS EVO.
Compound Semi & Microtechnology
Hubert Breuss
Product Manager
Batch Sputtering Systems
The load lock sputter success
The first LLS was built in 1979. Since
then, over 240 LLS systems have been
successfully installed, more than 100
of them are LLS EVO. Twenty-five years
of process reliability in R&D and
production from this Unaxis product –
some of our customers are still ordering
retrofits for first generation LLS 800
systems! With its high flexibility regarding
target materials and substrate size,
with its excellent film uniformity and
reproducibility, co-sputtering, its simple
operation and easy maintenance, the LLS
encountered steadily increasing demand
in the market. Many new applications
could be won thanks to professional
sample work with fast turn-around. From
laboratory to production with cassette-
Unaxis Chip | 23
Figure 4: LLS EVO II
with reduced front
panel width
What is new on the LLS EVO II – what
has changed?
Media supply
Water (Figure 2): Service and maintenance
of the water battery have been simplified.
The completely reworked water battery is
one of the three main modules. Start-up
time at customer site has been reduced
due to the fact that all interfaces between
rack cabinet, water battery and vacuum
chamber are now equipped with fast plug
connectors. Pneumatic valves and the
flow-meter are controlled via “Profibus”,
screw couplings are realized
in stainless steel. Steering and power
cables are separated in defined positions
and the decentralized periphery results
in less cables.
Water input and output pressure are
controlled with a manometer and all water
pipes are equipped with plug connectors.
Each cathode has a separate water supply
with flow-meter indicating actual values,
the water pipe diameter has changed
from 3 /4” to 1.5”. “Blow out” of the water
supply (pipes and cathodes) during
target exchange is now standard, and
the operation is very user-friendly.
Gas (Figure 3): By changing the analog
control system to the digital “Profibus”
interferences of the Mass Flow Controllers
(MFC) could be eliminated. The new
digitally controlled MFC allowed a
reduction in the large variety of MFCs to
two sizes (50 sccm, 200 sccm), calibrated
for all process gases (Ar, N2, O2 and H2)
used in the LLS EVO II.
Compound Semi & Microtechnology
Front panel
The front panel width could be reduced
by more than 15% from 2.5 m to 2.1 m
(Figure 4). User functionality has been
optimized and simplified with a new
keyboard including trackball and an
integrated flat panel display. The function
“DOOR UP” has been implemented
and is controlled via the Graphic User
Interface (GUI) software, “CAGE
ROTATION” is integrated in the left
“DOOR DOWN” button.
Figuer 2: Completely
re-worked water battery
24 | Chip Unaxis
Figure 3: “Profibus”controlled gas battery
Rack cabinet
The new optimized rack cabinet also
contributes to a reduction in floor space
Features of the LLS EVO II
Figure 5b: Media
supply of the LLS
EVO II
Figure 5a: Rack cabinet
with integrated flat panel
display
of over 10%. The rack modules (power
supplies, RF generator, PCs) are now
located to the left of the control rack.
The power rack, which also includes
the space for the control and power units
of the optional auto handler, is located
immediately to the right. Both doors of
the power rack can be opened from the
front, so the only space required behind
the control and power racks is for the
media supply (Figure 5b). The new
arrangement of the rack cabinet is shown
in Figure 5a. Also new and very handy is
the flat panel display integrated into the
Highest process flexibility – each of the five
sources can be configured for any of the
following options:
DC Sputtering: conductive materials
and low doped reactive processes
RF Sputtering: dielectric materials and
high doped reactive processes
RF/DC combined sputtering: increased
rate for reactive sputtering
Pulsed DC sputtering: improved
performance of low and high reactive
processes also stress control for pure
metals (e.g. Cr, NiV)
Co-sputtering: increased rates or
individual mixtures of alloys (up to three
cathodes)
Load lock chamber for degassing; RF or
ion beam etching assures clean surfaces
and good adhesion.
front panel of the control rack together
with a stow-away keyboard.
Graphic user interface
The GUI (Figure 6) has been completely
re-designed and is now state-of-the-art
with a Windows XP operating system,
making recipe view and run protocol much
more user-friendly. A SECS/GEM interface
is available as an option.
A unique valve separates the load lock
and main chamber to avoid particles and
gaseous contamination, maintaining
repeatable process conditions.
Moveable shutter between the sources
eliminates cross-contamination and allows
pre-sputtering (shutter closed) as well as
co-sputtering.
Vertical sputtering generates fewer particles.
Optimized rectangular cathode design for
highest field homogeneity results in better
magnetic fields.
Easily convertible for different substrate
sizes and shapes (small pieces up to
standard 8” substrates, max. 200 x 200 mm,
frontside, backside loading).
High vacuum pumping systems are tailored
to specific process requirements.
Fully automatic cassette-to-cassette
handling (Figure 9) avoids potential
contamination through the operator (option).
Operator-friendly Windows XP-based
control system displays status and trends,
tracks and registers process information,
manages alarms and recipe handling.
Segment sputtering possible
Passive cooling enables processes <100°C.
SEGS /GEM interface (optional)
Corresponds with ISO14001
Figure 6: New graphic user interface
Unaxis Chip | 25
Compound Semi & Microtechnology
Different substrate sizes in same batch are
possible.
Equipment data
Substrate size
Up to 200 mm, square max 200 mm x 200 mm,
< 15 mm thick
Batch capacity
Front side loaded (round substrates)
75 mm
48 substrates
used for Soft PLC and GUI (Figure 7).
100 mm
36 substrates
Both rack module computers are located
125 mm
15 substrates
at the top of the control rack.
150 mm
12 substrates
200 mm
9 substrates
Compound Semi & Microtechnology
Backside loaded (round substrates)
50 x 50 mm
112 substrates (square)
75 mm
36 substrates
100 mm
30 substrates
125 mm
12 substrates
150 mm
10 substrates
200 mm
8 substrates
Deposition rate
dynamic
Au 200 Å /min (1 kW), WTi 180 Å /min (3 kW),
TaN 90 Å /min (1.5 kW), Al > 700 Å /min (10 kW),
Cu > 1000 Å /min (10 kW), Ti > 300 Å /min (8 kW),
Ni 240 Å /min (3 kW)
Magnet source
AKQ515 with 127 x 381 mm target
Heater
Degas LC – max 2 kW, power controlled
Process MC – max 4 kW, power controlled,
up to 350°C
Etching
RF etch >18 Å /kW min
Ion beam etch > 23 Å /kW min
Vacuum
Base press. LC < 5 x 10 E-7 mbar (CTI 8F onboard)
Base press. MC < 1 x 10 E-7 mbar (CTI 8F onboard)
Substrate handling
Manual or optional automatic cassette-to-cassette
Electrical data
3 x 400 / 230 V AC, 50 / 60 Hz, 30 kVA
Water
Cooling 18 – 25°C 60l /min
Compressed air
6 – 8 bar (87–116 psi)
Process gas
Ar, N2, O2, H2
Control unit
The reduction and optimization of rack
space were the main reasons to change
the control unit. The old Programmable
Logic Control (PLC) Simatic S7 has been
replaced by the latest Soft PLC version,
which is now running on a PC rack
module. Two independent computers are
26 | Chip Unaxis
Segment sputtering
In addition to dynamic sputtering,
segment sputtering is now possible as
well. The new rotary drive enables
sputtering of a specific segment, which is
particularly useful for laboratory use when
sputtering expensive target materials.
Service hoist
The new service hoist significantly
simplifies service and maintenance.
It is now integrated into the LLS EVO II
as a standard feature. In addition to the
substrate cage and the rotation engine
the new design now also allows removing
the LC pump and the LC high vacuum
valve.
Media consumption display
Power, water, Ar, N2, O2, H2 vent
nitrogen, and compressed air consumption
are now recorded and available as
current, monthly, and annual printouts
corresponding to ISO 14001.
Miscellaneous
The three main modules – water battery
(Figure 8), rack cabinet, and process
chamber on the platform with fixed
front panel – result in reduced installation
time at the customer and contribute
to simplified logistic processes.
Integrated and improved documentation:
DocuCat is an add-on module for
SPCat, which links all fields of service
documentation (operating instructions,
OEM instructions, and spare parts
catalog) into one database and integrates
them in a uniform control interface.
Figure 7: Optimized
control rack
Figure 8: Supply
chain module water
battery (on wheels)
Total reduced floor area: Due to the
reduction in width and the new optimized
rack cabinet, a total footprint reduction of
about 20% has been realized.
Improvements at protection shielding:
The modified anode frame protects the
anode flange from being coated. The
inside of the load chamber (LC) is now
fully shielded. The shutter box in the main
chamber (MC) has been modified to grant
a better gas flow distribution and pump
characteristic enabling better film uniformities, especially in reactive sputtering.
Regardless of the position of the various
cathodes, they perform more uniformly
when compared against each other –
another advantage of the LLS EVO II.
Benefits at a glance
Reduced footprint (–20%)
Lead-time reduced to three months
(with clarified system configuration)
New “Profibus”-compatible components
(Turbo Molecular Pump 1600, MFCs,
Dual DC pulsed generator, decentralized
periphery) replace all discontinued
components.
New water battery
Segment sputtering
LC door (open) software-controlled
Flat panel display in clean room and
grey room
New Graphic User Interface (GUI)
User-friendly process protocol and
recipe view
Soft PLC controlling unit
Simplified support
New optimized service hoist (standard)
Improved protection shielding
Supply chain modules
(simplified logistic)
New gas battery
Media consumption reporting
(ISO 14001)
Printer as standard
SECS /GEM Interface (option)
For more information please contact:
hubert.breuss@unaxis.com
Compound Semi & Microtechnology
All these benefits add up to quicker
assembly and installation, shorter service
times, and easier handling – contributing
to an increase in productivity and reduced
cost of ownership (CoO). The well-known
strengths of the LLS EVO have not been
compromised in the re-design, making
the Unaxis LLS EVO II a champion already.
Figure 9: LLS EVO II
with cassette-to-cassette
auto handling
Unaxis Chip | 27
Compound Semi & Microtechnology
Optimization of Low Stress
PECVD Silicon Nitride
for GaAs Manufacturing
Ken Mackenzie, Brad Reelfs, Mike DeVre,
Russ Westerman, and Dr. Dave Johnson, Unaxis Wafer Processing
Unaxis solutions for plasma-enhanced chemical vapor deposition (PECVD) silicon
nitride (SiNx) are used extensively in the production of GaAs devices. PECVD is
compatible with the low temperature constraints required for GaAs device manufacturing. With this technique, high quality SiNx can be deposited at temperatures less
than 400°C. PECVD SiNx is used in many different GaAs-based devices such as
MESFETs, HBTs, and HEMTs. In these devices, PECVD SiNx is typically used for
passivation, encapsulation, and as a capping layer. In addition, the large dielectric
constant of SiNx makes it attractive for use as the intermetallic dielectric in MIM
capacitors.
Compound Semi & Microtechnology
It is well recognized that the stress of
the SiNx layer in GaAs-based device
structures can impact the electrical
performance and lead to degradation.
For GaAs MESFET and HEMT devices,
it has been demonstrated not only
the magnitude of the stress but also
the stress state, compressive or tensile,
can affect the performance [1]. Stressinduced failure via microvoid formation in
SiNx MIM capacitors has also been
reported [2]. Therefore, the capability of
tailoring the magnitude and state of the
SiNx stress required for a specific device
structure is very important.
For SiNx, a common technique to
control the stress in a conventional
13.56 MHz parallel plate PECVD reactor
is through the addition of low frequency
power. At 13.56 MHz, SiNx films prepared
from standard gas mixtures of SiH4, NH3,
28 | Chip Unaxis
and N2 are typically tensile in nature. The
added low frequency (< 1 MHz)
component results in high energy ion
bombardment of the growing SiNx film.
This results in a change of the stress state
from tensile to compressive [3, 4]. At
Unaxis, a He dilution method has been
developed as a simpler alternative
technique to control the stress of PECVD
SiNx. As illustrated in Figure 1, the addition
of He to the standard gas mixture of SiH4,
NH3, and N2, enables stress control from
about 300 MPa, tensile through zero to
about –300 MPa, compressive.
Plasma-induced damage during the
SiNx deposition process, resulting in
physical and electronic degradation of
GaAs devices is a very important issue
[5–7]. Without the requirement of a low
frequency power source, the possibility
of damage is reduced with the He dilution
method. The RF power density at
13.56 MHz is very low and typically
less than 50 mW/cm2.
A designed experiment (DOE) was
implemented to characterize and optimize
a low stress SiNx process based on
the He dilution method on a Unaxis
PECVD production platform developed
for high volume GaAs manufacturing.
To understand the mechanism involved in
this technique for stress control, optical
spectroscopic analysis of different He/N2
plasmas in the PECVD reactor has been
performed.
Experimental
All the SiNx films were prepared on
100 mm Si test wafers from gas mixtures
of SiH4, NH3, N2, and He on a Unaxis
VERSALOCK ® PECVD system [8]. This
fully automated cassette-to-cassette
Figure 1: Stress
control of PECVD
Sinx by the He
dilution method at
the different rf power
levels indicated
400
Tensile
Stress [MPa]
200
0
0
20
40
60
80
–200
100
20 W
Compressive
50 W
100 W
–400
% N2 in (N2 + He) mixture
Figure 2: General
response trends
from DOE
➔
➔
➔
➔
➔
➔
➔
➔
Compound Semi & Microtechnology
Designed experiment results
In Figure 2, the general response trends
from the analyzed DOE are summarized.
The up and down arrows indicate the
directional change in the response resulting
from an increase in a process factor, NH3
➔
➔
➔
solution of 7:1 NH4F : HF was used for
the wet-etch rate measurements.
Etch
rate
➔
➔
➔
Power
Stress
➔
➔
% N2 / He
➔
–
NH3
➔
–
➔
Thickness
non-uniformity
➔
Dep
rate
➔
Index
➔
➔
Responses
Factors
system is capable of batch handling
eight 100 mm GaAs or five 150 mm
GaAs wafers. The PECVD reactor is a
conventional parallel plate configuration
and uses a 13.56 MHz RF power
source to generate the plasma. Wafer
temperature can be controlled over
a range of 100°C to 350°C. To obtain a
high yield and minimize system downtime,
several features in the PECVD reactor
have been implemented to maintain
system cleanliness. For example, both
the chamber walls and the upper gas
distribution electrode of the reactor are
heated to minimize particulate formation
during the SiNx deposition process.
In addition, an automated plasma
etchback sequencer interfaced to an
in-situ optical emission spectrometer
is used to achieve and consistently
maintain the reactor in a clean state.
Single wafer modules with either manual
or automatic loading are also available
for situations where batch processing
is unnecessary.
For process optimization, a two level
full factorial design on three factors
was constructed for the DOE. The
three factors were NH3 gas flow rate,
N2 /(N2+He) gas flow ratio, and RF power.
All films were deposited at 300°C.
The diluted SiH4 gas flow rate, process
pressure, and the combined N2 and
He gas flow rates were held constant
during the experiments.
The measured responses were
refractive index, deposition rate, thickness
non-uniformity, stress, and wet-etch rate.
The thickness non-uniformity is defined
as the thickness range divided by twice
the mean thickness expressed as a
percentage. The edge exclusion was
6 mm. A buffered oxide etch (BOE)
gas flow rate, N2 concentration in He,
or RF power. Double and single arrows
respectively indicate a strong or weak
dependence of a response on a factor
over the range investigated. All three
factors have a major influence on the SiNx
film stress. The measured film stresses
ranged from about 300 MPa, tensile to
about 400 MPa, compressive.
Unaxis Chip | 29
Stress control mechanism
Examination of the optical emission
spectra of the deposition plasma provides
important insight concerning the
mechanism responsible for compressive
stress by the He dilution method. Shown
in Figure 5 are two 13.56 MHz plasma
spectra, pure N2 and 10% N2/He. These
correspond to deposition conditions
associated with tensile and compressive
films. Emission lines at 391.4 nm and
427.8 nm are present in the 10% N2/He
plasma and are absent in the pure N2
plasma. These two lines are assigned to
N2+ ions and indicate its presence in the
10% N2/He plasma. As shown in Figure 5,
these N2+ spectral lines are also present
in a 380 kHz N2 plasma without any He
dilution. SiNx films prepared from SiH4,
Figure 4: Overlay plot
for an optimized low
stress SiNx process.
Non-shaded area is
the optimized
process regime.
Point in center
denotes center point
of the design.
20
% N2 in (N2 + He) mixture
< 100 MPa
18
16
Index: < 2.05
Index: > 2.0
14
< -100 MPa
< ±2.5%
12
10
–1.0
–0.5
0.5
0.0
1.0
40
N2+
N2+
Compressive
30
Tensile
30 | Chip Unaxis
Film parameter
Range
Stress (MPa)
–100 to +100
Refractive index
2.0 to 2.05
Thickness non-uniformity (%)
< ± 2.5
Wet-etch rate (Å /min)
> 300
100% N2
LF: 380 kHz
100% N2
13.56 MHz
20
N2+
10
N2+
Compressive
Figure 3: Criteria for
low-stress SiNx
process optimization.
Figure 5: Optical
emission spectra for
various plasmas.
Spectra are
displaced vertically
for clarity.
Relative NH3 flow rate
Plasma intensity
Compound Semi & Microtechnology
Low stress optimization
Figure 3 summarizes the typical customer
property requirements for a low stress
SiNx film. Figure 4 maps out the predicted
process space from the DOE for these
criteria as a function of NH3 gas flow rate
and N2/He concentration in the plasma.
These results clearly indicate a practical
process regime exists to achieve a lowstress silicon nitride film to meet the
desired criteria. The deposition rate
for the low stress films is greater than
100 Å /min. Faster deposition rates are
possible with either higher RF power or
more concentrated SiH4.
0
360
380
400
420
Wavelength [nm]
10% N2 /He
13.56 MHz
440
460
Compound Semi & Microtechnology
High Performance Oxide Etching
on the new VERSALINE™ Platform
Dr. Dave Johnson,
Director of Research
& Development
Silicon dioxide is used in the manufacture of many types of devices, both semiconductorbased and other, where it is chosen because its physical properties can meet the needs
of a wide range of applications. For example, its excellent electrical properties as an
insulator and dielectric make it suitable for use in the fabrication of capacitors and as an
inter-level dielectric material. It finds use in applications such as MEMS and hard drive
head construction, where its mechanical strength and good chemical resistance can make
it the material of choice. The optical properties of silicon dioxide (both as a thin film and
as bulk quartz) lead to its extensive use in the production of optical devices such as
photomasks, micro-optics, and waveguides.
Compound Semi & Microtechnology
Silicon dioxide can be deposited as a
thin film by various techniques including
flame hydrolysis at atmospheric pressure,
CVD, PECVD, and sputtering. For some
applications, a deposition step alone is
sufficient, but more commonly the
deposited film is subsequently etched to
define features into the oxide. Because of
the many different uses of silicon dioxide,
it is not surprising that the requirements
of the etch process are highly variable.
Thus, feature sizes may range from submicron to millimeter and etch depths
from less than 100 nm to greater than
100 micron. The required etched profile
varies from highly vertical to highly
sloped, and different mask materials,
such as photo-resist and various metals,
are used. The substrate material includes
silicon, metals, ceramics, and quartz in
various shapes and sizes. Fulfilling these
requirements places a severe demand on
the etch process and platform, with some
apparently mutually exclusive constraints.
However, since silicon dioxide is used
to some degree in all of the Unaxis
targeted market areas, solving these
issues and developing an oxide etch
solution has presented a key challenge.
32 | Chip Unaxis
Parameter
Minimum
Maximum
Etch depth
< 1 µm
> 100 µm
Etch rate
< 1000 Å /min
> 1µm /min
Etch rate uniformity
< 2%
–
Selectivity (to photo-resist)
<1:1
> 10 : 1
Selectivity (metal mask)
–
> 50 : 1
Wall profile
Replicate mask profile
90°
Substrate size
2 inch
200 mm
Substrate type
Silicon
Quartz, ceramic, metal
Table 1: Oxide etch,
range of requirements
RF
2 MHz
Substrate
Gas inlet
High density
plasma
Vacuum
Temperature-controlled
electrode
RF
13.56 MHz
Figure 1: Inductively
coupled plasma
process module
T °C
150
140
130
120
ICP = 1000 Watts
110
100
90
80
70
60
50
40
30
oxide surfaces the presence of -O tends
to oxidize any polymer and the surface
remains clean and continues to etch. Using
H2 or H-containing fluorocarbons as the
polymer promoting additives, it is possible
to increase the oxide:resist selectivity
ratio to values of 10 and higher. However,
the polymer also tends to deposit on
other plasma-contacted surfaces, which
ultimately leads to flaking, particle
contamination, and excessive downtime
for cleaning. The deposition can be
eliminated by elevating the temperature
of these surfaces above the polymer
condensation point, and this may be
150°C or higher, depending on the process
conditions. This temperature must be
maintained, even when the plasma is off,
to ensure long-term process stability.
Hence, the requirement of selective etching
drives the need for high temperature
operation and control. This, plus the need
for high power operation, represents the
major challenge in designing a flexible oxide
etch process.
Figure 2: CFD model
showing ICP source
temperature
Hardware design
Based on the above requirements,
the design of an oxide etch module
becomes primarily an exercise in thermal
management. One of the first steps was
to understand the heat balance in terms
of power-deposited (from the plasma)
versus heat-loss pathways. Temperature
measurements and a calorimetric analysis
were used, and the data collected was
used to verify a Computational Fluid
Dynamics (CFD) software model (Figure 2).
The close matching of the measurements
and the model-predicted parameters
allowed new design options to be first
tested in software, with a high degree of
confidence that the model output would
represent actual performance.
Compound Semi & Microtechnology
Oxide etch process
The solution is not to have just a single
“oxide etch process,” but rather a flexible
oxide etch capability, the performance of
which is well understood and controllable.
Table 1 outlines the range of capabilities
such a process must meet. The two
factors which create the biggest challenge
are high etch rate and high selectivity to a
photoresist mask. This is best understood
by a more detailed knowledge of the
oxide etch mechanism.
The energy necessary to break the
strong Si-O bond is provided by
bombardment from plasma-generated
ions that have been accelerated to the
substrate surface. This is conveniently
done in an Inductively Coupled Plasma
(ICP) configuration where inductive
coupling is responsible for generating
the plasma and a separate substrate RF
bias controls the ion energy (Figure 1).
In order to achieve a high oxide etch rate,
a high plasma density is required, which
in turn requires high power operation
of the inductive source. Importantly, this
requires the ability to then handle the
heat generated by such a high power
operation.
Silicon dioxide is etched using various
fluorocarbons such as CF4, CHF3, and
C4F8 that react with SiO2 to form volatile
by-products. However, these F-containing
gases also readily etch photo-resist,
especially in the presence of energetic
ion bombardment (necessary for a high
oxide etch rate). Therefore, to achieve
selective etching of the oxide relative to
photo-resist, polymer-promoting gases are
usually added in the gas mix. When the gas
ratio and ion energy are carefully adjusted,
such gases will cause the deposition of
polymer on photo-resist surfaces, but on
Unaxis Chip | 33
Figure 3: ICP
temperature stability
before modification
140
Temp [°C]
120
100
80
60
RF cycle:
15 min on @ 1 kW
3 min off
40
20
0
20
40
60
80
100
Time [min]
Figure 4: ICP
temperature stability
new design
160
RF On
140
Temp [°C]
120
Tset = 125°C
100
RF Off
80
60
Initial warm-up
RF cycle:
5 min on @ 1.5 kW
5 min off
Compound Semi & Microtechnology
40
20
0
10
20
Time [min]
30
40
In this way, a design to heat and
temperature control the ICP surfaces
was created without the need for timeconsuming “cut and try” methods:
essentially, the first prototype built met
the performance specifications. The
temperature control achieved with this
new design versus the original ICP
design is shown in Figures 3 and 4.
Likewise, a similar analysis and
modeling of the lower electrode assembly
helped to recognize a weakness in the
current design. With a new design, the
heat rejection improved by a factor of ~2,
a significant improvement which helps
maintain temperature control of the
substrate in high power applications.
Additional changes were made to the
RF coupling, permitting continuous high
power operation. Other changes, again
based on CFD modeling, were made to
the reaction chamber, which improved
the pumping speed while reducing the
internal volume, aimed at minimizing any
contamination-producing surfaces.
These various components that make
up the High Performance Oxide Etcher
(HiPOE) have been designed as modules,
which are incorporated into the new
VERSALINE™. From conception, this
platform has been designed with modularity
in mind, so such application-specific
improvements can be implemented with
the minimum impact on the overall
platform.
Process results
The operation of the oxide etcher
with the modified hardware was tested
over a range of process parameters,
encompassing a number of applications.
At one end of the application range is
a relatively shallow (< 2 µm deep) etch
34 | Chip Unaxis
Summary
A new process module has been designed
as part of the new VERSALINE™ platform,
to meet the many and varied oxide etch
Figure 5: Cross
section of Fresnel
lens etched into
quartz substrate
Figure 6: Highly
aspherical lens
etched ~40 µm deep
into quartz substrate
12,000
Thermal oxide
PECVD oxide
ICP = 2,000 Watts
10,000
Etch rate [Å /min]
8,000
6,000
4,000
2,000
0
100
200
300
400
Compound Semi & Microtechnology
into quartz, where etch rate is a secondary
consideration, but a precise selectivity
ratio to resist of 1:1 is the primary factor.
This ensures that resist features are
accurately transferred into the quartz
substrate and used to make refractive
optics. Such an etch, reproducing a
Fresnel Lens surface is shown in Figure 5.
The same etch can replicate spherical
lens surfaces when the photo-resist mask
is first heated and reflowed. An interesting
modification to this etch is obtained when
the selectivity to resist is increased to
values > 1:1. Then, the original spherical
mask profile is etched into the quartz to
create an aspherical surface, the optical
properties of which can be tailored to
produce high efficiency, small numerical
aperture lenses suitable for fiber optic
coupling. Figure 6 shows such a lens
etched to a depth of ~40 µm into quartz
at a rate of ~4000 Å /min. By operating the
source at 150°C for this higher selectivity
process, essentially no detrimental
polymer formation takes place.
The highest oxide etch rate process
is obtained using high ICP powers and
high bias powers. Figure 7 shows an
etch rate of 1µm /min is obtained at ICP
powers of ~2000 Watts when etching
PECVD oxide. Etch rates up to 1.4 µm /min
have been measured at the maximum
operating power level of the ICP.
Generally, such high power processes
can best exploit the stability of metal
masks and have been used to define
precise structures into thick oxide films
(10 µm) for waveguide applications.
RIE [ Watts]
needs. Much of the design involving
heat and gas flow was done using
computer-based modeling, which cut
the need for extensive prototyping.
This process has been tested over a
wide range of conditions and has shown
dramatic improvement over prior
capability.
Figure 7: Etch rate
of thermal and PECVD
oxides at different bias
powers
For more information please contact:
dave.johnson@unaxis.com
Unaxis Chip | 35
Compound Semi & Microtechnology
Pressure Control
in Deep Silicon Etch Processes
From telecommunication, to automotive, to biomedical applications,
MEMS technology plays an increasingly important role. In the manufacture
of such MEMS devices the time division multiplexed (TDM) plasma
processes are widely applied for deep silicon etching (DSE)[1]. The process
employs cyclically alternating etching and passivation steps[2].
Dr. Shouliang Lai, Senior Process Engineer
Russ Westerman, Director of Technology
Dr. Dave Johnson, Director of Research & Development
a
80
70
5s dep/4s etch
P (etch)
setpoint
60
P (dep)
setpoint
40
50
20
40
0
30
–20
Position [%]
Pressure [mT ]
60
Figure 1a:
Pressure (left axis)
and throttle valve
position (right axis)
in pressure mode.
Pressure overshoot
and undershoot
occur when process
steps alternate.
20
0
5
10
15
20
25
30
Time [s]
b
70
40
Pos (etch)
setpoint
50
20
Pos (dep)
setpoint
30
Desired
pre (etch)
10
Desired
pre (dep)
0
–10
10
–20
0
10
20
30
40
Time [s]
36 | Chip Unaxis
50
60
70
Position [%]
Pressure [mT ]
Compound Semi & Microtechnology
30
Figure 1b:
Throttle valve
position (right axis)
and the resultant
pressure (left axis)
in position mode.
Chamber pressure
exhibits slow
response and
undesired profile.
In a DSE process, different gases are
introduced into a reaction chamber at
different rates, and chamber pressures
are maintained at different levels in the
alternating steps. It is the alternating
process conditions that make pressure
control challenging.
Conventional pressure control
Throttle valves are conventionally
operated in either pressure mode or
position mode. In these two modes,
the internal proportional, integral and
derivative (PID) control mechanisms
regulate the movement of a throttle
valve according to prescribed pressure
or position values. In pressure mode, for
example, the chamber pressure is given.
A throttle valve adjusts its position to
achieve the desired pressure. Very often,
gas synchronization and particular mixes
of process conditions make it difficult to
effectively control pressure. As illustrated
in Figure 1a, chamber pressure exhibits
significant overshoot or undershoot.
When a passivation step (low pressure)
is alternated to an etch step (high
pressure) as shown in Figure 1a, the
throttle valve initially moves to a more
closed position. But etchant gas SF6 is
introduced into the chamber at a higher
rate, so pressure overshoot occurs. The
throttle valve then moves to a more open
position and subsequently settles in a final
Etch
Passivation
Stable
period
Transient
period
td2
Stable
period
Transient
period
te1
te2
td1 and te1: Transient periods, open-loop pressure control enabled
td2 and te2: Stable periods, close-loop pressure control enabled
Figure 3: Improved
pressure profile
obtained with the
new pressure control
technique
60
3s dep/4s etch
50
40
30
20
10
0
10
20
30
Time [s]
pressure irregularity and maintaining
pressure control. In doing so, a throttle
valve can be pre-positioned properly in
periods td1 and te1, when an open-loop
control is enabled. In periods td2 and te2,
a close-loop control is used to regulate
pressure. The internal PID functions of
the throttle valve are utilized to facilitate
such controls.
The new pressure control technique
for TDM etch processes has been tested
on a DSE™-III tool, which has a high
vacuum conductance and is equipped
with an ICP source. A High-density SF6
plasma is used for etching and a C4F8
plasma for passivation. Figure 3 shows
improved results with the new pressure
control technique. The etchant and
passivation gases have flow rates of
400 and 50 sccm, respectively, and the
given pressures are 50 and 20 mTorr.
As illustrated, the pressure overshoot and
undershoot during transition periods are
completely eliminated. Pressure has a
nearly “squared” profile, and pressure
transient times are reduced.
This novel pressure control technique
also improves long-term process stability.
It is usual that the temperature of chamber
walls varies during and between process
runs. Such temperature variation affects
plasma pressure. Because pressure is one
of the primary determinants of etch rate,
DSE performance would fluctuate over
time if long-term pressure stability is not
maintained. This issue is especially a
concern in the position control mode.
In essence, our new technique exerts
Compound Semi & Microtechnology
New pressure control
Recently, a novel technique has been
developed to improve pressure control
capability in DSE. The method is
illustrated in Figure 2. In pressure mode,
pressure overshoot and undershoot occur
in transient periods td1 and te1, while in
stable periods td2 and te2 pressure is well
regulated. In position mode, overshoot
and undershoot tend to be suppressed,
while pressure in the stable periods is not
well regulated. Thus, a combination of
pressure mode and position mode may
have the benefits in both suppressing
td1
Pressure [mT]
position. When an etch step is alternated
to a passivation step, the throttle valve has
a more opened position initially, causing a
pressure undershoot. Generally speaking,
such pressure deviations get worse when
process steps get shorter. Pressure overand undershoot harm plasma stability and
etch performance, and spurious
movement of throttle causes valve
wearing and particle contamination.
In position mode, the position of the
throttle valve is given. A learning
procedure is required to establish the
correspondence between pressure
and position. As shown in Figure 1b,
pressure response is slow, and actual
pressures are not stabilized even when
the throttle is positioned at constant
values. Moreover, since pressure control
now is essentially an open-loop control,
long-term pressure drift occurs, causing
problems in maintaining DSE process
repeatability. There have been some
efforts in devising methods to better
control chamber pressure in alternating
processes [3–6]. While these approaches
have their own advantages, various
drawbacks exist.
Figure 2: New
pressure control
technique: in the
transient periods,
open-loop pressure
control is enabled; in
the stable periods,
close-loop pressure
control is enabled.
Unaxis Chip | 37
Figure 4: An example
of long-term
pressure stability
using the new
pressure control
technique.
Compound Semi & Microtechnology
Application in MEMS manufacturing
MEMS manufacturing demands TDM
etch processes to satisfy a wide range
of etch performance requirements,
and often trade-offs must be made.
For example, high etch rate and smooth
sidewall smoothness are normally
incompatible in conventional TDM etch
processes. But in some MEMS
applications, optically smooth surfaces
are needed along with high etch rate
for throughput considerations. A fast gas
switching technique has been developed
by Unaxis Wafer Processing to achieve
high etch rates while minimizing scallops
on the Si sidewall [7]. The process steps
are short, close to 1.0 second only, and
conventional pressure control methods do
not apply.
Figure 5: Optically
smooth deep silicon
structure etched in a
DSE™ process with
short steps. Scallop
depth is below 10
nm, and overall etch
rate is 6.4 µm/min.
38 | Chip Unaxis
ICP = 3000 W
SF6 = 400 sccm
P(etch) = 90 mT
95
Pressure [mT]
close-loop control on pressure. It enables
the long-term pressure drifts to be
eliminated, as demonstrated in Figure 4.
The etch pressure remains at 90 mTorr
during a continuous process operated for
over 70 minutes at very high ICP power.
100
90
85
80
75
0
200
400
1,800
2,000
2,200
4,000
4,200
4,400
Time [s]
The new pressure control technique is
especially advantageous in controlling
pressure in processes with very short
steps. Pressure response time is reduced,
and pressure profile is improved. Thus,
the new control is an enabler to the fast gas
switching technique. Figure 5 shows the
improved plasma etch capability. Trenches
with a4 µm wide opening are etched into
150 mm silicon wafer. The trenches have
an aspect ratio of 10:1. As demonstrated,
the overall etch rate is 6.4 µm/min, while
the scallop depth is below 10 nm. The
planar view SEM image on the right confirms
the smoothness of etched silicon trench
sidewalls.
In conclusion, the new pressure control
technique opens up a new dimension in
DSE processing. The Unaxis proprietory
DSE™ III process technology works
therefore with a unique algorithm
implemented in combination with the
valve’s internal PID control function.
Pressure over- and undershoot and
long-term pressure drift are eliminated
and response times are significantly
improved.
DSE™ III provides higher process
reliability and etch rates for DSE MEMS
manufacturing.
For more information please contact:
shouliang.lai@unaxis.com
References
1 K. Suzuki et al., U.S. Patent No. 4,579,623, April
1, 1986; F. Laermer and A. Schilp, U.S. Patent
No. 5,498,312, March 12, 1996.
2 S. Lai et al., Chip Magzine, Vol. 8, March 2003,
pp. 35 – 36.
3 M. Puech, U.S. Patent No. 6,431,113,
August 13, 2002.
4 F. F. Kaveh et al., U.S. Patent No. 5,758,680,
June 2, 1998.
5 B.K. McMillin et al., U.S. Patent No. 6,142,163,
November 7, 2000.
6 C. Beyer et al., U.S. Patent No. 5,944,049,
August 31, 1999.
7 S.L. Lai et al., Proc. on Micromachining and
Microfabrication Process Technology VIII,
SPIE-4979, pp. 43 – 50, San Jose, California,
2003.
Compound Semi & Microtechnology
DSE™
Notch Reduction for SOI
The deep silicon etching process found
in widespread industrial use [1, 2] is often
referred to as being Time Division
Multiplexed. The reason for this name
is the process cycles alternating between
etching and passivation cycles. Using
well-known established SF6 chemistry
in an ICP dry-etching chamber, silicon
is etched at high rates followed by a
fluorocarbon deposition step to keep the
etched profile vertical. In addition to
satisfying high etching rate requirements,
the DSE™ process meets the conditions
of smooth sidewalls, selectivity-to-masking
materials, and lateral mask undercut. [3]
SOI wafers have the additional constraint
that “notching” [4] must be eliminated.
Unaxis Wafer Processing removes SOI
limitations with its DSE™ technology.
⊕ ⊕
⊕ ⊕
Figures 1a and 1b:
Charging mechanism
in conventional DSE™
TDM etch
Charging of buried oxide and
notching
SOI wafers have a layer of single crystal
silicon atop a silicon oxide layer. In its
simplest forms, the SOI wafer is an oxide
film on a silicon wafer where the oxide
is deposited either through thermal
oxidation, PVD, CVD, PECVD, or even
Mask
Si
Mask
y
y
y
y
y
y
y
y
y
y
y
y
Si
⊕ ⊕ ⊕ ⊕
⊕ ⊕ ⊕ ⊕
Insulator
Insulator
a
b
simpler, a silicon wafer bonded to glass.
In these cases, a membrane can be
formed by etching of the silicon wafer
and stopping on the oxide or insulating
layer. In more complex designs, the oxide
layer can be “buried” beneath another
layer of silicon. When used in this manner,
the oxide can also behave as an etch
stop or as a local release “sacrificial layer.”
Typically, with an etch stop layer, the
effects of Aspect Ratio Dependent
Etching (ARDE), where different feature
sizes etch at different rates, should not
be apparent. In ARDE, mass transfer of
reagents and reaction products result in
wider features etching faster and reaching
the buried oxide layer faster than the
narrower or higher aspect ratio features.
During the time between when the wider
features have reached the oxide and the
narrower features are still being etched,
positive charge builds up on the wider
features. The positive charge built up
before the buried oxide layer is exposed
recombines effectively through the bulk
silicon as shown in Figure 1a. Once the
oxide layer is exposed to the plasma,
a positive charge builds up on the
insulator. Simplistically, this accumulation
of positive charge leads to preferential
etching of silicon at the Si-oxide interface,
as is illustrated in Figure 1b.
Unaxis Chip | 39
Compound Semi & Microtechnology
Sunil Srinivasan, Associate Scientist
Dr. Dave Johnson, Director of Research
& Development
Russ Westerman, Director of Technology
Micro-Electro-Mechanical Systems (MEMS) applications are
increasingly turning towards silicon-on-insulator (SOI) wafers.
The creation of low-stress, flexible structures made possible
with SOI wafers is increasing surface micro-machining
opportunities. One of the critical processes in many MEMS
fabrication flows is the Deep Silicon Etch (DSE™) of high
aspect ratio silicon structures.
Figure 2: Notching
at Si-buried oxide
interface in
conventional
DSE™ TDM etch
The profile of the feature formed from
this preferential lateral etching is called
“notching.” The notch formed at the
Si-oxide interface is a function of aspect
ratio (feature depth divided by feature
width) and the time of the overetch [5].
Usually, “overetch” on a cleared feature
is described as the percentage of overall
process time it is exposed to the plasma,
while the smaller features are being
etched. Due to ARDE and the range of
features sizes on a wafer, overetch
percentages may be as high as 60% on
the wider features. The aspect ratio
determines the extent to which notching
occurs and worsens as the aspect ratio
increases.
Compound Semi & Microtechnology
Unaxis DSE™ SOI solutions
The problem of charge formation and
notching with conventional DSE
processes prompted Unaxis Wafer
Processing to develop a proprietary
method to reduce and in certain cases,
eliminate notching. This method requires
the etching process be divided into
two parts, as illustrated in Figure 3a.
Figures 3a and 3b:
Process schematic
showing bulk
DSE™ III TDM and
Unaxis proprietary
DSE™ III TDM
finish etch
Si
Notch
SiO 2
The bulk of silicon in the SOI wafer is
etched with a conventional DSE process
(t1). This process produces smooth
sidewalls at a fast etching rate, with high
selectivity-to-mask, and minimum
undercut. The second part is a “finish”
etching process that is utilized to etch
the smallest features and is equal to the
overetching period t3. A critical
Mask
OES end point detection at t2
DSE™ III TDM
Bulk etch, t1
DSE™ III TDM
Finish etch, t3
component of this hybrid process is the
transition between the bulk and finish
etching steps. Since notching is sensitive
to the overetch percentage, any significant
exposure of the oxide to the plasma
during t1 will cause notching. In order to
make the transition at the appropriate
time, Optical Emission Spectroscopy
(OES) is used to detect initial exposure
Si
t1
t3
Process time, t
a
40 | Chip Unaxis
Buried oxide layer
b
Si
a
Figures 4a and 4b:
Notch reduction with
Unaxis proprietary
DSE™ III TDM finish
etch
b
Conclusions
The emerging importance of SOI
substrates for MEMS processing is the
driving force behind Unaxis’ DSE SOI
hybrid process. The opportunity for
MEMS designers to incorporate SOI
structures in their devices requires
eliminating notching without sacrificing
etching rate, sidewall smoothness, profile,
or selectivity. This recent progress
maintains the advantages of using a
high-density plasma for high-rate deep
silicon etching. A two-step hybrid process
that relies on sensitive endpoint detection
and charge dissipation effectively
eliminates notching.
References
1 F. Laermer et al., U.S. Patent No. 5,498,312
2 Suzuki et al., U.S. Patent No 4,579,623
3 S. L. Lai et al., Proc. on Micromachining
and Microfabrication Process Technology VIII,
SPIE-4979, pp. 43 – 50, San Jose, California,
2003
4 Gyeong S. Hwang et al. , J. Vac. Sci. Technol. B
Jan/Feb 1997
5 Gyeong S. Hwang et al., J. Apply. Phys. 82(2) ,
July 1997
Compound Semi & Microtechnology
of the oxide in the widest features. This
is t2 in the Figure 3a. With Unaxis
proprietary OES endpoint algorithm
uniquely programmed for TDM, exposed
oxide in the lowest aspect ratio features
is detected at as little as 2% open area on
a 150 mm wafer.
As illustrated in Figure 3b, the etching
depth in the various features depends on
the feature widths. The feature on the far
right is almost entirely etched using the
bulk etch. The OES end point algorithms
detect when the features equivalent to the
far right feature are cleared throughout the
wafer. The unetched silicon in the higher
aspect ratio features is then etched using
the DSE finish etching process. Figure 3b
highlights the transition between the
DSE bulk etching step and the DSE finish
etching step with respect to the different
features. Using this hybrid process,
notching at the Si-oxide interface is greatly
reduced. Innovative Unaxis finish etching
process technology compensates for
the conditions leading to notch formation,
namely, positive charge accumulation
on the buried oxide interfaces.
The SEM in Figure 4a is a cross-section
of a standard Unaxis SOI test structure
etched with this hybrid DSE SOI process.
The aspect ratios range from 22:1 to 5:1
in the cross-section for the 30 micron
deep features. As seen, the notching is
completely eliminated from 10:1 aspect
ratio feature and lower. By using this
hybrid process for SOI wafers, significant
overetching of the smaller aspect ratio
features is possible. Even with significant
overetching, notching is not seen on the
5:1 aspect ratio features and lower. This
is illustrated in Figure 4b with a highmagnification image of the silicon-oxide
interface on a 5:1 aspect ratio feature.
Unaxis Chip | 41
Unaxis Insights
Unaxis Wafer Processing
Around the Globe
12th – 14th
Semicon West
Wafer Processing
San Francisco
www.semi.org
16th – 18th
Semicon West
Final Manufacturing
San Jose
www.semi.org
August
29th – 2nd Sept.
COMS
Wafer Processing
Edmonton, Alberta, Canada
www.mancef-coms2004.org
September
13th – 15th
Semicon Taiwan
Wafer Processing
Taipei
www.semi.org
14th – 15th
Photomask Technology
(BACUS)
Monterey, California, USA
www.spie.org
27th – 2nd Oct.
SEMI Expo CIS
Semicon Moscow
Wafer Processing
Moscow
www.semi.org
1st– 3rd
Semicon Japan
Wafer Processing
Tokyo
www.semi.org
July
Truebbach, Switzerland
PVD, Soft Etch, RTP, UHV-CVD, LEPC, LEPECVD
www.waferprocessing.unaxis.com
St.Petersburg, FL, USA
Etch (RIE, ICP), PECVD
June 2004
events
events
December
For updates please check www.waferprocessing.unaxis.com
Unaxis Wafer Processing at Semicon China 2004
Unaxis Insights
Unaxis Wafer Processing
Around the Globe
12th – 14th
Semicon West
Wafer Processing
San Francisco
www.semi.org
16th – 18th
Semicon West
Final Manufacturing
San Jose
www.semi.org
August
29th – 2nd Sept.
COMS
Wafer Processing
Edmonton, Alberta, Canada
www.mancef-coms2004.org
September
13th – 15th
Semicon Taiwan
Wafer Processing
Taipei
www.semi.org
14th – 15th
Photomask Technology
(BACUS)
Monterey, California, USA
www.spie.org
27th – 2nd Oct.
SEMI Expo CIS
Semicon Moscow
Wafer Processing
Moscow
www.semi.org
1st– 3rd
Semicon Japan
Wafer Processing
Tokyo
www.semi.org
July
Truebbach, Switzerland
PVD, Soft Etch, RTP, UHV-CVD, LEPC, LEPECVD
www.waferprocessing.unaxis.com
St.Petersburg, FL, USA
Etch (RIE, ICP), PECVD
June 2004
events
events
December
For updates please check www.waferprocessing.unaxis.com
Unaxis Wafer Processing at Semicon China 2004
Worldwide
Greater China
Korea
Kenneth T. Barry
President,
Unaxis Wafer Processing
ken.barry@unaxis.com
Benjamin Loh
President Unaxis Greater China
benjamin.loh@unaxis.com
Brian Kim
President Unaxis Korea
brian.kim@unaxis.com
Dr. Gordon Shyu
Vice President Sales
and Marketing
Greater China
gordon.shyu@unaxis.com
Daniel Kim
Key Accounts Manager
daniel.kim@unaxis.com
North
America
Europe
Paul Henry
Vice President of International
Sales and Marketing
paul.henry@unaxis.com
Jim Pollock
Director Sales and Marketing
North America
jim.pollock@unaxis.com
Mark Hashemi
Director Sales and Marketing
Europe
mark.hashemi@unaxis.com
Andreas Dill
Vice President and
General Manager
Europe
andreas.dill@unaxis.com
David Hartel
Customer Support Manager
david.hartel@unaxis.com
Sylvester Sebold
Customer Support Manager
Europe
sylvester.sebold@unaxis.com
Wolfgang Radloff
Marketing Manager
wolfgang.radloff@unaxis.com
Kibom Kim
Customer Support Manager
kibom.kom@unaxis.com
Taiwan
China
Peter Sermon
Regional Sales Manager
North Europe
peter.sermon@unaxis.com
Kevin Jan
Sales Director
kevin.jan@unaxis.com
William Zhu
Sales Director
william.zhu@unaxis.com
Jenny Yang
Assistant Wafer Processing
jenny.yang@unaxis.com
Eastern North
America
Jürg Steinmann
Global Communications Manager
juerg.steinmann@unaxis.com
Dan Pace
Sales Engineer
dan.pace@unaxis.com
Ralf Eichert
Regional Sales Manager
Central Europe
ralf.eichert@unaxis.com
Daven Hsu
Customer Support Manager
daven.hsu@unaxis.com
Wingo Lu
Sales Manager
wingo.lu@unaxis.com
Robert van der Putten
Global Customer Support
Manager
robert.vanderputten@unaxis.com
Peter Potter
Sales Engineer
peter.potter@unaxis.com
Dr. Gotthard Kudlek
Sales Accounts Manager
Central Europe
gotthard.kudlek@unaxis.com
Jimmy Chen
Senior Account Manager
jimmy.chen@unaxis.com
Jimmy Xu
Customer Support Supervisor
jimmy.xu@unaxis.com
Hirohide Fujii
President Unaxis Japan
hirohide.fujii@unaxis.com
Fiorenzo Slaviero
Regional Sales Manager
South Europe
fiorenzo.slaviero@unaxis.com
Allan Lin
Senior Account Manager
allan.lin@unaxis.com
Sunday Huang
Sales Assistant
sunday.huang@unaxis.com
Yukihide Kajimoto
Customer Support Manager
Osaka
yukihide.kajimoto@unaxis.com
Michael Helmes
Sales Manager
michael.helmes@unaxis.com
Claude Dupuy
Sales Accounts Manager
South Europe
claude.dupuy@unaxis.com
Joanne Teng
Sales Assistant
joanne.teng@unaxis.com
Todd Smith
Sales Engineer
todd.smith@unaxis.com
Elke Haselmayr
Sales Assistant Europe
elke.haselmayr@unaxis.com
Japan
Western North
America
Masatoshi Nakamura
Customer Support Manager
Tokyo
masatoshi.nakamura@unaxis.com
Singapore
Jim Greenwell
Sales Engineer
jim.greenwell@unaxis.com
Chih Heng Han
Vice President
South East Asia
Asiachihheng.han@unaxis.com
Toshihide Haruki
Sales Manager
toshihide.haruki@unaxis.com
Swee Teck Ong
Customer Support Manager
sweeteck.ong@unaxis.com
Wataru Momose
Sales Engineer
wataru.momose@unaxis.com
Boon Kwong Tan
Sales Engineer
boonkwong.tan@unaxis.com
Taeko Matsui
Sales Assistant
taeko.matsui@unaxis.com
Elaine Ng
Sales Assistant
elaine.ng@unaxis.com
Our experienced team of R&D, sales and systems support specialists are there
for you, wherever and whenever you may need them – anywhere in the world.
For updates please check
www.waferprocessing.unaxis.com
Digital Imagery © copyright 2001 PhotoDisc, Inc.
Worldwide
Greater China
Korea
Kenneth T. Barry
President,
Unaxis Wafer Processing
ken.barry@unaxis.com
Benjamin Loh
President Unaxis Greater China
benjamin.loh@unaxis.com
Brian Kim
President Unaxis Korea
brian.kim@unaxis.com
Dr. Gordon Shyu
Vice President Sales
and Marketing
Greater China
gordon.shyu@unaxis.com
Daniel Kim
Key Accounts Manager
daniel.kim@unaxis.com
North
America
Europe
Paul Henry
Vice President of International
Sales and Marketing
paul.henry@unaxis.com
Jim Pollock
Director Sales and Marketing
North America
jim.pollock@unaxis.com
Mark Hashemi
Director Sales and Marketing
Europe
mark.hashemi@unaxis.com
Andreas Dill
Vice President and
General Manager
Europe
andreas.dill@unaxis.com
David Hartel
Customer Support Manager
david.hartel@unaxis.com
Sylvester Sebold
Customer Support Manager
Europe
sylvester.sebold@unaxis.com
Wolfgang Radloff
Marketing Manager
wolfgang.radloff@unaxis.com
Kibom Kim
Customer Support Manager
kibom.kom@unaxis.com
Taiwan
China
Peter Sermon
Regional Sales Manager
North Europe
peter.sermon@unaxis.com
Kevin Jan
Sales Director
kevin.jan@unaxis.com
William Zhu
Sales Director
william.zhu@unaxis.com
Jenny Yang
Assistant Wafer Processing
jenny.yang@unaxis.com
Eastern North
America
Jürg Steinmann
Global Communications Manager
juerg.steinmann@unaxis.com
Dan Pace
Sales Engineer
dan.pace@unaxis.com
Ralf Eichert
Regional Sales Manager
Central Europe
ralf.eichert@unaxis.com
Daven Hsu
Customer Support Manager
daven.hsu@unaxis.com
Wingo Lu
Sales Manager
wingo.lu@unaxis.com
Robert van der Putten
Global Customer Support
Manager
robert.vanderputten@unaxis.com
Peter Potter
Sales Engineer
peter.potter@unaxis.com
Dr. Gotthard Kudlek
Sales Accounts Manager
Central Europe
gotthard.kudlek@unaxis.com
Jimmy Chen
Senior Account Manager
jimmy.chen@unaxis.com
Jimmy Xu
Customer Support Supervisor
jimmy.xu@unaxis.com
Hirohide Fujii
President Unaxis Japan
hirohide.fujii@unaxis.com
Fiorenzo Slaviero
Regional Sales Manager
South Europe
fiorenzo.slaviero@unaxis.com
Allan Lin
Senior Account Manager
allan.lin@unaxis.com
Sunday Huang
Sales Assistant
sunday.huang@unaxis.com
Yukihide Kajimoto
Customer Support Manager
Osaka
yukihide.kajimoto@unaxis.com
Michael Helmes
Sales Manager
michael.helmes@unaxis.com
Claude Dupuy
Sales Accounts Manager
South Europe
claude.dupuy@unaxis.com
Joanne Teng
Sales Assistant
joanne.teng@unaxis.com
Todd Smith
Sales Engineer
todd.smith@unaxis.com
Elke Haselmayr
Sales Assistant Europe
elke.haselmayr@unaxis.com
Japan
Western North
America
Masatoshi Nakamura
Customer Support Manager
Tokyo
masatoshi.nakamura@unaxis.com
Singapore
Jim Greenwell
Sales Engineer
jim.greenwell@unaxis.com
Chih Heng Han
Vice President
South East Asia
Asiachihheng.han@unaxis.com
Toshihide Haruki
Sales Manager
toshihide.haruki@unaxis.com
Swee Teck Ong
Customer Support Manager
sweeteck.ong@unaxis.com
Wataru Momose
Sales Engineer
wataru.momose@unaxis.com
Boon Kwong Tan
Sales Engineer
boonkwong.tan@unaxis.com
Taeko Matsui
Sales Assistant
taeko.matsui@unaxis.com
Elaine Ng
Sales Assistant
elaine.ng@unaxis.com
Our experienced team of R&D, sales and systems support specialists are there
for you, wherever and whenever you may need them – anywhere in the world.
For updates please check
www.waferprocessing.unaxis.com
Digital Imagery © copyright 2001 PhotoDisc, Inc.