EMC-aware Printed Circuit Board Design of
DC-DC Converters
Raul Blecic
Department of electronics, microelectronics, computer and intelligent systems
Faculty of Electrical Engineering and Computing University of Zagreb, Unska 3, 10000 Zagreb, Croatia
Tel: +385 (0)1 6129547, fax: +385 (0)1 6129653, e-mail: raul.blecic@fer.hr
Abstract—In this paper a printed circuit board (PCB) design of DC-DC converters with respect to the electromagnetic
compatibility (EMC) is analyzed. The simulation methods for
parallel plate waveguides are evaluated and the most appropriate
one for the design of DC-DC converters is recognized. The
simulation results using the proposed method are compared to the
results from the general purpose full-wave electromagnetic (EM)
simulators. The influence of the equivalent series resistance (ESR)
and equivalent series inductance (ESL) of decoupling capacitors
on electromagnetic interference (EMI) is investigated and the
concept of reducing the EMI by a careful choice of decoupling
capacitors is presented. A new PCB layout scheme is proposed
to reduce the EMI of DC-DC converters.
Index Terms—PCB layout optimization, circuit-EM cosimulation, EM simulation, cavity mode modeling, integralequation methods, power integrity, power distribution network.
I. I NTRODUCTION
Switching DC-DC converters are more efficient and smaller
in volume and weight when compared to linear converters
which makes them an appealing choice for various applications. However, due to the switching mode of operation
and high dv/dt and di/dt they are sources of EMI [1]. The
ongoing trend of integration of DC-DC converters pushes
the switching frequencies to higher values because of the
maximum nominal value limitation of integrated reactive
components. Higher switching frequencies increase switching
losses and degrade the efficiency of DC-DC converters. To
decrease switching losses and increase the efficiency, the
dv/dt and di/dt are increased [2]. This, in turn, increases
EMI even more and makes it the most challenging part of
a DC-DC converter design. Products incorporating DC-DC
converters must comply with conducted and radiated emission
limits according to standards CISPR22, FCC part 15 and EN
55022 as shown in Fig. 1.
The EMI of the switching buck DC-DC converter (similar
to those in the INVENT project [3]) is studied in [4]. It was
found that the resonance formed by the capacitance of the
low-side FET in off state Coss and the total inductance of the
decoupling loop is the main source of ringing of the phase
voltage and for increased EMI. The same authors provided
EMC guidelines for buck converter design in [5]. The ringing
of the phase voltage and increased EMI were co-simulated in
[6]. The same authors suggested six buck converter PCB layout
modifications for reducing the EMI in [7], and proposed to
(a) Conducted emission levels.
(b) Radiated emission levels.
Fig. 1. Standards for conducted and radiated emissions levels for products
incorporating DC-DC converters [3].
damp the parasitic LC resonance by adding losses in switching
loop in a form of RL snubber connected to the drain of the
high-side FET. The impact of the PCB layout on the EMI
of DC-DC converter was also investigated in [8] and in [9]
where, similar to [7], the parasitic LC resonance is damped
Fig. 2.
required charge to the switching circuits, lowering the power
supply noise. However, decoupling capacitors in combination
with the parasitic inductances of the capacitor package, trace
inductances and IC package inductances form a resonant circuit [15]; below the resonant frequency the capacitor actually
shows a capacitive behaviour and reduces the PDN impedance,
however, above resonant frequency it shows inductive behavior
and is practically useless as a decoupling capacitor. To extend
the usable frequency range of decoupling capacitors, several
options are available:
Basic power delivery system [10].
1) Multiple capacitors of different values. Multiple capacitors of different values will have an antiresonant
peak between each resonant frequency which potentially
limits their effectiveness [15], since noise and radiated emission considerably increase at antiresonances
[16]. However, if the capacitor values are progressively
decreasing, the anti-resonant spike can be shifted to
frequencies out of the range of interest [10].
2) Multiple capacitors all of the same value. For each
additional capacitor added, an equivalent capacitance is
increased, while an equivalent inductance is decreased.
Thus, the PDN impedance is decreased.
3) Embedded PCB Capacitance. Taking the concept of
using a large number of equal value capacitors to its
limit, the ideal decoupling configuration is an infinite
number of infinitesimal capacitors, i.e. distributed capacitor [15]. The parallel-plate waveguide capacitance,
if large enough, can be used as a distributed capacitor.
However, due to the reflections from the ends of finite
parallel plates, the resonances of the embedded PCB
capacitance occur which limit its usability [16]. If the
boundary of the power-ground plane pair is terminated
into parallel-plate characteristic impedance, this resonances are avoided and a resonant-free PDN can be
achieved [17], [18].
by choosing capacitors with high ESR.
All of the mentioned papers based their work on the fullwave simulations and/or measurements. Full-wave simulations
are time consuming which makes them unpractical for the design optimization. Measurements are not only unpractical but
are also an expensive way to optimize the design. Therefore, a
fast circuit simulation method that enables the optimization of
a DC-DC converter PCB design is needed. The fast simulation
method for the design, optimization and analysis of DC-DC
converters is presented in this paper.
This paper is structured as follows: Section II presents basic
issues with a power distribution network design and additional requirements imposed by DC-DC converters; Section
III presents the analytic solutions and semi-analytic simulation
methods for a parallel-plate waveguide, their advantages and
disadvantages, and suggest the best simulation method for a
DC-DC converter design; Section IV shows the application
examples of the suggested method; Section V shows simulation results using the 3D full-wave simulators; and in Section
VI the conclusion is given.
II. P OWER D ISTRIBUTION N ETWORK
A power distribution network (PDN) consists of a power
supply, a power load, and interconnect lines connecting the
supply to the load (Fig. 2). The power supply is assumed to
behave as an ideal voltage source providing nominal power
and ground voltage levels, Vdd and Vgnd . The power load is
modeled as a variable current source I(t). The interconnect
lines connecting the supply and the load are not ideal; the
power and ground lines have a finite parasitic resistance Rp
and Rg , respectively, and inductance Lp and Lg , respectively.
Resistive voltage drops VR = IR and inductive voltage
drops VL = LdI/dt develop across the parasitic interconnect
impedances, as the load draws current I(t) from the power
distribution network. The voltage levels across the load terminals, therefore, change from the nominal level provided by the
supply, dropping to Vdd −IRp −Lp dI/dt at the power terminal
and rising to Vgnd + IRg + Lg dI/dt at the ground terminal,
as shown in Fig. 2 [10]. This change in the supply voltages
is referred to as a power supply noise (DC (IR) noise caused
by high average currents and an AC (delta-I) noise caused by
fast current transients [11], [12], [13], [14]).
Decoupling capacitors are often used to reduce the
impedance of a power distribution network and provide the
Beside EMC, another major issue in the design of DCDC converters are the losses that generate heat which can
damage the system if not properly taken care of [19]. This
places additional strict requirements on a design of the PDN
for DC-DC converters [3] (which, in turn, affects its EMC):
1) The power and ground pins should be connected to
power and ground planes that serve as heatsinks. Electrically viewed, power and ground planes form a parallelplate waveguide whose distributed nature needs to be
taken into account.
2) Exposed pads can be used to maximize the thermal
transfer. Distributed nature of exposed pads should be
taken into account.
3) The copper should be as thick as possible to reduce the
parasitic resistance.
4) Multiple layers for power and ground planes can be
used to decrease parasitic resistance and inductance.
Multiple vias should be used for inter-layer connections
to minimize parasitic inductance. However, too many
vias degrade the quality of the parallel-plate waveguide
2
since perforations in parallel-plate waveguides increase
their inductance.
Looking at the list of issues from a PDN design and the list
of additional requirements from a DC-DC converter design, it
is obvious that the design of the PDN is not a straightforward
task and that an optimization algorithm is more than welcome.
The algorithm would be useful for any system design, and is
not limited to the design of DC-DC converters.
III. PARALLEL -P LATE WAVEGUIDE M ODELING
A. Analytic solutions
1) Cavity-mode model: The impedance between two ports
in a parallel-plate waveguide is most often calculated as [20]:
Z Z
1
G(r, r0 )dSi dSj ,
(1)
Zij = −
Si Sj Si Sj
Fig. 3.
Rectangular parallel-plate waveguide.
0
where G(r, r ) is the electric field Green function for electric
currents in a 2D transmission line structure; the observation
point r is element of dSi ; and the source point r0 is element
of dSj . Since Green functions are available for rectangular,
special triangular and cylindrical cavities only, analytic solutions for impedance matrix in 2D transmission line structures
are also available for these geometries only [20].
The cavity mode model is based on the impedance definition
(1) so it does not take the perforations from vias into account,
and it is available for rectangular and triangular cavities only.
Therefore, it is not the appropriate method for a DC-DC
converter design. However, it is a very popular modeling
method which can be used to verify the validity of semianalytic modeling methods, as well as for the fast analysis
of PCB parameters. The influence of the dimensions of the
structure and the parameters of the substrate material on antiresonant peaks in impedance profile are investigated in [13];
the influence of decoupling capacitors is investigated in [14],
to name a few examples.
Cavity-mode modeling method is an analytic solution of
the impedance matrix equation of a rectangular parallel-plate
waveguide (see Fig. 3) based on the Green function of the
2D Helmholtz equation with the boundary condition of the
second kind, i.e. the perfect magnetic walls [11]. The boundary
condition corresponds to the requirement that the thickness of
the PCB is much smaller than the wavelength which is almost
always satisfied in real PCBs. The elements of the impedance
matrix are calculated as [12]:
Zij =
ohmic losses [16]; xi and yi , and xj and yj are the coordinates
of the center of the ith and jth ports, respectively; and w is
the half-width of rectangular ports and is much smaller than
the wavelength of interest.
Equation (2) converges extremely slow for the selfimpedance, because of the singularity of the Green function.
Using the summation formula of a Fourier series, the double
series is reduced to the single series [11]:
Zij =
×sinc2 (kyn w)
cos(αn x− ) + cos(αn x+ )
,
αn sin(αn )
(3)
q
2 , x = 1 − (x ± x )/a, and C is
where αn = a k 2 − kyn
±
i
j
n
a constant equal to Cn = 1 if n = 0 and Cn = 2 if n 6= 0.
The ’fast algorithm’ for the input impedance Zii of a
rectangular parallel-plate waveguide is also provided in [11],
however, when combined with transfer impedances calculated
using either double or single summation, it forms an illconditioned impedance matrix and can not be used whenever
multiple ports are present.
The accuracy of the method greatly depends on the number
of modes taken into account, when higher modes are taken into
account the solution is more accurate, however, the simulation
time is increased [11]. Since resonant frequency for each mode
is determined only by the mode itself and is not affected by
the number of modes taken into account, for fast evaluation
smaller number of modes such as 30-80 (depending on the
size of the structure) is sufficient for reasonable accuracy.
2) Cylindrical Wave Definition: Another analytic solution
is available for the circular parallel plate as shown in Fig. 4.
Solution of the 2D Helmholtz equation for a 2D transmission line structure in cylindrical coordinates is [21]:
∞ X
∞
X
jωµh Kmn sinc2 (kxm w)sinc2 (kyn w)
2 + k2 − k
ab
kxm
yn
m=0 n=0
× cos(kxm xi ) cos(kyn yi ) cos(kxm xj ) cos(kyn yj ),
∞
X
ωµha
Cn cos(kyn yi ) cos(kyn yj )
j2b
n=0
(2)
where ω is the radian frequency; µ is the permeability of
vacuum; h is the thickness of the substrate, and is much
smaller than the wavelength of interest; a is the length and
b is the width of the rectangular cavity; Kmn is a constant
equal to Kmn = 1 if m = n = 0, Kmn = 2 if m = 0 ∨ n = 0
and Kmn = 4 if m 6= 0 ∧ n 6= 0; kxm = mπ/a, kyn = nπ/b;
k is the complex wavenumber including the dielectric and the
(1)
(2)
Ez = AH0 (kR) + BH0 (kR)
j
(1)
(2)
Hφ = [AH1 (kR) + BH1 (kR)],
η
3
(4)
Fig. 5.
Illustration of a real PCB design: irregularly shaped multiply
connected boundaries with cut-outs.
Fig. 4.
Another solution is the segmentation method - an irregular
plane pair is divided into smaller and regular shapes, each
regular shape is modeled using analytic solution, and then all
segments are assembled together [22]. Obviously, the more
irregular the structure to be modeled is, the more complex the
segmentation is, which limits its usability.
1) Contour integral method (CIM): CIM uses the integral
equation solution to calculate the impedance matrix. The
problem geometry is shown in Fig. 5. The voltage inside and
on the boundary of a source-free region can be expressed by
the integral of voltages and current densities on the boundary
(multiply connected contour C; see Fig. 5) [23], [24]:
I
R
k
(2)
[ n̂˙ 0 H1 (kR)V (r0 ) +
V (r) = K
j C R
Cylindrical parallel-plate waveguide.
where A and B are arbitrary constants depending on the source
and boundary conditions; k is the complex wavenumber; R is
the radial distance from the center; η is the wave impedance,
(1)
(1)
η = ωµ/k; H0 and H1 are the zeroth- and the first-order
(2)
(2)
Hankel functions of the first kind; and H0 and H1 are the
zeroth- and the first-order Hankel functions of the second kind.
With the source condition I = I0 at ri , and the perfect
magnetic conductor (PMC) boundary condition (Hφ = 0) at
the periphery of the circular parallel plate ρ = R0 , constants
A and B are uniquely defined and the input impedance at the
center of the circular parallel plate is calculated as [21]:
(1)
(2)
+jηhH0 (kR)Jn (r0 )]dl0 ,
where K is equal to 1/2 for points on the contour C, and 1/4
for points inside the contour C; R is the vector from the source
point r to the observation point r0 , R = r − r0 ; R is the length
of R; n̂0 is the normal vector to the contour C at the source
(2)
(2)
point; H0 and H1 are the zeroth- and the first-order Hankel
functions of the second kind; k is the complex wavenumber;
η is the wave impedance, η = ωµ/k; and h is the thickness
of the substrate, and is much smaller than the wavelength of
interest. The integration is defined over the source point.
To solve the equation (7), the boundary of the power-ground
plane pair is divided into many straight segments so that the
length of each segment is much smaller than the wavelength
(the voltage and current at each segment are approximated to
be uniform). Then, V and Jn are expanded using unit pulse
functions and the following relation is obtained [23], [24]:
(0)
Vi
−Ez h
jωµh H0 (kri ) + ΓR J0 (kri )
, (5)
Zii =
=
=
Ii
2πri Hφ
2πkri H (2) (kri ) + Γ(0) J1 (kri )
1
R
where J0 and J1 are the zeroth- and the first-order Bessel
(0)
functions of the first kind; and ΓR represents the reflection
from the outer PMC boundary of the plate pair at ρ = R0
[20]:
(2)
(0)
ΓR = −
H1 (kR0 )
.
J1 (kR0 )
(7)
(6)
Note that equation (5) is analytically limited to cylindrical
structures and to one center port only and is practically useless
in a real PCB analysis. However, it will serve as a basis for
the semi-analytic solution presented in the next subsection.
[U] · V = [H] · I,
B. Semi-analytic solutions
(8)
where V denotes the unknown voltage vector, I denotes the
excitation current vector, and [U] and [H] are (N ×N ) matrices
whose elements are calculated as [23], [24]:
Z
k
R ˙ 0 (2)
Uij = δij −
n̂ H1 (kR)dl0 ,
(9)
2j w R
Z
kηh
(2)
Hij =
H (kR)dl0 ,
(10)
2w w 0
Real PCB design are almost never regularly shaped, are
regularly perforated with multiples vias, and often cutouts in
power-ground plane pair are present (see Fig. 5). Numerical
assessment is necessary when dealing with a real PCB designs.
The solution presented in [18] meshes the power-ground plane
pair and each element is represented with a transmission line.
It is an accurate method, but also an inefficient method, since
the generated netlist of a PCB can get quite large.
4
where δij is the Kronecker Delta; and w is the length of the
boundary element or the perimeter of the via. The integrals in
equations (9) and (10) can be simply evaluated at a distance
between the observation point and the center of the source
point segment [24].
Finally, the impedance matrix can be calculated as:
[Z] = [U]−1 · [H].
(11)
Fig. 6.
Limitation of this method is the via antipad modeling. Every
via antipad can be taken as one additional segment as in [23]
or can be divided into several segments as in [24]. If via
antipads are modeled using one segment, the evaluation of
the contour integral method is faster, but it lacks the accuracy
as the perforations from vias are not taken into account; and
vice versa.
CIM is applied to various types of problems: the return
currents is modeled in [25] for SI/PI so-simulation; the decoupling capacitors and air holes are simulated in [26]; emission
and susceptibility of parallel-plate waveguide are investigated
in [27]; voltage distribution and far-field radiation pattern are
simulated in [24], to name a few.
2) Boundary integral equation method (BIE): BIE starts
from a different definition of the impedance of a parallel plate
waveguide [20]:
Z Z
1
G(r, r0 )dli dlj .
(12)
Zij = −
li lj li lj
.
The line averages, as opposed to area averages, take into
account the perforations from vias.
It can be shown that the solution of the line average
impedance definition is a generalized cylindrical wave defini(0)
tion (equation (5)) [20]. There, ΓR represented the reflection
from the outer PMC boundary of the plate pair at ρ = R,
which can be related to the ratio of the outward and inward
zero-order cylindrical waves, the P ×P radial scattering matrix
for the plate pair [20]:
(f )
where matrix Spp is a P × P matrix denoting direct illuminations among ports [20]:
(2)
H0 (krij ) i 6= j
R
Spp (i, j) =
(15)
0 i = j;
M is the matrix relating ports and boundary elements [20]:
jk R ˙ 0 (2)
n̂ H1 (kR);
(16)
Min = −
4 R
ZM is the method of moment (boundary element) matrix [20]:
jk
˙ 0 (2)
−4 R
R n̂ H1 (kR) m 6= n
(17)
ZM (m, n) =
0.5w m = n;
and H is the matrix relating boundary elements and ports [20]:
(2)
Hnj = H0 (kR), n = 1, 2, · · · , N.
(18)
The impedance is finally calculated using the equation (5).
The limitation of this method (and CIM) is the lowfrequency ill-conditioning that originates from the integral
equation solution when the whole object becomes small in
terms of wavelength. The basic problem is the decoupling
of the current into a solenoidal part and a non-solenoidal
part [28]. Various methods have been developed to solve this
problem [28].
IV. R ESULTS
A. Bare-board simulation
The parallel-plate waveguide shown in Fig. 6 is simulated
using Cavity mode model with single summation and 80
modes taken into account and Boundary integral equation
method. The simulated structure is 50 mm long and 50 mm
wide. The port coordinates are (5 mm, 5 mm), and the port
radius is 1 mm. The frequency range from 1 MHz - 3 GHz,
with 201 logarithmically spaced frequency points is simulated.
The thickness of the substrate is 0.25 mm, relative permitivity
is 4.6, tanδ is 0.02 and the conductivity of the planes is
5.8e7 S/m.
The simulation results are shown in Fig. 7. At frequencies
at which the structure is comparable to or bigger than the
wavelength of interest, both methods show the same results.
BIE fails to predict the impedance correctly at frequencies
below approximately 100 MHz as a consequence of illconditioning of the electric field integral equation [28]. This
can be a great problem since in many applications (including
DC-DC converters) most of the signal spectrum falls into
frequency range from 1 - 100 MHz.
b
SR
(13)
pp = − .
a
A convenient characteristic of a radial scattering matrix (13)
is that it defines the relationship between two ports while all
of the source-free ports are matched. This means that the SR
pp
is calculated from a solid (not perforated) power-ground plane
regardless of the number of vias present, which simplifies its
evaluation.
It can be shown that the SR
pp (i, j) is equal to the total
electric field at the port i under the condition that the port
j is excited and all other ports (except port j and including
port i) are matched [20]. Therefore, method for calculating
the SR
pp matrix is based on the integral equation solution as
in the CIM [20]. The boundary is again divided into many
small segments, then the integral equation is discretized, and
the matrix equation is solved using the method of moments.
Final solution for SR
pp is [20]:
−1
(f )
SR
H,
pp = Spp + MZM
Bare board test case.
(14)
5
Impedance, Z [Ohm]
10
10
10
10
10
10
3
BIE
Cavity mode
2
1
0
Fig. 9.
Test case for evaluation of the influence of ESR and ESL of
decoupling capacitors on EMI of DC-DC converter.
1
TABLE I
O PTIMIZED PARAMETERS OF THE DECOUPLING CAPACITORS .
2
10
6
10
Fig. 7.
7
8
10
Frequency, f [Hz]
10
9
ESR (Ω)
ESL (nH)
C2
0.9
0.1
C3
0.4
1
C4
0.1
2
Bare board test case simulation results.
in the commercial EM solver to verify the EMI performance.
For the reference simulation, the decoupling capacitors are
chosen to be the same, with C = 10 uF, ESR = 0.55 Ohm and
ESL = 0.1 nH. After a series of simulations it is found that
the best set of the parameters with respect to EMI is as shown
in Table I. It can be seen that if the ESR of the capacitors
close to the chip and the ESL of the capacitors far from the
chip are increased, the EMI is decreased.
The impedance profiles for reference and optimized cases
are shown in Fig. 10. It can be seen that the impedance at
low frequencies is sacrificed in order to lower the resonant
peak at approximately 300 MHz. Also, the resonant frequency
is lowered to approximately 250 MHz. Additional resonant
frequency can be seen in optimized impedance profile at
approximately 600 MHz. However, since the frequency component of the typical current waveform decreases with a 40
dB per decade (related to the PWM signal that switches the
FETs), this resonance is not a real treat.
The reduction of the maximum E-field of the optimized case
relative to the reference case is 8 dB at resonant frequencies
(simulated in the commercial EM solver). Since the far-field
analysis is done under the approximation of a broadband
signal and a typical current spectrum decreases with a 40
dB per decade, when scaled with respect to frequency of
the resonance, the actual reduction in maximum E-field is
around 5 dB which still is a great result, especially taking
into account that the optimization is done by hand and that
only ESR and ESL are varied. It is reasonable to expect that
by the automated optimization of the ESR, ESL, position and
number of decoupling capacitors additional reduction could be
achieved.
HS FET
Term
LS FET
Coss
1 nF
Fig. 8.
C1
0.9
0.1
Z-matrix
PCB model
The simulation model of the DC-DC converter.
B. Influence of the ESR and ESL of the Decoupling Capacitors
on EMI of DC-DC converters
The resonance formed by the capacitance of the lowside FET in off state Coss and the total inductance of the
decoupling loop is the main source of ringing of the phase
voltage and for increased EMI [7]. The ESR of the decoupling
capacitors can be increased to limit the resonant current and
therefore reduce the associated EMI [7].
The test case to assess the influence of the ESR and ESL
of the decoupling capacitors is the same as shown in the last
two subsections. Additional decoupling capacitors are placed
at (15 mm, 5 mm), (15 mm, 15 mm), (15 mm, 25 mm) and
(15 mm, 35 mm) (red dots in Fig. 9). The port (observation
point) is connected to the phase voltage node (yellow dot
in Fig. 9). The high-side FET of the DC-DC converter is
modeled as a short circuit, while the low-side FET is modeled
as a off state capacitor Coss = 1 nF. The parameters of the
decoupling capacitors (ESR and ESL; nominal capacitance
and their position are kept the same) are varied in order to
lower the impedance looking from the phase voltage node.
Lowering the impedance lowers the resonant current which
reduces the EMI. The maximum electric far-field is simulated
V. 3D EM SIMULATIONS
The resonance formed by the capacitance of the lowside FET in off state Coss and the total inductance of the
decoupling loop is the main source of ringing of the phase
voltage and for increased EMI [7]. If this loop is minimized,
the EMI would also be minimized.
6
3
Impedance, Z [Ohm]
2.5
Reference model
Optimized model
2
1.5
1
(a) Far-field diagram of the
reference design.
(b) Far-field diagram of the
folded loop design.
0.5
Fig. 12.
0 6
10
10
7
8
10
Frequency, f [Hz]
10
Far-field diagrams of folded loop concept test cases.
9
Boundary integral equation method is recognized to be the
appropriate method to simulate DC-DC converters. Boundary
integral equation method is implemented in Matlab and the
interface to SPICE (SPICE netlister) is written.
The influence of ESR and ESL on the EMI of a DC-DC
converter design is evaluated. The ESR of the capacitors close
to the chip and the ESL of the capacitors far from the chip
are increased to reduce the EMI. The far-field analysis is done
in the commercial EM solver and the hand-optimized results
show the reduction of maximum electric field by 5 dB relative
to the reference test case.
The final goal of this work is to create the analysis and
optimization tool for DC-DC converters with respect to the
EMC. Since this is the work in progress, additional 3D EM
simulations are done to assess the issues related to the DCDC converter from the INVENT project. The folded loop
placement of decoupling capacitors decreased the EMI by 3
dB.
Future work includes:
Fig. 10. Impedance profile of the reference and optimized parameters of the
decoupling capacitors.
The idea presented here is to fold the loop and to split one
big loop into two smaller ones, in which the current would go
in opposite directions therefore canceling the magnetic flux
and reducing the EMI.
The structures simulated are 20 mm long and 10 mm
wide. The thickness of the substrate is 70 um, dielectric
constant is 4.6 and tanδ is 0.02. In the reference design, the
current flow forms one big loop, while in the folded loop
design this one loop is broken into two smaller loops that are
folded to minimize the magnetic flux and therefore minimize
the EMI. This is achieved by placing decoupling capacitors
rotated by 180 degrees when compared to the reference design.
The simulations are done in the commercial EM solver. The
maximum E-field is decreased by 3.36 dB when the resonance
loop is folded. The original and modified PCB layouts are
shown in Fig. 11. The far-field diagrams for both structures
are shown in Fig. 12.
1) Implement a low-frequency correction for contour integral equation.
2) Include current loops when calculating far-field diagrams.
3) Add a near-field calculation.
4) Simulate band limited instead of broadband sources.
5) Add via models.
6) Write the optimization algorithm.
7) Consider including thermal parameters in the optimization algorithm.
R EFERENCES
(a) Reference design.
Fig. 11.
(b) Folded loop design.
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VI. C ONCLUSION
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