Academic Update
San Jose State University Simulates the Thermal Characterization
of Fan-in Package-on-Packages
The need to integrate more device
technology in a given board space for
handheld applications such as mobile
phones and medical devices has driven the
adoption of innovative packages which
stack such devices in the vertical or third
dimension (3D). Further reduction of
size, thickness, and cost of this Packageon-Package (PoP) solution was possible
through the development of Fan-in Packageon-Package (FiPoP) technology which
enabled more device integration while
maintaining reliability requirements of
typical handsets.
One common mode of failure of FiPoPs
occurs due to thermal conditions in the stack.
Providing a thermal path for heat dissipation
is the only option to maintain the junction
temperatures in these packages due to
space and cost constraints. Though various
factors affect package thermal performance,
graduate student Nandini Nagendrappa with
guidance from Professor Nicole Okamoto
and Professor Fred Barez of San Jose State
University, chose to focus on varying the
internal design parameters only to observe
the change in thermal performance.
Based on the research of earlier generation
models, the parameters chosen for analysis
in this work included (a) number of thermal
vias (b) solder ball Input/Output (I/O)
density and (c) die size. Geometrical and
materials parameters for a typical FiPoP
were acquired from STATS ChipPac Ltd.
The stacked package within FiPoP chosen
for analysis included two metal layers, 14
x 14 mm body size, 9 mm x 9 mm die size,
0.075 mm thickness for both top and bottom
packages, and 0.5 mm solder ball pitch.
For this study a test package was modeled
in Abaqus/CAE, as it provides the ability
to create intricate parts at the micron level,
which was required to model the package
involving vias, traces, and wirebonds.
JEDEC-specified standards and environment
were applied to carry out the steady-state
finite element thermal analysis. Thermal
boundary conditions applied were power
dissipation, ambient temperature, and
a combined heat transfer coefficient for
natural convection and radiation (typical of
still air conditions). Also, changes in thermal
resistance were examined from one test run
to another rather than absolute values.
www.simulia.com
(Top) FiPoP model with stacked top and bottom package. (Bottom) Bottom package with interposer close-up
copper traces and wire bonds.
The simulation on the stack was carried
out by either powering (loading) the top or
bottom package one at a time or by powering
both. This was done to study the effect of
thermal loads separately and combined.
In development of mobile handsets and
medical devices, designers must pay
particular attention to the design of efficient
heat paths to the die package. Heat flows
from the silicon die to the ambient through
two main mechanisms. One is through
conduction from the silicon die of both top
and bottom packages through the die attach,
substrate, and solder balls to the PCB. The
other is through conduction from the die
through the mold compound to the top and
sides of the package. From the package
the heat is transferred to the surroundings
through convection and radiation. A surfaceto-surface contact approach was adopted in
Abaqus to define the electrical/thermal I/O
path. The contact detection toolset in Abaqus/
CAE automatically generated all the required
surfaces and interactions making it very easy
to define the extensive thermal contacts in
this model.
The importance of the analysis results lies in
the change in resistance from one simulation
to the next rather than the absolute value,
since the total resistance includes the
convection resistance which is a constant
for all cases. For each case, absolute values
of results were obtained and percentage
changes between simulations were tabulated.
The analysis predicted that the thermal
resistance of the bottom package of a FiPoP
decreases with the increase in the number
of thermal vias and solder balls placed
under the package. As expected, the thermal
resistance of the entire package increases as
the die size drops.
The article is based on the paper presented at the
26th IEEE Semiconductor Thermal Measurement &
Management Symposium - 2010, entitled “Thermal
Characterization of Fan-in Package-on-Packages,” by
Nandini Nagendrappa, Nicole Okamoto, and Fred Barez
from San Jose State University, San Jose, California,
USA.
For More Information
www.engr.sjsu.edu
INSIGHTS
May/June 2010 21