EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
Status: Engineering
Features:
• VDS, 100V
• Maximum RDS(on), 550 mΩ
• ID , 1 A
• Pb-Free (RoHS Compliant), Halogen Free
Applications:
• High Frequency DC-DC Conversion
EPC2037 eGaN® FETs are supplied only in
passivated die form with solder balls
• Wireless Power Transfer
Die Size: 0.9 mm x 0.9 mm
• LiDAR/Pulsed Power Applications
• Class-D Audio
MAXIMUM RATINGS
Parameter
Value
Maximum Drain – Source Voltage
Gate – Source Maximum Voltage Range
Continuous Drain Current, (TA = 25 °C, RθJA = 120 °C/W)
Maximum Pulsed Drain Current, 25 °C, Tpulse = 300 µs
Optimum Temperature Range
100 V
-4 V < VGS < 6 V
1A
2.4 A
-40 °C < TJ < 150 °C
STATIC CHARACTERISTICS
Conditions
Parameter
Maximum Drain – Source Leakage
Maximum RDS(on)
Typical RDS(on)
Gate – Source Threshold Voltage
Gate – Source Maximum Positive Leakage
Gate – Source Maximum Negative Leakage
VDS = 80 V, VGS = 0 V
VGS = 5 V, ID = 0.1 A
VGS = 5 V, ID = 0.1 A
VDS = VGS, ID = 0.08 mA
VGS = 5 V
VGS = -4 V
Value
0.1 mA
550 mΩ
400 mΩ
0.8 V < VGS(TH) < 2.5 V
1 mA
-0.1 mA
TJ = 25 °C unless otherwise stated
Specifications are with Substrate shorted to Source
Subject to Change without Notice
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
DYNAMIC CHARACTERISTICS
Conditions
Parameter
Typical Value
12.5 pF
CISS (Input Capacitance)
COSS (Output Capacitance)
6 pF
VDS = 50 V, VGS = 0 V
0.1 pF
CRSS (Reverse Transfer Capacitance)
QG (Total Gate Charge)
115 pC
VDS = 50 V, ID = 0.1 A, VGS = 5 V
30 pC
QGS (Gate to Source Charge)
QGD (Gate to Drain Charge)
23 pC
VDS = 50 V, ID = 0.1 A
27 pC
QG(TH) (Gate Charge at Threshold)
QOSS (Output Charge)
VDS = 50 V, VGS = 0 V
530 pC
0
QRR (Source-Drain Recovery Charge)
TJ = 25 °C unless otherwise stated
Specifications are with Substrate shorted to Source
THERMAL CHARACTERISTICS
TYP
RθJC
RθJB
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Board
Thermal Resistance, Junction to Ambient (Note 1)
14
79
100
°C/W
°C/W
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
Subject to Change without Notice
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
25 °C
2
ID - Drain Current (A)
ID - Drain Current (A)
2
1.5
VGS
VGS = 5 V
1
VGS
VGS = 4 V
VGS = 3 V
VGS
0.5
125 °C
VDS = 3 V
1.5
1
0.5
VGS = 2 V
VGS
0
0
0
1
1.5
2
2.5
0.5
VDS - Drain-to-Source Voltage (V)
3
IDID=0.1
= 0.1AA
= 0.5AA
IDID=0.5
1200
IDID=1
= 1AA
= 2AA
IDID=2
800
400
0
2
2.5
3
3.5
4
4.5
VGS - Gate-to-Source Voltage (V)
1
1.5
2
2.5
3
3.5
4
VGS - Gate-to-Source Voltage (V)
4.5
5
Figure 4: RDS(on) vs. VGS for Various Drain Temperatures
1600
RDS(on) - Drain-to-Source Resistance (mΩ)
RDS(on) - Drain-to-Source Resistance (mΩ)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
0.5
5
1600
25 °C
125 °C
1200
ID = 0.1 A
800
400
0
2
Figure 5a: Capacitance (Linear Scale)
2.5
3
3.5
4
4.5
VGS - Gate-to-Source Voltage (V)
5
Figure 5b: Capacitance (Log Scale)
20
10
CISS
CISS ==CGD
CGD ++CGS
CGS
15
CRSS ==CGD
CGD
CRSS
Capacitance (pF)
Capacitance (pF)
COSS
COSS == CGD
CGD ++ CSD
CSD
10
5
0
COSS
C ==CGD
C ++CSD
C
OSS
1
GD
SD
CISS
CISS==CGD
CGD+ +CGS
CGS
CRSS ==CGD
CGD
CRSS
0.1
0.01
0
20
40
60
80
VDS - Drain-to-Source Voltage (V)
Subject to Change without Notice
100
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0
20
40
60
80
VDS - Drain-to-Source Voltage (V)
COPYRIGHT 2015
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
Figure 6: Gate Charge
Figure 7: Reverse Drain-Source Characteristics
4
ISD - Source-to-Drain Current (A)
VGS - Gate-to-Source Voltage (V)
5
ID = 0.1 A
VDS = 50 V
3
2
1
0
1.5
1
0.5
0
0
20
40
60
80
QG - Gate Charge (pC)
100
120
0
Figure 8: Normalized On Resistance vs. Temperature
0.5
1 1.5 2 2.5 3 3.5 4
VSD - Source-to-Drain Voltage (V)
4.5
5
Figure 9: Normalized Threshold Voltage vs. Temperature
2
1.40
Normalized Threshold Voltage
Normalized On-State Resistance - RDS(on)
25 °C
125 °C
2
ID = 0.1 A
VGS = 5 V
1.8
1.6
1.4
1.2
1
1.30
ID = 0.08 mA
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.8
-25
0
25
50
75
100 125 150
TJ - Junction Temperature (°C)
175
-25
0
25
50
75 100 125 150
TJ - Junction Temperature (°C)
175
Figure 10: Gate Current
0.35
25 °C
IG - Gate Current (mA)
0.3
125 °C
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
Subject to Change without Notice
6
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All measurements were done with substrate shorted to source
COPYRIGHT 2015
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
Figure 11: Transient Thermal Response Curves
Junction-to-Board
ZϴJB, Normalized Thermal Impedance
1E+01
Duty Cycle
0.1
1E-1
0.5
0.1
0.01
1E-2
0.05
0.02
0.001
1E-3
0.01
Single Pulse
0.0001
1E-4
1E-5
10-5
1E-4
10-4
1E-3
1E-2
1E-1
10-3
10-2
10-1
tp - Rectangular Pulse Duration [s]
1E+0
1
1E+1
10+1
Junction-to-Case
ZϴJC, Normalized Thermal Impedance
1E+01
Duty Cycle
0.1
1E-1
0.5
0.2
0.01
1E-2
0.1
0.05
0.02
0.001
1E-3
0.01
Single Pulse
0.0001
1E-4
10-6
1E-6
10-5
1E-5
10-4
10-3
10-2
1E-4
1E-3
1E-2
tp - Rectangular Pulse Duration [s]
10-1
1E-1
1
1E+0
Figure 12: Safe Operating Area
ID - Drain Current (A)
1
Pulse Width
0.1
100 ms
10 ms
1 ms
100 μs
0.01
0.1
1
10
VDS - Drain Voltage (V)
100
TJ = Max Rated, TC = +25˚C, Single Pulse
Subject to Change without Notice
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
DIE MARKINGS
AC
Part Number
YYY
Die orientation dot
EPC2037ENGR
Laser Marking
Part # Marking Lot_Date Code
Line 1
Marking Line 2
AC
YYY
Gate Pad bump is
under this corner
DIE OUTLINE
Solder Bar View
All measurements in micrometers (µm)
A
g
X4
DIM
2
d
B
4
e
3
c
MIN
Nominal
MAX
A
870
900
930
B
870
900
930
c
450
450
450
d
450
450
450
e
210
225
240
f
210
225
240
g
187
208
229
f
1
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
MICROMETERS
SEATING PLANE
Subject to Change without Notice
815 Max
165 +/- 17
(625)
Side View
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EPC2037 – Enhancement Mode Power Transistor
Preliminary Specification Sheet
RECOMMENDED LAND PATTERN
(Units in µm)
900
190
X4
The land pattern is solder mask defined
Solder mask is 10 µm smaller per side than bump
1
450
900
3
225
4
450
225
2
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
RECOMMENDED STENCIL
(Units in µm)
900
Recommended stencil should be 4mil (100µm) thick, must
be laser cut, openings per drawing.
200
225
450
Additional assembly resources available at http://epcco.com/epc/DesignSupport/AssemblyBasics.aspx
225
900
450
Intended for use with SAC305 Type 4 solder, reference
88.5% metals content
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein. Engineering devices, designated with
an ENG* suffix at point of purchase, are first article products that EPC is preparing for production release. Specifications may change on final production release of the
device. If you have questions please contact us. EPC does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights, nor the rights of other.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
Subject to Change without Notice
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COPYRIGHT 2015
Revised December, 2015
Page 7