EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
Status: Engineering
Features:
• VDS, 15V
• Maximum RDS(on), 28 mΩ
EPC2040 eGaN® FETs are supplied only in
passivated die form with solder balls
• ID, 3.4 A
• Pulsed ID, 28 A
Die Size: 0.85 mm x 1.20 mm
• Pb-Free (RoHS Compliant), Halogen Free
Applications:
• Pulsed Laser Driver
• LiDAR/Pulsed Power Applications
MAXIMUM RATINGS
Parameter
Value
Maximum Drain – Source Voltage
Gate – Source Maximum Voltage Range
Continuous Drain Current, (TA = 25 °C, RθJA = 210 °C/W)
Maximum Pulsed Drain Current, 25 °C, Tpulse = 300 µs
Optimum Temperature Range
15 V
-4 V < VGS < 6 V
3.4 A
28 A
-40 °C < TJ < 150 °C
STATIC CHARACTERISTICS
Conditions
Parameter
Maximum Drain – Source Leakage
Maximum RDS(on)
Typical RDS(on)
Gate – Source Threshold Voltage
Gate – Source Maximum Positive Leakage
Gate – Source Maximum Negative Leakage
VDS = 12 V, VGS = 0 V
VGS = 5 V, ID = 1.5 A
VGS = 5 V, ID = 1.5 A
VDS = VGS, ID = 1 mA
VGS = 5 V
VGS = -4 V
Value
0.25 mA
28 mΩ
22 mΩ
0.8 V < VGS(TH) < 2.5 V
1.2 mA
-0.25 mA
TJ = 25 °C unless otherwise stated
Subject to Change without Notice
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EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
DYNAMIC CHARACTERISTICS
Parameter
Conditions
Typical Value
100 pF
CISS (Input Capacitance)
COSS (Output Capacitance)
VDS = 6 V, VGS = 0 V
25 pF
CRSS (Reverse Transfer Capacitance)
QG (Total Gate Charge)
VDS = 6 V, ID = 1.5 A, VGS = 5 V
VDS = 6 V, ID = 1.5 A
160 pC
200 pC
QG(TH) (Gate Charge at Threshold)
QOSS (Output Charge)
930 pC
270 pC
QGS (Gate to Source Charge)
QGD (Gate to Drain Charge)
70 pF
VDS = 6 V, VGS = 0 V
450 pC
0
QRR (Source-Drain Recovery Charge)
TJ = 25 °C unless otherwise stated
Specifications are with Substrate shorted to Source
Subject to Change without Notice
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EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
Figure 4: RDS(on) vs. VGS for Various Drain Temperatures
RDS(on) - Drain-to-Source Resistance (mΩ)
RDS(on) - Drain-to-Source Resistance (mΩ)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
80
ID
ID =1.5
= 1.5AA
ID =3
= 3.0
ID
A A
60
ID
ID =4.5
= 4.5AA
ID =6
= 6.0
ID
A A
40
20
0
2.5
3
3.5
4
4.5
VGS - Gate-to-Source Voltage (V)
5
25 °C
125 °C
60
ID = 1.5 A
40
20
0
2.5
Figure 5a: Capacitance (Linear Scale)
3
3.5
4
4.5
VGS - Gate-to-Source Voltage (V)
5
Figure 5b: Capacitance (Log Scale)
200
1000
150
COSS
CGD
+ CSD
COSS == C
GD + CSD
COSS
==CGD
C
C ++CSD
C
CISS =
= CGD
CGD +
+ CGS
CGS
CISS
CISS ==CGD
CGD++CGS
CGS
CISS
OSS
Capacitance (pF)
Capacitance (pF)
80
CRSS =
CGD
CRSS
= CGD
100
50
0
GD
SD
CRSS==CGD
CGD
CRSS
100
10
0
2.5
5
7.5
10
12.5
VDS - Drain-to-Source Voltage (V)
Subject to Change without Notice
15
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0
2.5
5
7.5
10
12.5
VDS - Drain-to-Source Voltage (V)
COPYRIGHT 2016
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EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
Figure 6: Gate Charge
Figure 7: Reverse Drain-Source Characteristics
VGS - Gate-to-Source Voltage (V)
5
4
ID = 1.5 A
VDS = 6 V
3
2
1
0
0
0.2
0.4
0.6
0.8
QG - Gate Charge (nC)
1
Figure 8: Normalized On Resistance vs. Temperature
Figure 9: Normalized Threshold Voltage vs. Temperature
Figure 10: Gate-Source Characteristics
Subject to Change without Notice
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EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
DIE OUTLINE
Solder Bar View
A
f
e
DIM
3
6
MICROMETERS
MIN
Nominal
MAX
A
820
850
880
B
1170
1200
1230
2
5
B
c
c
400
d
187
208
229
e
185
200
215
f
210
225
240
c
d
1
4
Pad 1 is Gate;
Pads 2 & 5 are Drain;
Pads 3, 4, 6 are Source;
c
Side View
Subject to Change without Notice
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EPC2040 –Enhancement Mode Power Transistor
Preliminary Specification Sheet
RECOMMENDED LAND PATTERN
(Solder Mask Defined, Units in µm)
Pad 1 is Gate;
Pads 2 & 5 are Drain;
Pads 3, 4, 6 are Source;
RECOMMENDED STENCIL DESIGN (Units in µm)
850
200
225
400
Recommended stencil should be 4mil (100µm) thick, must
be laser cut, openings per drawing.
400
1200
R 60
200
Intended for use with SAC305 Type 4 solder, reference
88.5% metals content
Additional assembly resources available at http://epcco.com/epc/DesignSupport/AssemblyBasics.aspx
400
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein. Engineering devices, designated with
an ENG* suffix at point of purchase, are first article products that EPC is preparing for production release. Specifications may change on final production release of the
device. If you have questions please contact us. EPC does not assume any liability arising out of the application or use of any product or circuit described herin;
neither does it convey any license under its patent rights, nor the rights of other.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
Subject to Change without Notice
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COPYRIGHT 2016
Revised Janaury, 2016
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