Back-to-Back Connected Five-Level Diode-Clamped
PWM Converters for Motor Drives
Hatti Natchpong, Yosuke Kondo, and Hirofumi Akagi, Fellow, IEEE
Department of Electrical and Electronic Engineering
Tokyo Institute of Technology, Japan
Email: hatti.n.aa@m.titech.ac.jp, kondo.y.ac@m.titech.ac.jp, and akagi@ee.titech.ac.jp
Abstract—This paper addresses a medium-voltage adjustablespeed motor drive consisting of two five-level diode-clamped
PWM converters connected back-to-back. It is followed by
designing, constructing and testing a 200-V down-scaled model
to verify the validity and effectiveness of the medium-voltage
motor drive. This down-scaled model has four split dc capacitors
equipped with a voltage-balancing circuit using two bidirectional
buck-boost choppers. The two five-level converters are based on
sinusoidal PWM (SPWM) with a carrier frequency of 3 kHz. The
motor tested in this paper is a three-phase four-pole induction
motor rated at 200 V, 5.5 kW and 60 Hz. Experimental waveforms
show that the four split dc-capacitor voltages are well balanced in
any operating conditions, and that the total harmonic distortion
(THD) values of the input line current and the output motor
current are 3.9% and 3.35%, respectively.
I. I NTRODUCTION
Since the three-level neutral-point clamped (NPC), or diodeclamped, PWM inverter was invented in 1980 [1], it has been
practically applied to steel mill drives, traction drives, STATCOMs and UPFCs. Recently, attention has been paid to fourlevel and five-level diode-clamped PWM inverters intended for
higher-voltage and higher-power applications [2]. Significant
developments of power semiconductor technology has made
the so-called ”high-voltage IGBT” rated at 3.3/4.5/6.5 kV [3]
available from the market.
The motivation of introducing the five-level inverter into
a medium-voltage motor drive is to eliminate heavy, costly
transformers from the motor drive, as well as to rely on lower
common-mode voltage and lower dv/dt that lead to lower
stress on motor bearings and motor windings, and higher
voltage capacity [4]-[6]. However, a five-level diode-clamped
PWM inverter with a three-phase diode rectifier as the front
end suffers from voltage imbalance of four split dc capacitors.
This paper addresses a medium-voltage adjustable-speed
motor drive system based on two five-level diode-clamped
PWM converters connected back-to-back, with focus on
voltage-balancing control of four split dc capacitors. A 200V, 5.5-kW down-scaled motor drive system is designed, constructed, and tested to verify the viability and effectiveness. It
consists of a set of five-level diode-clamped PWM rectifier and
inverter with the same carrier frequency as 3 kHz, a voltagebalancing circuit using two bidirectional buck-boost choppers
with the same carrier frequency as 3 kHz, and an induction
motor rated at 200 V and 5.5 kW. Experimental waveforms
observed from the down-scaled system verify satisfactory sys-
1-4244-0844-X/07/$20.00 ©2007 IEEE.
tem performance including voltage-balancing performance in
any operating conditions. Moreover, experimental results agree
well with theoretical results including dc currents flowing in
the bidirectional buck-boost choppers for achieving voltagebalancing control.
II. D ESIGN C ONCEPT OF THE 6.6- K V T RANSFORMERLESS
M OTOR D RIVE S YSTEM
A. Five-Level Diode-Clamped PWM Rectifier and Inverter
Fig. 1 shows the 6.6-kV 1-MW transformerless motor drive
system, where the five-level rectifier is directly connected to
the 6.6-kV grid, and the five-level inverter to the 6.6-kV motor
without transformer. Each switching device is either single
4.5-kV IGBT or a string of three 1.7-kV IGBTs connected
in series. A single 4.5-kV diode can be used as a clamping
diode. When the rectifier and the inverter have the same carrier
frequency as 3 kHz, the actual switching frequency of each
IGBT ranges from 0 to 1.5 kHz. The weight of the 6.6-kV,
1-MVA, 50-Hz transformer ranges from 3,000 to 4,000 kg,
while that of the 6.6-kV, 1-MW rectifier or inverter ranges
from 1,000 to 2,000 kg. Thus, it is reasonable to eliminate the
transformer from the 6.6-kV motor drives system in terms of
reducing cost, weight and physical size.
B. Review of Voltage-Balancing Control of The Four Split DC
Capacitors
The four common dc capacitors connected in series between
the rectifier and the inverter has the following five node points
in the dc link: the outer positive point P2, the inner positive
point P1, the mid-point M, the inner negative point N1, and
the outer negative point N2, as shown in Fig. 1. Whenever the
motor is operated either in powering mode or on regenerative
mode, an amount of dc current would flows into, or out of, the
two inner points P1 and N1. This causes voltage imbalance of
the four capacitors unless special care were taken of voltage
balancing.
Existing solutions to voltage imbalance inherent in the
motor drive system can be classified into the following two
groups; one is based on sophisticated switching control [7]-[9],
and the other is based on additional hardware installation [10].
The former is more preferable in cost than the second one.
The authors of [7] have proposed a practical switching-angle
control method for staircase modulation or the so-call ”onepulse PWM.” It appropriate adjusts all the switching angles of
1456
Rectifier
Voltage-balancing
circuit
Inverter
6 kV
P2
P1
6.6 kV
6.6 kV
M
IM
N1
N2
-6 kV
Fig. 1.
The 6.6-kV transformerless motor drive system based on the five-level diode-clamped PWM rectifier and inverter connected back-to-back.
both rectifier and inverter so as to balance the four capacitor
voltages, in addition to sinusoidal line current control, dc-link
voltage regulation, and sinusoidal motor current control. The
latter is superior to the first one in system performance and
adaptability to existing triangle-carrier modulation and spacevector modulation without mutual interference between current
control and voltage-balancing control.
From these considerations, the authors have decided to connect positive and negative bidirectional buck-boost choppers
to the positive and negative points. Hence, each of the rectifier
and the inverter devotes itself to concentrating on each highpriority task pursuing better system performance including
higher reliability and robustness, while the positive bidirectional buck-boost chopper devotes itself to voltage balancing
between vP 2−P 1 and vP 1−M , and the negative buck-boost
chopper plays its part between vM −N 1 and vN 1−N 2 .
III. S YSTEM C ONFIGURATION
Fig. 2 shows the 200-V, 5.5-kW laboratory motor drive
system that is designed, contructed, and tested in this paper.
Fig. 3 shows the dc-link voltage and the individual split dc
capacitor voltages. Table I sumarizes the circuit parameters of
the experimental system.
The rectifier and the inverter with the same carrier frequency
as 3 kHz are operated independently, and the two buckboost choppers with the same carrier frequency as 3 kHz
are controlled independently. The rectifier is connected to
the 200 V laboratory ac mains through an ac inductance of
LAC = 5.2%. No switching ripple filter is installed upstream
of LAC . The inverter is directly connected to a 200-V, 5.5kW induction motor without any inductor. The motor is
TABLE I
R ATINGS AND CIRCUIT PARAMETERS IN F IG . 1.
Power rating
5.5 kW
Rated ac voltage
200 V
Inductance of ac link inductor
LAC
1.2 mH (5.2% )
Resistance of ac link inductor
RAC
2 mΩ (0.03 % )
DC capacitor voltage
Vdc
85 V
Split dc capacitor
Cdc
10 mF
DC link voltage
4Vdc
340 V
Unit capacitance constant
H
26 ms (340V)
Chopper inductor
LP =LN
4.2 mH
Carrier frequency
fC
3 kHz
on a three-phase, 50-Hz, 200-V, 5.5-kW, 16-A base
mechanically coupled with a permanent-magnet synchronous
generator connected to a three-phase resistive load.
Fig. 4 shows the sinusoidal PWM technique used in the
experimental system, which is based on a single reference
signal e∗ and four 3-kHz carrier signals with different dcbias voltages. The unit capacitance constant H [s] in Table I
is defined by the ratio of the energy [J] stored in the dc-link
capacitor with respect to the power rating [W]. Since each of
the four dc-link capacitors has the same capacitance as Cdc
= 10 mF, the unit capacitance constant H is 26 ms under 2.5
mF, 340 V, and 5.5 kW.
IV. A NALYSIS OF DC M EAN C URRENT F LOWING INTO
T WO N ODES P1 AND M
When the dc mean currents flowing into, or out of, nodes P1,
N1, and M are nonzero, voltage imbalance occures between
the corresponding dc capacitors. The dc mean currents flowing
1457
Rectifier
Voltage-balancing
circuit
iLP
TR1
iRP 1
TR2
LP
P2
TI1
iIP 1
TI2
P1
TI3
TR3
200 V
50 Hz
DC
CT
vS
iS LAC
eR
iRM
TR4
TR5
TR7
iS
PLL
LN
TR8
A/D
iO 200 V, 5.5 kW
TI4
TI5
iLN
TR6
vS
iIM
M
PT
f∗
∗
Vdc
Inverter
IM
eO
TI6
N1
TI7
TI8
N2
24
θ
Calculation
(DSP)
e∗
PWM
(FPGA)
4
24
4
A/D
Fig. 2.
P2
P1
M
vP 2−P 1
The 200-V 5.5-kW laboratory motor drives system.
vP 2−M
vP 1−M
B. The DC Mean Current Flowing into Node P1
It is assumed that the rectifier line-to-neutral voltage reference e∗ and the source or line current iS are the following
sinusoidal waveforms.
√
e∗ =
2E sin ωt
(3)
√
2I sin(ωt + φ)
iS =
√
√
=
2Id sin ωt − 2Iq cos ωt
(4)
vP 2−N 2
vM −N 1
N1
N2
Fig. 3.
vM −N 2
vN 1−N 2
The dc-link voltage and split dc-capacitor voltages.
into, or out of, nodes P1 and N1, come from the same principle
of operation. This section conducts theoretical analysis of the
dc mean curents of iRP 1 and iRM in the rectifier.
A. Voltage Reference and Duty Factor
Fig. 5 shows the relations between a voltage reference e∗
and duty factors DP 1 and DM . A duty factor represents a
ratio of a time interval, during which the line or motor current
flows into, or out of, a node, with respect to a period of the
line frequency (50 Hz) or the inverter frequecy. Thus, the
instantaneous current flowing into, or out of, a node is given
as the product of the corresponding duty factor and the line
or motor current. Assuming that the PWM carrier frequency
is much higher than the maximal inverter frequency, the duty
factors DP 1 and DM are given by
⎧
(VN 2−M ≤ e∗ < 0)
⎨ 0
∗
(0 ≤ e∗ < VP 1−M )
e /VP 1−M
DP 1 =
(1)
⎩
∗
2 − e /VP 1−M (VP 1−M ≤ e∗ ≤ VP 2−M ),
DM
⎧
0
⎪
⎪
⎨
1 + e∗ /VP 1−M
=
1 − e∗ /VP 1−M
⎪
⎪
⎩
0
(VN 2−M ≤ e∗ < VN 1−M )
(VN 1−M ≤ e∗ < 0)
(0 ≤ e∗ < VP 1−M )
(VP 1−M ≤ e∗ ≤ VP 2−M ).
(2)
Here, E is the rms value of the rectifier line-to-neutral
voltage reference. The dc mean current īRP 1 in a steady state
can be defined as an average value of the instantaneous current
flowing into the node P1 over a period of the line cycle T (=
20 ms). Therefore, īRP 1 is given by
īRP 1
=
3
T
0
Let the time, when
It is given by
TVP 1−M
T
√
6
DP 1 iS dt =
T
T
4
0
DP 1 iS dt.
(5)
2E is equal to VP 1−M , be TVP 1−M .
1
= sin−1
ω
VP 1−M
√
2E
.
(6)
√
2E ≥ VP 1−M , īRP 1 is given by
6Id
E
4ωTVP 1−M − 2 sin(2ωTVP 1−M )
īRP 1 =
ωT VP 2−M
√
(7)
−π} +2 2 cos(ωTVP 1−M ) .
√
When 2E ≤ VP 1−M , īRP 1 is given by
6Id
Eπ
.
(8)
īP =
ωT VP 2−M
When
1458
VP 2−M
e∗
DC-link voltage control
+
PI
–
∗
4Vdc
VP 1−M
vSu
vSv
vSw
VN 1−M
VN 2−M
Fig. 4. A converter voltage reference signal and four carrier signals for the
5-level converter.
DM
iSu
iSv
iSw
1
Fig. 5.
−Vdc
trans.
0
e∗
Vdc
īRP 1 − īIP 1
(9)
Fig. 8 shows the theoretical results obtained from (9) when
the inverter is operated with the rated constant-torque load,
while Fig. 9 shows those when the inverter is operated with a
fan/blower-like load.
C. The DC Mean Current Flowing into Node M
The dc current flowing into node M, īM gets zero, irrespective of the rectifier or the inverter.
3 T
DM iS dt = 0.
(10)
īM =
T 0
Equation (10) implies that as long as the voltage reference
e∗ and the source current iS are sinusoidal waveforms, no dc
mean current flows into node M. However, in an actual fivelevel converter, a small amount of dc mean current may flow
into node M, because component tolerances and tuning errors
exist in both power and control circuits. Therefore, the voltages vP 2−M and vM −N 2 might get imbalanced. Fortunately,
applying the volt-per-hertz control to the five-level inverter
makes vP 2−M and vM −N 2 automatically balanced because of
existance of the following internal negative feedback loop that
an increased capacitor voltage is accompanied by an increased
loss, which in turn makes the capacitor voltage decrease.
V. C ONTROL OF T HE F IVE -L EVEL R ECTIFIER AND
I NVERTER
A. Overall Control
The control system is based on a fully-digital control circuit
using DSPs and FPGAs. Each data sampling of the source
voltages and currents, and the four dc capacitor voltages are
e∗
Rd
e∗
Rq
e∗
Ru
e∗
Rv
e∗
Rw
Inv.
d-q
trans.
iSd
trans.
iSq
A control block diagram of the rectifier.
Voltage
Current
regulator
regulator
∗
i∗LP
vLP
+
+
PI
P
–
–
2Vdc
It should be noted that the reactive current Iq is excluded
from (7) and (8), and that the active current Id and the output
voltage E determine īRP 1 . When attention is paid to the
direction of iIP 1 , the dc mean current flowing in the positive
chopper inductor LP , īLP is given as the substraction of īIP 1
from īRP 1 .
=
vSq
Decoupled
current
control
d-q
Fig. 6.
vP 2−P 1 +
–
vP 1−M
Converter voltage e∗ and duty factors DP 1 and DM .
īLP
vSd
d-q
DP 1
D
−2Vdc
i∗
Sd
vP 2−N 2
0
Comparator
Gate
signals
iLP
Carrier signal (3 kHz)
Fig. 7. The control block diagram of the positive chopper in the voltagebalancing circuit.
performed at every top and bottom of the four carrier signals
with different dc-bias voltages. Fig. 6 shows the control block
diagram of the rectifier. It consists of decoupled current control
that have been described in [11], and dc-link voltage control.
The so-called ”volt-per-hertz” control with a base voltage and
frequency of 200 V and 60 Hz is applied to drive the 200-V,
5.5-kW induction motor. The five-level rectifier and inverter
use four common carrier signals, as shown in Fig. 4.
B. DC-Link Voltage Control
The dc-link voltage between P2 and N2 is regulated by a
PI controller that detects vP 2−N 2 and compares it with its dc∗
. The PI controller is designed to
link voltage reference 4Vdc
have a proportional gain of 0.25 A/V, and an integral gain of
0.6 A/V·s.
C. Voltage-Balancing Control
As shown in Fig. 2, the voltage-balancing circuit consists
of two positive and negative buck-boost choppers operated
independently. Fig. 7 shows the control block diagram of
the positive chopper for achieving voltage balancing between
vP 1−M and vP 2−P 1 . A proportional-plus-integral (PI) controller for voltage regulation is designed to have a proportional
gain of 5.0 A/V, and an integral gain of 0.02 A/V·s. A
proportional (P) controller for current regulation is designed
to have a proportional gain of 0.1 V/A. A common 3-kHz
triangle-carrier signal is used to produce the gate signals for
the two choppers.
VI. ACTUAL S WITCHING F REQUENCIES OF T HE IGBT S IN
T HE F IVE -L EVEL C ONVERTER
The five-level diode-clamped converter consists of a string
of eight IGBTs per leg. As shown in Fig. 2, the eight IGBTs
1459
TABLE II
C URRENT THD AND HARMONIC CURRENTS OF iSu AND iOu
200 V, 5.5 K W, EXPRESSED AS %
DC mean choppercurrent [A]
20
Fig. 8.
load.
īIP 1
15
Rec. Side
Inv. Side
|īLP |
3rd
0.4
0.3
4th
0.3
0.4
5th
2.8
2.8
7th
1.4
1.6
11th
1.9
0.7
40th
0.3
1.0
200
īRP 1
vSu
5
0
[V]
0
0.3
-200
30
0.4
0.5 0.6 0.7 0.8 0.9
Inverter modulation index
iSu
1.0
0
[A]
eRu−M
[V]
DC mean chopper current [A]
2nd
0.8
0.2
60 H Z ,
10
Theoretical dc mean chopper current in the rated constant-torque
Fig. 9.
THD
3.9
3.5
AT
eRu−v
15
-30
200
0
-200
400
0
[V]
-400
360
vP 2−N 2
10
īIP 1
[V]
320
200
|īLP |
5
īRP 1
0
0.3
340
[V]
vP 1−M
0
-200
40
0.4
0.5 0.6 0.7 0.8 0.9
Inverter modulation index
iOu
1.0
[A]
Theoretical dc mean chopper current in a fan/blower-like load.
eIu−M
[V]
are referred to as T1, T2, · · · , and T8 from the top to the
bottom. During the converter voltage reference e∗ is higher
than VP 1−M , T1 and T5 are repetitively switched on and off,
and the other IGBTs keep unswitched. Moreover, during 0 <
e∗ < VP 1−M , T2 and T6 are switched on and off. Symmetrical
operation makes T1, T4, T5, and T8 have the same switching
frequency, and T2, T3, T6, and T7 have the same switching
frequency, but the two frequencies are unequal. Therefore, it
is reasonable to consider the switching frequencies of T1 and
T2 as fS1 and fS2 . Since e∗ is given by (3), the period, during
which T1 is switched on and off, is specified as
TVP 1−M ≤ t ≤
T
− TVP 1−M .
2
eIu−v
[V]
=
fS2
=
T /2 − 2TVP 1−M
fC ,
T
fC
− fS1 .
2
vN 1−M
vN 2−M
0
-40
200
0
-200
400
0
-400
20
iLP
[A]
0
-20
20
iLN
[A]
0
-20
10 ms
(11)
Fig. 10.
Thus, the switching frequencies, fS1 and fS2 are given by
fS1
vP 2−M
(12)
(13)
√
When 2E = VP 2−M , and fC = 3 kHz, fS1 gets a
maximal value of 1 kHz, while fS2 gets a minimal value of
Experimental waveforms at 5.5 kW and 60 Hz.
500 Hz. Moreover, when e∗ ≤ VP 1−M , fS1 gets zero, and fS2
gets 1.5 kHz. The rectifier voltage reference is nearly equal
to the source line-to-neutral voltage vS , fRS1 1 kHz, and
fRS2 500 Hz. On the other hand, since the amplitude of the
inverter voltage reference is proportional to the output inverter
frequency, fIS1 = 0 ∼ 1 kHz, and fIS2 = 0.5 ∼ 1.5 kHz.
1460
200
200
vSu
vSu
0
[V]
-200
30
-200
30
iSu
eRu−M
[V]
eRu−v
[V]
iSu
0
[A]
[A]
eIu−M
[V]
eIu−v
[V]
-30
200
eRu−M
0
[V]
-200
400
eRu−v
0
[A]
[A]
0
0
-400
360
vP 2−N 2
0
[V]
340
320
200
-40
200
[V]
0
-200
400
iOu
0
[A]
eIu−M
0
[V]
eIu−v
0
[V]
vN 1−M
vN 2−M
0
-40
200
0
-200
400
0
-400
20
-20
2 ms
Fig. 11.
vP 2−M
vP 1−M
0
-200
40
-20
20
iLN
-30
200
-200
400
[V]
-400
20
iLP
0
[A]
-400
40
iOu
0
[V]
iLP
Time-expanded waveforms in Fig. 10.
[A]
0
-20
20
VII. E XPERIMENTAL R ESULTS
iLN
A. Constant-Torque Load Operation
The inverter frequency was controlled in a range 5 to 60
Hz. The resistive load was adjusted to have the motor produce
the rated torque. That is, the output power is proportional to
rotating speed.
Figs. 10 and 11 show observed waveforms when the motor
was operated at 5.5 kW and 60 Hz. Table II summarizes the
measured current THD (Total Harmonic Distortion) values and
harmonic currents of iSu and iOu , where each value is a ratio
with respect to the fundamental current. Note that harmonic
currents being less than 0.1% were excluded from Table II.
Both waveforms of iSu and iOu have THD values lower than
5.0%. Moreover, the waveform of iSu meets the Japanese
harmonic guideline that the line-current THD value is less
than 5% and each harmonic current is less than 3%.
It is clear from Fig. 10 that the rectifier and inverter
voltages with respect to point M, eRu−M and eIu−M are fivelevel waveforms, and that the rectifier and inverter line-to-line
voltage eRu−v and eIu−v are nine-level waveforms. These are
peculair to the five-level converter.
[A]
0
-20
10 ms
Fig. 12.
Experimental waveforms at 3.2 kW and 35 Hz.
The dc voltage ripple of vP 2−N 2 stayed within ±0.7% while
the dc mean voltage of vP 2−N 2 was 340V. The four split dc
capacitor voltages of vP 2−P 1 , vP 1−M , vM −N 1 , and vN 1−N 2
are well balanced as shown in Fig. 10. The voltage ripples
of vP 2−M and vP 1−M stayed within ±2.3.% and ±1.7%,
respectively. The rectifier switching frequencies of TR1 and
TR2, fRS1 and fRS2 were 950 Hz and 550 Hz, respectively.
The inverter switching frequency of TI1, fIS1 was 960 Hz,
while that of TI2, fIS2 was 540 Hz. The dc mean currents
flowing into the chopper inductors, īLP and īLN were 1.39
A, and −1.55 A, respectively. Fig. 11 shows time-expanded
waveforms of Fig. 10. The 3-kHz switching ripples were
superimposed on the dc current iLP and iLN .
Fig. 12 shows observed voltage and current waveforms
at 3.2 kW and 35 Hz. The possitive and negative dc-mean
1461
DC mean chopper current [A]
0
[V]
-200
30
iSu
0
[A]
eRu−M
[V]
eRu−v
-30
200
0
-200
400
0
[V]
DC mean chopper current [A]
vP 2−N 2
[V] 340
320
200
vP 2−M
vP 1−M
0
vN 1−M
vN 2−M
-200
40
iOu
[A]
eIu−M
[V]
eIu−v
[V]
0
-40
200
0
-200
400
[A]
[A]
10
3.0
|īLP |
|īLN |
5
Theory
Output power
0
0.3
0.4
0.5 0.6 0.7 0.8 0.9
Inverter modulation index
0
1.0
15
|īLP |
|īLN |
Theory
Output power
10
6.0
5.5 kW
P
3.0
īL
5
0
0.3
0.4
0.5 0.6 0.7 0.8 0.9
Inverter modulation index
0
1.0
0
Fig. 14 shows theoretical and experimental dc mean currents
of iLP and iLN at each inverter modulation index, where
the theoretical values were obtained from (5) to (9). The
theoretical and experimental results agreed each other with
acceptable errors. The maximal currents were about 80% of
the rated current of 16 A.
0
-20
20
iLN
P
Fig. 15. DC mean chopper chopper current and inverter modulation index
in a fan/blower-like load.
-400
20
iLP
6.0
5.5 kW
īL
Fig. 14. DC mean chopper current and inverter modulation index in the
rated constant-torque load.
-400
420
[V]
15
Output power [kW]
vSu
Output power [kW]
Overvoltage detected
200
0
-20
0
B. Fan/Blower-like Load Operation
20
105
20 ms
Fig. 13. Experimental waveforms before and after disabling the voltagebalancing circuit at 3.2 kW and 35 Hz.
chopper currents got maximal values of īLP = −13.5 A, and
īLN = 12.7 A, while the four split dc capacitor voltages were
well balanced. Because the inverter output voltage was reduced
by volt-per-herz control, the number of voltage levels of eIu−v
was decreased to five.
Fig. 13 shows observed voltage and current waveforms before and after the voltage-balancing circuit were intentionally
disabled at t = 20 ms during the motor was operated at 3.2
kW and 35 Hz. As soon as the voltage-balancing circuit was
disabled, the capacitor voltages vP 2−P 1 and vN 1−N 2 started
increasing, and then they reached a overvoltage protection
level. Finally, the system was shut down at t = 105 ms. These
experimental waveforms confirmed the effectiveness of the
voltage-balancing circuit for achieving stable operation.
Fig. 15 shows experimental results when the resistive load
was adjusted to act as a fan or a blower in which the output
power is proportional to a cubic of rotating speed. When an
inverter modulation index was 0.63, that is, the inverter output
frequency was 40 Hz, the dc mean inductors currents īLP
and īLN reached their maximal currents of -5.5 A and 5.1 A,
respectively. The maximal currents were one-third as low as
the rated current of 16 A.
VIII. C ONCLUSION
This paper has discussed the 6.6-kV transformerless backto-back system using two five-level diode clamped PWM
converters for motor drives. Attention has been paid to voltagebalancing control of the common four dc capacitors connected
in series. These voltages can be balanced by the voltagebalancing circuit consisting of two bi-directional buck-boost
choppers. Theoretical anlysis has been carried out on the dc
mean currents flowing in the chopper inductors. Experimental
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results obtained from a 200-V 5.5-kW laboratory model have
verified the effectiveness of the voltage-balancing circuit and
the validity of the theoretical analysis.
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