Convergence and Connectivity 2003
System in Package:
Flexibility in Integration
Chris Scanlan
Sr. Director, System in Package
Amkor Technology
cscan@amkor.com
Outline
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System in Package Definition
Benefits of SiP
Application examples and market drivers
SOC, SiP, or SOB
What is System in Package?
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An IC package containing multiple die?
A fully integrated system or sub-system:
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One or more semiconductor chips plus:
Passive components that would otherwise be
integrated on the mother board
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Other subsystem components:
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Surface mount discrete passives
Embedded or patterned into substrate
Integrated passive components
EMI shield, SAW filters, packaged ICs, connectors,
antennas, mechanical housings, etc.
A fully integrated functional block bridging the gap
between SOC and SOB (system on board)
SiP Benefits
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Simplifies product system board design and
assembly.
Increased functionality per unit area/volume.
Improved electrical performance.
Reduced system manufacturing costs.
Improved interconnect reliability.
Flexibility
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Can make changes to system or subsystem without
changing mask-sets or mother board designs.
Standardized sub-system “macros”
Silicon Area Efficiency
400
Silicon Area Efficiency =Si Area / Package Area
Silicon Efficiency(%)
300
Four-chip
Stacked CSP
2002
Area
Area Array
Array Packages
Packages
Triple-chip
Stacked CSP
2000
200
Stacked CSP
1998
100
Bare
Bare Chip
Chip
80
50
TSOP/QFP
1985
‘90
Stacked
TSOP/QFP
1995
Wafer-level
Wafer-level CSP
CSP
CSP
1996
Peripheral
Peripheral Packages
Packages
‘95
‘98
1st Year of Production
‘00
‘02
‘03
Stacked Penetrating the
Handset Market
Stacked CSP is being rapidly adopted in cell phones.
Move from 2G to 3G Is driving need for more memory and
processing power.
q 3D package integration is required to fit more functionality
in less space.
q
700
Million units
600
500
Memory
card slot
400
MEMS
300
200
100
0
'00
'01
S-CSP
'02
'03
Phones
'04
Source: Prismark
More ASIC
& memory
3D Technology – Reasons Why...
q Reduce
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System Level Costs
Single Package Assembly, Test and Handling
q Wafer
Level Cost Optimization for Dissimilar Technologies
Improved Design Time-TTM(fewer steps)-Yield-Capacity
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Low and high density die combinations
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No Need for Finest Design Geometry for Low Density Silicon Architectures (eg:
SRAM)
Low and high voltage die combinations
Mixed signal combinations (Memory/Logic)
Flexibility of combining custom devices with off-the-shelf devices
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Quicker and Easier Market Penetration
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Quickly add memory or other functionality to react to
changes in market demand
Greater access to niche markets through flexible
integration
3D Technology – More Reasons Why...
qSystem
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2 or More Die in 1 Package
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Level Size Reduction
Flash/SRAM, Logic/Memory, etc.
Double/Triple… functionality within same footprint
Stacked memory die
Reduced motherboard size (smaller cards)
Fewer components
Reduced Signal routing density, etc.
Small (x-, y-axis), Thin (z-), Light Weight
qConventional
Surface Mount
Cellular baseband module
w/ 6 die including 2 stacked die
Technology
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BGA & LGA Footprints and Compatibility with Thin Profile
Mobile Phone Product Requirements
Aligned with advanced BGA technology roadmaps
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Pb Free/Green
Cu Wirebonding
Flip Chip
Core Technology For 3D Packages
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Thin Spacer Technology
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Die overhang wirebonding
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Low loop wirebonding
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Wafer thinning/handling
less than 75um
Thin core laminates and thin die attach layers
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Package Stacking
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Higher final test yield
because each package
in stack is tested before
final assembly.
Easier to integrate die
from multiple suppliers.
FA is simplified.
Ideal for logic plus
memory integration.
CABGA, S-CSP family
low cost
PS-etCSP(3D)
flexible substrate design
good thermal performance
substrate technology under development
SiP Application Example:
802.11(b) Module
Balun
RFPA
Diversity
Switch
RF Filter
T/R
Switch
Transceiver
Baseband
To MAC
Balun
LNA
Clock
May be Integrated
on Transceiver Die
PLL
Synthesizer
Memory
Power
Managemet
Loop Filter
Transceiver section
Transmit section
Baseband section
Courtesy of Agere Systems
802.11b IFE Module
Courtesy of Agere Systems
Courtesy of Agere Systems
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Integrates 5 die and over 100 passives in a compact 25 mm x
25 mm BGA package
Includes compartmentalized metal EMI shield
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Separation of Tx/Rx sections and baseband
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No EMI shield required on the system board.
Fully integrated 802.11 IFE module
Transfer Molded Integrated
Shielding
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Compatible with high volume
assembly processes
Eliminates requirement for
shield at product level board
assembly.
Benefits are realized when the
module is of high functionality
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Meets required isolation
levels for cell phone
applications
Requires 1/2 the area of
traditional shields (.4-.5mm
per side)
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2 Turn Inductor #1 with Large Opening Shield Tabs
-10
2
-30
I.L. (dB)
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2.5
3
3.5
4
4.5
5
5.5
6
6.5
baseline no runners
baseline with runners
-50
-70
one shield
two shields
-90
noise floor
-110
-130
Freq (Mhz)
7
7.5
8
SiP Application Example:
DC/DC Converters
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Power One 15A DC/DC point of load converter
Integrates full circuit
including driver IC,
Controller and 2
MOSFETS plus
passives in a single
10mm x 12mm LGA
package!
Source: Power One data sheet
DC/DC Converter SiP
Current Solution
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SiP Solution
Benefits of SiP solution:
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Reduces board area required for POL converter.
Reduces external component count by 90%
LGA format reduces assembly cost, improves reliability
Lower total system cost.
Can be mounted closer to point of load
Application Example:
Logic – Memory integration
ASIC
Memory
(tested, burned-in)
1.0 - 1.5 mm
BGA Pitch
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Passive
High Density Build-up Substrate
Integrates ASIC and memory devices in a single module.
Memory is fully tested and burned-in in a standard CSP package.
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Cu Heat Spreader
Lower risk and higher final test yield. Off-the-shelf memory
Reduces board space by over 50%.
Improved electrical performance – memory much closer to ASIC.
Enables higher bus speeds
SiP Application Example:
Camera Modules
160
Source: Cahners InStat
Total
140
120
Cell phone, PDA, Handheld
PC, Security cameras
Digital still cameras
Million Units
100
Auto, Toys, other
80
60
40
20
0
2000
2001
2002
2003
2004
2005
Cell phones will become primary market for CMOS image sensors after 2003
Digital cameras will adopt CMOS sensors over the next few years
Camera in a Package
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CMOS Camera SiPs are
IC packages plus:
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IR glass
Lens mount and barrel
assembly
Passives and control IC
Flexible connector
Fully integrated camera
plus controller can be
easily integrated in
portable products.
Ceramic
Mount/lens
holder
Lens
Barrel
Exploded view of
Source:
Electronic
Trend Publications
ceramic
camera
module
SiP Application Example:
Memory Cards
Memory Stick
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MMC
RS-MMC
xD Picture Card
1GB memory card will hold:
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content of 16 music CDs (64MB per CD)
385 JPEG images in 5-megapixel quality
24 minutes of DVD-quality video (MPEG2)
six hours of MPEG4 (384 Kbps) moving
images
SonyDUO
Secure Digital (SD)
mini-SD
Flash Memory Card Hosts
2006 flash card
market by application
Digital Cameras
30%
Compressed Audio
10%
Other
4%
PDA & PC
6%
Industrial and
Telecom
50%
•Projected total flash card market
in 2006 = 311 million units
•About 55% to be SD card format
Source: IDC
Oct 2002
Memory Card Categories
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Game Cards
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Multimedia Cards
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ROM-based
1 - 2 die solutions
no SMT
typically LF-based
controller + Flash memory
2 - 7 die solutions
100% SMT ; COB + SMT ; 100% COB
typically Laminate based
I/O Cards
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controller + Flash memory + I/O functionality (e.g. GPS,
WiFi, camera, etc.)
3+ die solutions
COB + SMT
LF/Laminate hybrid
SOC, SiP and SOB
WiFi example
Circuit Design
By Customer
SOC
MAC
System on Board
Diversity and
T/R switches
SiP
RFPA
PM
Memory
Switches
DSP
MAC??
RF Filter
Transceiver
RFPA
+
Baluns
Transceiver
Memory
DSP
Crystal Oscillator
Power Management
EMI shield
Antenna
Baluns
+
Crystal Oscillator
MAC
EMI shield
Antenna
Antenna
SiP vs. SoC
System LSI example
Functionality (High)
Development Cost
(Low)
Device Cost
(Low)
SiP
üFlexibility
üShort development cycle
üCan integrate more memory
üLow Noise
üCost reduction for system
SoC
Flexibility
(high)
Development
Period (Short)
Installed memory capacity
üHigh Performance
üArea Shrink
üLower Device Cost
Adapted From: Renesas System-in-Package Catalog
Summary
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The power of SiP is the ability to bring together
many IC and packaging technologies to create
highly integrated products with optimized cost,
size and performance.
SiP and SOC are not mutually exclusive!
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Most SiP products contain at least one SOC device
In general, functions that can be economically
integrated on chip should be integrated using SOC.