Intel’s Revolutionary
22 nm Transistor Technology
Mark Bohr
Kaizad Mistry
Intel Senior Fellow
22 nm Program Manager
May, 2011
1
Key Messages
• Intel is introducing revolutionary Tri-Gate transistors on its
22 nm logic technology
• Tri-Gate transistors provide an unprecedented combination
of improved performance and energy efficiency
• 22 nm processors using Tri-Gate transistors, code-named
Ivy Bridge, are now demonstrated working in systems
• Intel is on track for 22 nm production in 2H „11, maintaining a
2-year cadence for introducing new technology generations
• This technological breakthrough is the result of Intel‟s highly
coordinated research-development-manufacturing pipeline
• Tri-Gate transistors are an important innovation needed to
continue Moore‟s Law
2
Intel Technology Roadmap
Process Name
P1266
P1268
P1270
P1272
P1274
Lithography
45 nm
32 nm
22 nm
14 nm
10 nm
1st Production
2007
2009
2011
2013
2015
Intel continues our cadence of introducing a
new technology generation every two years
3
Traditional Planar Transistor
Gate
Drain
High-k
Dielectric
Source
Oxide
Silicon
Substrate
Traditional 2-D planar transistors form a conducting channel in the
silicon region under the gate electrode when in the “on” state
4
22 nm Tri-Gate Transistor
Drain
Gate
Source
Oxide
Silicon
Substrate
3-D Tri-Gate transistors form conducting channels on three sides
of a vertical fin structure, providing “fully depleted” operation
Transistors have now entered the third dimension!
5
22 nm Tri-Gate Transistor
Gate
Oxide
Silicon
Substrate
Tri-Gate transistors can have multiple fins connected together
to increase total drive strength for higher performance
6
22 nm Tri-Gate Transistor
Gate
Oxide
Silicon
Substrate
Tri-Gate transistors can have multiple fins connected together
to increase total drive strength for higher performance
7
22 nm Tri-Gate Transistor
Gates
Fins
8
32 nm Planar Transistors
22 nm Tri-Gate Transistors
9
Intel Transistor Leadership
2003
90 nm
SiGe
2005
65 nm
2007
45 nm
2009
32 nm
2011
22 nm
Invented
Gate-Last
High-k
Metal Gate
2nd Gen.
Gate-Last
High-k
Metal Gate
First to
Implement
Tri-Gate
SiGe
Invented
2nd Gen.
SiGe
SiGe
Strained Silicon Strained Silicon
Strained Silicon
High-k Metal Gate
Tri-Gate
10
Std vs. Fully Depleted Transistors
Bulk Transistor
Gate
Gate
Oxide
Inversion
Layer
Source
Drain
Depletion
Region
Silicon Substrate
Silicon substrate voltage exerts some electrical influence on
the inversion layer (where source-drain current flows)
The influence of substrate voltage degrades electrical
sub-threshold slope (transistor turn-off characteristics)
NOT fully depleted
11
Std vs. Fully Depleted Transistors
Partially Depleted SOI (PDSOI)
Gate
Floating
Body
Source
Drain
Oxide
Silicon Substrate
Floating body voltage exerts some electrical influence
on the inversion layer, degrading sub-threshold slope
NOT fully depleted
Not used by Intel
12
Std vs. Fully Depleted Transistors
Fully Depleted SOI (FDSOI)
Gate
Source
Drain
Extremely thin
silicon layer
Oxide
Silicon Substrate
Floating body eliminated and sub-threshold slope improved
Requires expensive extremely-thin SOI wafer,
which adds ~10% to total process cost
Not used by Intel
13
Std vs. Fully Depleted Transistors
Fully Depleted Tri-Gate Transistor
Gate
Oxide
Silicon
Fin
Silicon Substrate
Gate electrode controls silicon fin from three sides
providing improved sub-threshold slope
Inversion layer area increased for higher drive current
Process cost adder is only 2-3%
14
Transistor Operation
“On”
Current
Planar
Channel
Current
(normalized)
Threshold
Voltage
“Off”
Current
Gate Voltage (V)
Operating
Voltage
Transistor current-voltage characteristics
15
Transistor Operation
Planar
Channel
Current
Tri-Gate
(normalized)
Reduced
Leakage
Gate Voltage (V)
The “fully depleted” characteristics of Tri-Gate transistors provide a
steeper sub-threshold slope that reduces leakage current
16
Transistor Operation
Tri-Gate
Channel
Current
Reduced Threshold
Voltage
Tri-Gate
(normalized)
Gate Voltage (V)
Reduced Operating
Voltage
The steeper sub-threshold slope can also be used to target a
lower threshold voltage, allowing the transistors to operate at
lower voltage to reduce power and/or improve switching speed
17
Transistor Gate Delay
Transistor
Gate Delay
Slower
32 nm
Planar
(normalized)
Lower Voltage
Operating Voltage (V)
Transistor gate delay (switching speed) slows down
as operating voltage is reduced
18
Transistor Gate Delay
32 nm
Planar
Transistor
Gate Delay
(normalized)
22 nm
Planar
Operating Voltage (V)
22 nm planar transistors could provide some performance improvement,
but would still have poor gate delay at low voltage
19
Transistor Gate Delay
37%
32 nm
Planar
Faster
Transistor
Gate Delay
(normalized)
22 nm
Tri-Gate
18%
Faster
Operating Voltage (V)
22 nm Tri-Gate transistors provide improved performance at high voltage
and an unprecedented performance gain at low voltage
20
Transistor Gate Delay
32 nm
Planar
Transistor
Gate Delay
(normalized)
-0.2 V
22 nm
Tri-Gate
Operating Voltage (V)
22 nm Tri-Gate transistors can operate at lower voltage
with good performance, reducing active power by >50%
21
Tri-Gate Transistor Benefits
• Dramatic performance gain at low operating
voltage, better than Bulk, PDSOI or FDSOI
37% performance increase at low voltage
>50% power reduction at constant performance
• Improved switching characteristics
(On current vs. Off current)
• Higher drive current for a given transistor
footprint
• Only 2-3% cost adder (vs. ~10% for FDSOI)
Tri-Gate transistors are an important innovation needed to continue Moore‟s Law
22
22 nm Tri-Gate Circuits
• 364 Mbit array size
• >2.9 billion transistors
• 3rd generation high-k + metal gate
transistors
• Same transistor and interconnect
features as on 22 nm CPUs
22 nm SRAM, Sept. „09
22 nm SRAMs using Tri-Gate transistors were first demonstrated in Sept. „09
Intel is now demonstrating the world‟s first 22 nm microprocessor (Ivy Bridge)
and it uses revolutionary Tri-Gate transistors
23
22 nm Manufacturing Fabs
D1C Oregon
Fab 28 Israel
D1D Oregon
Fab 32 Arizona
Fab 12 Arizona
24
On-Time 2 Year Cycles
90 nm
2003
65 nm
2005
45 nm
2007
32 nm
2009
22 nm
2011
Intel continues to successfully introduce leading edge
process + products on a 2 year cadence
25
Intel’s R-D-M Pipeline
Research
Development
Manufacturing
Pathfinding
Copy Exactly!
Bringing innovative technologies to high volume manufacturing is the result of a
highly coordinated internal research-development-manufacturing pipeline
26
Key Messages
• Intel is introducing revolutionary Tri-Gate transistors on its
22 nm logic technology
• Tri-Gate transistors provide an unprecedented combination
of improved performance and energy efficiency
• 22 nm processors using Tri-Gate transistors, code-named
Ivy Bridge, are now demonstrated working in systems
• Intel is on track for 22 nm production in 2H „11, maintaining a
2-year cadence for introducing new technology generations
• This technological breakthrough is the result of Intel‟s highly
coordinated research-development-manufacturing pipeline
• Tri-Gate transistors are an important innovation needed to
continue Moore‟s Law
27