(a) High Speed (HP/SP) and
Low Power Logic (LP/ULP)
(b) High Voltage (TG)
22nm SoC tri-gate transistor families, including high-speed logic, low power and high voltage.
Figure 1
Logic
-High Speed
(HP/SP)
- Low Power
(LP/ULP)
High Voltage
Fin cut TEM, gate cut TEM, and tilted SEM of logic thin gate (top) and high-voltage thick-gate (bottom)
transistors
Figure 2
Transistor
Type
High Speed Logic
Options
High
Standard
Performance Perf./ Power
(HP)
(SP)
Vdd
(Volt)
Gate Pitch
(nm)
Low Power Logic
High Voltage
Low
Power
(LP)
Ultra Low
Power
(ULP)
1.8 V
3.3 V
0.75 / 1
0.75 / 1
0.75 / 1
0.75/1.2
1.5/1.8/3.3
3.3 / >5
90
90
90
108
min. 180
min. 450
Lgate (nm)
30
34
34
40
min. 80
min. 280
N/PMOS
Idsat/Ioff
(mA/um)
1.08/ 0.91
@ 0.75 V,
100 nA/um
0.71 / 0.59
@ 0.75 V,
1 nA/um
0.41 / 0.37
@ 0.75 V
30 pA/um
0.35 / 0.33
@ 0.75 V
15 pA/um
0.92 / 0.8
@ 1.8 V
10 pA/um
1.0 / 0.85
@ 3.3 V
10 pA/um
22nm modular transistor options and device characteristics
Intel’s Complete 22-nm Tri-Gate Technology For SoC Applications: Historically, gains in transistor
Table
1 become more difficult and so innovations in
performance have come from making them smaller.
That has
transistor architecture are receiving more emphasis. Multiple-gate transistors are one such innovation. They
provide superior on/off control, enabling high drive currents to be achieved at a lower supply voltage than
otherwise. At the IEDM, Intel will discuss its use of the multiple-gate approach to build a complete and
versatile 22-nm 3D tri-gate transistor technology platform for system-on-chip (SoC) applications. It provides
leading-edge transistors (families of high-speed, low-standby-power and high-voltage-tolerant devices),
state-of-the-art interconnects and RF/mixed-signal features for a very wide range of SoC applications.
The high-speed logic transistors have subthreshold leakages ranging from 100 nA/µm to 1 nA/µm, while the
low-power versions feature leakage of < 50 pA/µm yet have drive currents 50% higher than 32-nm planar
(traditional technology) devices. The process also yields high-voltage transistors (1.8 V or 3.3 V) for analog
circuits, I/O, legacy designs and other applications. They feature the highest reported I/O device drive
currents for an SoC technology (NMOS/PMOS=0.92/0.8 mA/µm at 1.8 V). The trigate technology platform
also features eight to 11 layers of low-k and ultra-low-k carbon-doped oxide (CDO) interconnect at tight
pitches for different applications; many analog/mixed-signal features; and three different SRAM bit cells,
spanning high-density/low-leakage (0.092 µm2), low voltage (0.108 µm2) and high-performance (0.130
µm2). (Paper #3.1, “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for UltraLow-Power, High-Performance and High-Density SoC Applications,” C.-H. Jan et al, Intel)