PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
Design and Implementation of a 125kW T-NPC PV Inverter
Yuelin, Wu, National Active Distribution Network Technology Research Center (Beijing
Jiaotong University), Beijing, China, 13121480@bjtu.edu.cn
Guohong, Zeng, National Active Distribution Network Technology Research Center (Beijing
Jiaotong University), Beijing, China, ghzeng@bjtu.edu.cn
Jingdou, Liu, National Active Distribution Network Technology Research Center (Beijing
Jiaotong University), Beijing, China, jdliu@bjtu.edu.cn
Gaosheng, Song, MITSUBISHI ELECTRIC&ELECTRONICS (SHANGHAI) CO., LTD.,
Shanghai, China, SongGS@mesh.china.meap.com
Jian, Sun, MITSUBISHI ELECTRIC&ELECTRONICS (SHANGHAI) CO., LTD., Shanghai,
China, SunJian@mesh.china.meap.com
Abstract
This paper presents a design method and its implementation of PV inverter, in which the Ttype NPC three-level (T-NPC) topology is adopted, to achieve the benefits of low voltage
stress, low switching losses, low harmonic distortion and high conversion efficiency. The
design procedure is presented in detail, including power losses calculation, efficiency
analysis, power stack designing, filter designing. The effectiveness of the proposed PV
inverter and its design method is validated by experimental results.
1.
Introduction
Driven by the increasing environmental concerns, photovoltaic (PV) power generation
systems are attracting the market and research interest. PV grid-connected inverters, acting
as the interface between the grid and PV power system, have been studied widely. Although
two-level inverter is commonly adopted, three-level topology is found to be more suitable for
distributed PV generation systems. As one of the most typical three-level inverter, neutralpoint-clamped (NPC) inverter, has been researched in many literatures[1-2], with the
advantage of low device voltage stress , superior output voltage quality, low switching losses
and low du/dt. To simplified the control algorithm and reduce the number of devices, topology
of T-type three-level neutral-point-clamped converter (T-NPC) is derived[3], as shown in Fig.1.
P
+Udc/2
L1
L2
Ua
C1
T1
D1
T2
T3
D2
D3
T4
D4
Ub
O
Grid
O
Uc
C2
-Udc/2
N
Fig. 1.
Cf
Topology of T-NPC PV inverter
Fig. 2.
Single-phase of T-NPC topology
Compare to that in NPC, each bridge leg in T-NPC reduces two diodes as shown in Fig.2, so
lower conduction losses can be achieved and the operation algorithm can be simplified, while
the other advantages of NPC are kept. Considering the lower DC link voltage available in
distributed PV generation systems, T-NPC grid-connected PV inverter is more exceptive in
efficiency and cost comparing to NPC inverters.
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
This paper attempts to give the power losses calculation method and design procedure of TNPC PV inverter with high efficiency for power and space. To verify the effectiveness and
reliability of T-NPC inverter, temperature rise experiment has been performed.
2.
Efficiency analysis
This section explains the operation principle of T-NPC and gives the calculation method of
power losses to design dissipation system. Based on the method, a calculation example is
given to show the high efficiency of T-NPC.
2.1.
Operation principle of T-NPC
The single-phase of T-NPC PV inverter is shown in Fig.2, in which T1~T4 are IGBT switches,
D1~D4 are FWDs, C1 and C2 are DC link capacitors. Assume that the direction of current
flowing out from bridge leg is positive. Generally, the output terminal of the bridge leg can be
connected to positive (P), neutral (O), or negative (N) side of DC link, and the output
voltage can be set to three values, as shown in Table 1.
Operation mode
T1
T2
T3
T4
Output voltage
P
ON
ON
OFF
OFF
+Udc/2
O
OFF
ON
ON
OFF
0
N
OFF
OFF
ON
ON
-Udc/2
Table. 1. Switching operation modes of IGBT
The driving signals of T1 and T2 are complemented to T3 and T4 respectively, T1 and T4
cannot be turned on simultaneously.
To illustrate the working process and control principle of T-NPC, the switch commutation
procedure is analyzed in detail. Six current commutation diagrams are deduced, as shown in
Fig.3, and can be described as follow.
P
C1
T2
T1
T3
D1
D2
D3
T4
D4
C1
D1
D2
C2
P
D3
T4
C2
D4
T1
T2
(2)Mode O, Uo=0,IL＞0
D1
T1
T2
O
D3
T4
D4
N
C2
D4
C1
D1
T3
T1
D1
T2
T3
D2
D3
T4
D4
O
D2
D3
T4
C2
D4
N
(4)Mode P, Uo=Udc/2,IL＜0
D3
T4
(3)Mode N, Uo=-Udc/2,IL＞0
O
D2
D2
P
C1
T3
D1
T3
N
P
C1
T1
T2
O
N
(1)Mode P, Uo=Udc/2,IL＞0
Fig. 3.
T1
T3
O
N
C2
C1
T2
O
C2
P
P
(5)Mode O, Uo=0,IL＜0
N
(6)Mode N, Uo=-Udc/2,IL＜0
Current commutations of T-NPC topology
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
(1) The direction of output current is positive, T1 and T2 are turned on, T3 and T4 are turned
off, current commutates over T1 and the output voltage Uo=Ud/2.
(2) The direction of output current is positive, T2 and T3 are turned on, T1 and T4 are turned
off, current commutates over T2 and D3 and the output voltage Uo=0.
(3) The direction of output current is positive, T3 and T4 are turned on, T1 and T2 are turned
off, current commutates over D4 and the output voltage Uo=-Ud/2.
(4) The direction of output current is negative, T1 and T2 are turned on, T3 and T4 are turned
off, current commutates over D1 and the output voltage Uo=Ud/2.
(5) The direction of output current is negative, T2 and T3 are turned on, T1 and T4 are turned
off, current commutates over T3 and D2 and the output voltage Uo=0.
(6) The direction of output current is negative, T3 and T4 are turned on, T1 and T2 are turned
off, current commutates over T4 and the output voltage Uo=-Ud/2.
From the six operating mode, it can be deduced that the operation algorithm can be
simplified compared with NPC.
2.2.
Power losses Calculation
To design the inverter efficiently and to handle the power dissipation effectively, power
losses of each device should be estimated precisely. The losses of each power device is
consisted of conduction losses PON, and switching losses Psw.
Conduction losses
Two factors need to be considered in calculating conduction losses. One is the conduction
time in a modulation period, and the other is the conduction current. During one modulation
period, assume only one transition of P-O-N or N-O-P is permitted.
Conduction voltage drop and instantaneous conduction power can be described as:
VT VT 0 iT rT
(1)
2
(2)
Pon VT 0iT iT rT
Where rT, VT0, VT and iT are conduction internal resistance, initial saturation voltage,
conduction voltage drop, conduction current, respectively.
The energy losses of power devices in one carrier cycle can be calculated with:
EON
T
VT iL DTc
[VT 0 +I m sin( t )rT ]I m sin( t ) DTc
(3)
Where Tc is period of carrier wave, D is duty ratio, a function of modulation ratio M and power
factor angle θ. Imsinωt is load current and Im is the peak current.
Then the average conduction losses in one modulation period can be calculated with:
PON
T
1
T0
EON T d t
1
2
2
[VT 0 +I m sin( t )rT ]I m sin( t ) Dd t
1
(4)
Where T0 =2π, [θ1~θ2] is the conduction time interval.
Switching losses
The switching losses of power devices are proportional to current and DC voltage. Turn-on
energy losses Eon.nor, turn-off energy losses Eoff.nor of IGBT and reverse recovery energy Err.nor
of FWD in normal working condition are shown in the datasheet, they should be converted in
actual working condition according to Udc and Ion, Ioff, Irr, which mean DC link voltage, turn-on
current, turn-off current of IGBT, reverse recovery current of FWD. The switching frequency
is fs, the switching power losses in one modulation period can be calculated with:
Psw
on
1 1
Tc T0
2
1
Eon.nor
I on U dc
dt
I nor U dcnor
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
Psw
Psw
off
rr
1 1
Tc T0
1 1
Tc T0
2
Eoff .nor
1
2
Err .nor
1
I off U dc
dt
I nor U dcnor
(6)
I rr U dc
dt
I nor U dcnor
(7)
Where Psw-on, Psw-off and Psw-rr are IGBT turn-on losses, IGBT turn-off losses, FWD reverse
recovery losses, respectively. Inor and Udcnor are output current and DC voltage in normal
working condition.
2.3.
Efficiency Calculation Example
In this paper, MITSUBISHI 4in1 module CM400ST-24S1 is adopted in T-NPC PV inverter to
design with high efficiency for power and space, 1200V chip for half bridge (T1/D1 and
T4/D4), 650V chip for AC SW (T2/D2 and T3/D3). Test condition is shown as Table 2.
Modulation
DC voltage
Switching frequency
Heat sink temperature
SPWM
850V
8kHz
95℃
Power factor
Gate resistance
Modulation ratio
Fundamental frequency
0.9
1.5Ω
0.605
50Hz
Table. 2. Test condition for efficiency calculation
The power losses calculation results of T-NPC according to equation (1) ~ (7) are shown in
Table 3.
Device
T1/T4
T2/T3
D2/D3
D1/D4
Io(A)-rms
255A
PON-T(W)
82.3
86.5
96.5
0.6
Psw-T(W)
91.8
5.8
11.4
1
P_sum(W)
174.1
92.3
107.9
1.6
P_total(W)
Efficiency
751.8
98.38%
Table. 3. Calculation results of T-NPC
Based on the calculation results of power losses above, suitable fan and heat sink can be
chosen as dissipation system.
3.
Design of T-NPC inverter
Power stack is one of the important devices in a PV inverter which have great impact on
stability and reliability. This section designs a modular power stack consisting of power
device, DC link capacitor and current sensor etc. As another important element in a PV
inverter, LCL filter designing procedure is also presented in this section.
3.1.
Design of T-NPC power stack
Fig.4 shows the schematic diagram of T-NPC power stack, filtering the DC voltage through
DC link capacitor, feeding the DC power to IGBT modules, converting the DC power into AC
power which can regulate the voltage amplitude and frequency by control the switching
devices in T-NPC inverter. It has the functions of over-voltage protection, over-current
protection, over-heat protection, short circuit protection and fault locking.
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
DC+
0
C1
Heat
sink
P
DCC2
N
O
P
O
N
P
O
AC
AC
N
AC
CT1
CT2
AC.out.U
AC.out.V
CT3
AC.out.W
Drive board-A
Drive board-B
Drive board-C
Drive signal A
Drive signal B
Drive signal C
Fig. 4. Schematic diagram of T-NPC power stack
To reduce system volume and stray parameters, it integrate the power devices, cooling
system and sensors into a high power density stack as shown in Fig.5 and Table 4.
6
5
4
3
2
1
Fig. 5.
3.2.
The figure of power stack
Number
Device
1
Fan
2
DC link laminated busbar
3
DC link capacitor
4
Power device CM400ST-S21
5
Current sensor
6
Drive board
Table. 4. Devices in the power stack
Design of LCL filter
LCL filter is preferred to L filter because its switching harmonic attenuation with smaller
reactive element is more effective. Thus the cost and the weight of the inverters are reduced.
So LCL filter is adopted in this paper. The design of the filter is mainly based on the harmonic
voltage. Harmonic current is generated by harmonic voltage and inverter-side inductor, the
output current is the one which passes through from filter capacitor and grid-side inductor.
The choice of filter elements is a tradeoff considering switching harmonics attenuation,
reactive power consumption, relative short-circuit voltage drop, grid decoupling, filter losses,
and the costs and sizes of filter elements. The equivalent circuit of inverter with LCL-filter is
shown in Fig.6.
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
ig
Lg
e
Fig. 6.
L
C
u
Equivalent circuit of inverter with LCL-filter
Where e, u, Lg, L, C are grid voltage, inverter output voltage, grid-side inductor, inverter-side
inductor, filter capacitor, respectively. Filter capacitor C needs to be satisfied with:
C
P
3 2 f1 Em 2
(8)
Where P, Em, f1, λ are rated power of inverter, RMS phase voltage of grid, fundamental
frequency of grid, the ratio of the fundamental reactive power absorbed by filter capacitor C
to rated power of inverter P, respectively.
The resonance frequency fres of inverter should satisfied with equation (9) as followed to
avoiding resonance peak emerges at too low frequency and too high frequency band.
(9)
10 f1 f res 0.5 f sw
The fsw is switching frequency. The range of resonance frequency can be further reduced as:
(10)
Based on engineering experience, 1450Hz can be chosen as resonance frequency.
According to equation (11) as follow:
1kHz
f res
f res
1
2
2kHz
Lg LC
Lg
(11)
L
Take cost and volume into consideration, LCL-filter parameters C=180uF, L=190uH,
Lg=100uH are chosen in this paper.
4.
Experimental method and results
The parameters of the T-NPC PV inverter are shown in Table 5.
Parameter
Value and unit
Rated capacity
139kVA（125kW, PF=0.9）
Rated output voltage
315Vrms
Rated output current
255Arms
Rang of output frequency
47.5~51.5Hz
Power factor
0.9ind~0.9cap
DC link voltage
480~850V
DC link capacitor
1300uF
Switching frequency
8~10kHz
Power module
1200V/600V/400A
Table.5. Parameters of T-NPC PV inverter
To verify the stability and reliability of T-NPC power stack, H-bridge circuit is composed of
two T-type bridges connected an inductor load (L=640uH) shown in Fig.7. Output voltages of
the two bridges are U1 and U2 (AC-O). Voltage difference ΔU can be adjusted by changing
the phase angle θ of U1 and U2, so rated output power can be achieved. Fig.8 shows phasor
diagram of H-bridge circuit, it can work in both inverter operation and rectifier operation.
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
P
P
T1
D2
D1 D5
D3
U1
O
T2
T5
T3
D7
D6
T7
T6
U2
L
+ ΔU -
O
U1
I
ΔU
θ
U2
ΔU
T4
D4 D8
θ
T8
N
N
Fig.7. H-bridge circuit for testing T-NPC
U2
I
U1
(a) Inverter operation
(b) Rectifier operation
Fig.8. Phasor diagram of H-bridge circuit
Fig.9 shows the waveforms in inverter operation (a) and rectifier operation (b).
(a)
(b)
Fig.9. Experimental waveforms of inverter operation and rectifier operation
Where CH1 is DC link ripple current (100A/div), CH2 is U1 (500V/div), CH3 is ΔU (500V/div),
CH4 is load current I (200A/div). After about 1 hour, the temperature of some main
components in the power stack have been measured, results are shown in Table 6.
Component
Initial
temperature(℃)
DC link capacitor
Final temperature(℃)
Temperature rise(℃)
Inverter
operation
Rectifier
operation
Inverter
operation
Rectifier
operation
18
37.5
41
19.5
23
DC laminated busbar
18
32
32
14
14
AC output busbar
18
64.5
57
46.5
39
Table. 6. Results of temperature rise experiment
The experimental results indicate that the T-NPC PV inverter can meet the working
requirements and reach the industry standard of Technical Specification of Grid-connected
PV inverter (NB/T 32004-2013).
5.
Conclusion
A T-NPC PV inverter has been presented in this paper. Calculation method of power losses
and design procedure of power stack and LCL filter are expressed. Because of the high
power density power stack, the PV inverter can achieve more efficiency, less space and less
stray parameters. Experimental results proved the effectiveness and reliability.
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PCIM Asia 2015, 24 – 26 June 2015, Shanghai, China
6.
References
[1] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, A Survey on Neutral-PointClamped Inverters, IEEE Transactions on Industrial Electronics, vol. 57, pp. 2219-2230, 2010.
[2] A. Yazdani and R. Iravani, A Neutral-Point Clamped Converter System for Direct-Drive
Variable-Speed Wind Power Unit, IEEE Transactions on Energy Conversion, vol. 21, pp. 596607, 2006.
[3] Schweizer, M., Lizama, I., Friedli, T., & Kolar, J. W. (2010, November). Comparison of the
chip area usage of 2-level and 3-level voltage source converter topologies. In IECON 201036th Annual Conference on IEEE Industrial Electronics Society (pp. 391-396). IEEE.
[4] Liu Fei, Zha Xiaoming, & Duan Shanxu. (2010). Design and Research on Parameter of
LCL Filter in Three-Phase Grid-Connected Inverter [J]. Transactions of China
Electrotechnical Society, 25(3), 110-116.
[5] DU Yi & LIAO Meiying. (2011), Losses calculation of IGBT module and heat dissipation
system design of inverters [J]. ELECTRIC DRIVE AUTOMATION, 33(1), 42-46.
[6] LI Youmin, TONG Yibin, WU Xuezhi &YAO Xiuyuan. (2013). 65kW TNPC Three-level
Grid-connected Inverter Design [J]. Power Electronics, 47(12), 66-68.
[7] CM400ST-24S1 datasheet, MITSUBISHI ELECTRIC.
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