WorldAcademics
World Academics Journal of Engineering Sciences
____________________________________________________________
World Acad. J. Eng. Sci 01 1009 (2014)
doi:10.15449/wjes.2014.1009
ISSN: 2348-635X
Topologies of Multilevel Inverter–“A Review”
Himanshu Joshi* and Rahul Agrawal
Dept. of Electrical Engg.Vindhya Institute of Technology & Science, Indore (M.P.), India
*Email: himanshujoshi@hotmail.com
Abstract:
With the advancements in semiconductor technology, multilevel inverter technology is widely
employed for megawatt power and medium voltage energy control applications. Construction of
multilevel inverter is similar to single and three phase inverters. These inverters do not use a
transformer for their operation, reduce harmonic losses and give less disturbance. This paper
explains the topologies of multilevel inverter such as diode clamped, capacitor clamped or flying
capacitor and cascade H-bridge.
Keywords: Multilevel Inverter, Modulation and Control Technique, Cascade multilevel inverter.
Introduction
In recent times the power demand of the
industries is increasing very rapidly because many
industries are using higher power apparatus and
drives, this apparatus worked on high power and
medium voltage, to supply energy to this apparatus or
drives multilevel inverter is used. A multilevel
inverter is a power electronic system which gives the
desired output voltage from several DC voltage
sources as input [1].
The first multilevel inverter is introduced in 1975
by Baker and Bannister named as cascade H bridge
inverter. Cascade inverter gives (2n+1) level output
by using D.C. sources, such as battery, PV cell or any
other form of D.C. source. In 1980 Baker introduced
another diode clamped inverter. This inverter uses a
series connected semiconductor device to split the dc
bus voltage in the set of voltage level. In 1992
Meynard and Foch introduced a new topology, which
is flying capacitor; this topology uses the floating
capacitor to clamp the voltage [2].
Multilevel inverter is also used in renewable
energy such as wind turbine and solar cell etc. to
interface the energy sources to high power
applications [3-4].
The advantage of multilevel inverter is that this
gives high power at low harmonics, low switching
losses, best power quality and high voltage
capability. The main disadvantage of multilevel
inverter is that it uses so many power semiconductor
switches.
In addition from topologies several modulation and
control technique have been developed for multilevel
inverter. Modulation technique is selective harmonic
elimination PWM (SHE-PWM), space vector PWM
(SVM), sinusoidal PWM (SPWM). In this
modulation technique selective harmonic elimination
PWM is used for low switching frequency and high
power application.
Cascade h-bridge multilevel
inverter
The cascade H bridge inverter is shown in Fig. 1.
In cascade multilevel inverter the number of HBridge inverter is connected in series and the output
is the sum of all H-Bridge inverter. Each H-Bridge
inverter uses separate DC source as input so it is very
useful for renewable sources because every
renewable source is working like a separate source.
Depending on the output voltage the number of Hbridge inverter is change. The output voltage of
Cascade H-Bridge inverter is:
Vout= VDC1 + VDC2 + VDC3+……..+ VDCn
(1)
To get 2n+1 level output voltage „n‟ number of
separate DC source required. The cascade multilevel
inverter uses less no. of switches as compare to
Diode clamp and flying capacitor inverter. To
minimized harmonic distortion switching angle is
chosen very carefully.
Each level of inverter generates the three different
output +Vdc, 0 and – Vdc. As the switches S1 and
S4 are ON then the output voltage is +Vdc, on the
other hand when S3 and S2 turns ON then the output
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World Acad. J. Eng. Sci. 01 1009 (2014)
voltage is – Vdc and when S1, S2or S3, S4are ON
the output voltage is 0 [4].
The advantage of this inverter that it uses less no.
of switches so it is cheap and consume less space.
The disadvantage of this inverter is that it uses many
separate DC power sources. It required no. of
batteries or renewable sources like PV cell etc. Fig. 1
show the cascade multilevel inverter and fig. 2 show
the wave form of inverter.
Mahesh Manivanna and Rama Redd [19]
proposed a topology
for cascade H-Bridge
multilevel inverter. This topology consist eight
switches, eight diodes and two DC sources, and gives
THD 5.79% and conventional 7-Level Cascade Hbridge inverter gives the THD value of 8.73%. Rokan
Ali et al. [20] give a topology with reduce no. of
switches for asymmetrical cascade multilevel
inverter. This gives large no. of output voltage
without increasing the no. of bridge in this topology
they use two bidirectional switches and a new
algorithm give to determine its output voltage.
Joshi and Agrawal
Ebrahimi et al. [23] proposed a simple and new
topology for cascade multilevel converter which use
less no. of power electronic component and produce
high no. of output level. This topology provides 125
levels in output voltage with peak voltage of 400 V,
and use 24 IGBTs, the blocking voltage is 604.5 V on
bidirectional switches, other topology produces 161
voltage levels and use 28 IGBTs and blocking
voltage is 1000 V. The proposed topology use lower
switches and components as compared with other and
it operates also very full in bridge converters at lower
voltage.
Figure 2-Waveform of Multilevel Inverter.
Figure 1-Cascade H Bridge Multilevel Inverter.
Mohsen Ebadpour, Mohammad Bagher Bannae
Sharifian and Seyed Hossein Hosseini [21] give a
new topology of Multilevel Inverter which use less
Number of Switches, this topology proposed for
Electric Vehicle Applications. By reducing the
number of switches the size and power consumption
of driving circuits of inverter is reduced. The
proposed inverter also reduces the THD in output
voltage. Himanshu Misra et al. [22] gives a new
topology with less no of switches for eleven level
inverter. In this topology they use nine and five
switches. The main drawback of this topology is that
the upper batteries use more as compared to other
batteries, therefore batteries discharge rapidly. Javad
M. Naga Raju, K. Vijay Kumar [24] proposed a
topology for electric vehicle applications. In
conventional cascade inverter output voltage level is
given as 2n+1, where n is no. of switches in inverter,
but in proposed topology the output level is 12n+1,
where n is the no. of voltage in series or parallel
circuit and 3n+9 switching device is required for
almost sinusoidal output voltage. M. Kavitha, A.
Arunkumar, N. Gokulnath and S. Arun [25]
introduced cascade H-Bridge inverter topology with
less no. of switches and sources, they implement this
topology on five level cascaded H-bridge multilevel
inverter with only five switches, two DC power
source and one diode. Using this topology THD of
five level inverter is 21.95%. The proposed work of
Single phase five level multilevel cascade inverter
reduces the THD and improves efficiency of the
system. Jithin et al. [26] proposed topology for 21
Level Multi Level Inverter which use less Number of
Switches. In this topology only one switch is added
for every increase in levels, so it uses 14 switches and
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Joshi and Agrawal
10 DC source. This topology reduces initial cost and
THD as compare to cascade multilevel inverter.
output voltage is improved and the waveform is
closer to sinusoidal.
Neelesh Kumar et al. [27] proposed topology for
Three-Phase Multilevel Inverter which contains Less
Number of Switches. This topology use 9 switches
for 1-7 level inverter and 27 switches for 3- 7 level
inverter. Morteza Farsadi, et al. [28] proposed
cascaded multilevel converter using Five-Level
Power Cell. The proposed multilevel converter is
based on a 5-level regenerative converter. The
advantage of this topology rather than diode rectifiers
is being regenerative. This topology has some
drawbacks, it needs a complex input transformer in
order to reduce low order, and the conventional
structure uses large number of switches. K Prasada
Rao et al. [29] interface renewable energy sources to
AC grid using multilevel inveter, this new topology
use less no. of switch and reduce losses and cost. V.
Arun et al. [30] analyzed the performance of
Asymmetric Multilevel Inverter with less no. of
switch they simulated fifteen level output voltage
generated by unipolar sine reference with UPDPWM
technique and found THD is 8.13%. Simulated
fifteen level output voltage generated by unipolar
THI reference with UPDPWM technique and THD is
21.84%. Simulated fifteen level output voltage
generated by unipolar sine reference with
UAPODPWM technique and THD is 8.17%.
Simulated fifteen level output voltage generated by
unipolar THI reference with UAPODPWM technique
and THD is 22.01%. Simulated fifteen level output
voltage generated by unipolar sine reference with
UCOPWM technique and THD is 11.72%. Simulated
fifteen level output voltage generated by unipolar
THI reference with UCOPWM technique and THD is
22.43%. Barsana and Ganapathy [31] design cascade
multilevel inverter for high voltage application which
is based on the combination of the sub multilevel
converter and full bridge inverter. This topology uses
a lower number of switches and components,
compared to other topologies, but also the full-bridge
converters operate at a lower voltage.
Fig. 3 shows the three level diode clamped
multilevel inverter, this inverter uses two series
connected capacitor to divide the DC bus voltage into
three levels Vdc/2, - Vdc/2 and 0. Both capacitors are
ground connected at the middle point. To obtain a
voltage level of +Vdc/2 the switch S1 and S2 is on, to
get output voltage - Vdc/2 switch S1‟ and S2‟ is on
and when S2and S1‟ is on the voltage is 0. Clamping
diode limit stress on each semiconductor switch is
Vdc/2 to which is voltage across one capacitor [6].
Ebrahim Babaei et al. [32] present new structure
for asymmetric multilevel converters. This consists N
series-connection of two interconnected multilevel
converters per phase. Each stage constituted by two
DC voltage sources, and six bidirectional switches.
The technique can generate a large number of levels
(odd and even). The main advantage of the topology
is the minimum DC voltage sources with the
maximum number of available levels.
Diode clamped multilevel inverter
The Diode Clamped Multilevel Inverter uses a
series connected semiconductor device to split bus
voltage. The diode clamp multilevel inverter use (n1) capacitor to produce n level output phase voltage
and (n-1) * (n-2) diodes is used. In a diode clamp
inverter for n level phase voltage the line voltage is
(2n-1). As the voltage level is high the quality of
Figure 3-Diode Clamped Multilevel Inverter.
The advantage of diode clamp multilevel inverter
is that it uses less number of capacitors and use only
one DC source. The disadvantage of this topology is
that when the level is increased high voltage stress on
clamping diode. At a high level the balance charging
of capacitor is also difficult. Harmonic in multilevel
inverter damage electronic circuit and machine parts
like bearings so to reduce harmonic losses in inverter
we use Modulation technique, so M. Kedareswari
[17] use sinusoidal pulse width modulation (SPWM)
reduces total harmonic distortion in Diode clamp
multilevel inverter, this simulation done on three and
five level diode clamp inverter and this shows that as
the no. of level increased the THD is reduced. To
reduce the switching level in diode clamp inveter R.
Pon Perumal, W. Razia ultana, and W. Razia Sultana
[18] use carrier based closed loop PWM technique
using SPWM and the THD contents in inverter
output voltages is minimized within 5%. Diode
clamp Inverter suffered from DC link unbalance,
snubbing rail ON, series association of clamping
diode and inner device indirect clamping problem.
Xiaoming Yuan and Ivo Barbi [33] research on this
and proposed a new topology for diode clamp
inverter, this resolve the serious problem of the
diode. The unbalance problem of DC link and
Snubbing rail ON are not resolved. To resolve DC
link unbalance problem Ali Ajami and Hossein
Shokri [34] proposed a new topology, this use a
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World Acad. J. Eng. Sci. 01 1009 (2014)
chopper circuit for capacitor voltage and no. of
switches is also reduce as compare to other propose
topologies. This topology gives fast dynamic
response of the chopper, reduce voltage stress on the
switch and give high reliability.
Flying capacitor multilevel inverter
Joshi and Agrawal
Cascaded hybrid h-bridge
Cascade Hybrid H-bridge inverter is shown in
Fig.-5. This consists of a full bridge inverter to
connect with a D.C. bus to form a high level inverter.
With the help of CHHB inverter the output level is
increased by using less no. of switches. By using the
n cascade full bridge inverter the output voltage level
is 4n+1 is obtained [12].
The Flying Capacitor Multilevel Inverter is
similar to diode clamp multilevel inverter, the only
difference is that it uses capacitor at the place of the
diode and voltage clamping is achieved by these
capacitors. To clamp voltage in an n level flying
capacitor inverter it need (n-1)*(n-2)/2 capacitor. The
stress on the each capacitor is Vdc/(n-1).
Fig.4 shows the 3 level capacitor clamp
multilevel inverter. From a 3 level inverter we get the
output voltage in three steps, i.e. +Vdc/2, 0 and Vdc/2. This output voltage +Vdc/2 is obtained when
switches S1andS2 are on, 0 obtain by switches S1
and S2„are on and -Vdc/2 is obtained by turn on the
switches S1„, S2„[6-7].
Figure 5- Cascade Hybrid H-Bridge Multilevel
Inverter
The output voltage of CHHB inverter shown in fig. 5
is 9 levels
i)
Figure 4-Flying Capacitor Multilevel Inverter.
In multilevel inverter the Harmonic Distortion
(THD), crest factor, distortion factor and form factor
are eliminated using various modulation techniques.
The pulse width modulation technique uses Variable
Frequency (VF), Phase Disposition (PD), and Phase
Opposition Disposition (POD), Alternate Phase
Opposition Disposition (APOD), and Carrier
Overlapping (CO) technique for reducing the
different losses. Balamurugan, et al. [17] performed
simulation on 3-ϕ 5 level flying capacitor multilevel
inverter with Phase Opposition Disposition Pulse
Width Modulation (PODPWM) and Carrier
Overlapping Pulse Width Modulation (COPWM) in
MATLAB-SIMULINK this experiment result that
PODPWM gives output with relatively low distortion
and COPWM provides relatively higher fundamental
RMS output voltage.
Switch Sa, S2, S8, D6 is on output voltage
is Vdc/4.
ii) When switch S1, S2, S8, D6 is on output
voltage is 2Vdc/4.
iii) When switch S1, S2, Sb, S6 is on output
voltage is 3Vdc/4.
iv) When switch S1, S2, S5, S6 is on output
voltage is Vdc.
v) When the switch S4, D2, S8, D6 is on output
voltage is 0.
vi) When switch Sa, S3, S8, D6 is on output
voltage is - Vdc/4.
vii) When switch S3, S4, S8, D6 is on output
voltage is - 2Vdc/4.
viii) When switch S3, S4, Sb, S7 is on output
voltage is - 3Vdc/4.
ix) When switch S3, S4, S7, S8 is on output
voltage is - Vdc/4.
Topologies of hybrid multilevel
inverter
By using the hybrid source and configuration
multilevel inverter give the output voltage at less no.
of switches and at low harmonic losses [13]. The
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World Acad. J. Eng. Sci. 01 1009 (2014)
Joshi and Agrawal
topologies of Hybrid Multilevel Inverter are as
follow:
iii) When switch S11, S14, S21, S24 is on output is
3VDC.
i) Hybrid Symmetrical Multilevel Inverter.
iv) When all switches are off output is 0.
ii) Hybrid
Inverter.
Asymmetrical
Multilevel
H-bridge
Hybrid Symmetrical Multilevel
Inverter
Fig. 6 (a) shows the symmetrical Multilevel
Inverter and 6 (b) show the output voltage waveform
of inverter. If N is the no. of DC sources than the
level of output voltage of given topology is 2N+1.
v) When switch S12, S13, S21, S23 is on output is –
VDC.
vi) When switch S12, S14, S22, S23 is on output is 2VDC.
vii) When switch S12, S13, S22, S23 is on output is 3VDC [15].
Fig. 6(a) shows the five level multilevel inverter,
the switch S1-S4 operates at high frequency and
produce desired output voltage and S5-S8 operate at
low frequency and generate positive and negative
voltage. In this way it generates the five level output
voltage [14].
Figure 7- Asymmetrical Multilevel Inverter.
Conclusion
In this paper some topologies of multilevel
inverters and their working are reviewed. This is
observed that with change in inverter topology and
output level, total harmonic distortion (THD) of the
inverter is changed.
Acknowledgment
Figure 6- (a) Symmetrical Multilevel Inverter and
(b) show the output voltage waveform.
The first and second authors would like to thank
Department
of
Electrical
and
Electronics
Engineering, Vindhya Institute of Technology and
Science, Indore (M.P.) India for providing the
necessary help and support for preparing this paper.
Asymmetrical Hybrid Multilevel
Inverter
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