Comparison of Transformerless Converter
Topologies for Photovoltaic Application Concerning
Efficiency and Mechanical Volume
W.-Toke Franke, Nils Oestreich, Friedrich W. Fuchs
Institute of Power Electronics and Electrical Drives
Christian-Albrechts-University of Kiel
Kaiserstr. 2 24143 Kiel, Germany
Phone: +49 431 8806106
Fax: +49 431 8806103
Email: tof@tf.uni-kiel.de, fwf@tf.uni-kiel.de
URL: http://www.tf.uni-kiel.de
Abstract—Three transformerless converters for three phase
solar applications are compared concerning efficiency, leakage
current and mechanical volume. The investigated topologies
are the voltage source inverter (VSI), the three level neutral
point clamped (NPC) inverter and the z-source inverter (ZSI).
Therefore the topologies are introduced and the working principles are explained. The power losses, the resulting leakage
current at the pv array and the volume of the inverter are
investigated mathematically, by simulation and experimental
measurements. From the efficiency point of view the NPC has
the best performance followed by the VSI and ZSI. The leakage
current is for all topologies acceptable.
Figure 1. Grid-connected solar system, Pictures: SMA Solar Technology AG
I. I NTRODUCTION
Due to great decrease of the prices for solar cells in 2009
and constant high prices for electrical energy there is an
increasing demand on high efficient three phase solar inverters.
During the last years many topologies of solar inverters have
been proposed [1]–[5]. In general they can be classified into
topologies with and without a transformer. The transformer
decouples the pv array and the grid avoiding leakage currents
at the panels. The transformer can also be used to boost
the input voltage [6]. The advantages of the transformerless
topologies are higher efficiency and less volume. However
the lack of the transformer also leads to some drawbacks:
The main problems are the leakage currents between the
solar panel and earth. These leakage currents are a risk for
humans touching the panel and for some kind of solar cells
they accelerate the aging of the cells. In this paper three
three-phase four wire transformerless topologies are selected
that overcome the problem of the leakage currents. They are
compared regarding their leakage currents, their power losses
and their volume. Therefore in section 2 the three systems
are described and mathematical equations for calculating the
power losses are derived. After that the leakage currents
are explained and main parts of the inverter are discussed
concerning their volume. In the next section the topologies
are compared to each other. At the end a conclusion is given.
978-1-4244-6391-6/10/$26.00 ©2010 IEEE
Figure 2. Voltage Source Inverter linked with a dc boost converter and
earthed midpoint
II. S YSTEM D ESCRIPTION
The regarded system is shown in figure 1. There is on the
left side the solar panel. For this analysis, a rated power of 5
kW and an open circuit voltage of 1000 V is chosen. In the
middle the solar inverter is shown, which is connected to the
grid by a LCL filter.
For the inverter three different topologies with earthed dc
link midpoint have been investigated:
• Three phase four wire voltage source inverter linked with
dc-dc boost converter (BC+VSI) (figure 2)
• Three phase four wire Z-Source inverter (ZSI) (figure 3)
• Three phase four wire neutral point clamped inverter
linked with dc-dc boost converter (BC+NPC) (figure 4)
724
Table I
R EQUIREMENTS FOR THE POWER SEMICONDUCTORS FOR A 5 K W P /
1000 V ARRAY
max.
max.
max.
max.
max.
Figure 3.
Z-source inverter with earthed midpoint
blocking voltage switches
blocking voltage diodes
RMS current boost switches
RMS current boost/dc link diode
RMS current VSI switches
BC+VSI
1200 V
1200 V
8A
8A
8A
ZSI
1200 V
1200 V
10 A
15 A
BC+NPC
1200 V / 600 V
1200 V / 600 V
8A
8A
8A
is blocking since the dc link is short circuit by turning all
switches simultaneously on. The current is limited by the
inductors in the dc link [11].
A. Power Losses
Figure 4.
Neutral point clamped inverter with earth midpoint
The boost converter of the BC+VCI topology is turned off
as long as the output voltage of the pv array is above 750 V.
When the input voltage of the inverter drops below 750 V the
boost converter adjusts the input voltage of the VSI Vdc to 750
V. In both operation modes the MPP-tracking is realized by
the VSI. Even though the maximum dc link voltage is 1000
V power semiconductors that are able to block 1200 V are
sufficient since 1000 V is the open circuit voltage. As soon
as the inverter starts to operate the voltage drops immediately
to the maximum power point voltage. During this process the
current fed into the grid is limited by the inverter control.
The requirements for the power semiconductors are listed in
table I. The NPC inverter is a three level topology producing
three voltage levels per phase leg as + V2dc , 0 V and V2dc to
the output. The advantage is that due to a lower current ripple
smaller filter efforts are necessary. The working principle is
that the inner switches define the positive and negative half
of the sinusoidal waveform. The outer devices modulate the
sinusoidal output current.
The Z-source inverter is a new inverter that has been
discussed in several papers [7] [8]. Because of its unique
dc link network it is suitable for similar applications as the
three phase voltage source inverter linked with a dc to dc
boost converter [9] [10]. As long as the input voltage is
above 750 V the ZSI works similar as VSI. In case the input
voltage drops below this mark, the ZSI starts to boost the
input voltage by applying shoot-through-states instead of zero
states. During such a shoot-through state the dc link diode
Operating semiconductors in switching mode, four different
kinds of losses occur. These losses are conducting and offstate losses as well as switching and driving losses. Compared
with the conducting and switching losses the off-state and
driving losses are very small and can be neglected [12]. In
the following the forward or conducting characteristics of the
semiconductors have been linearized. The conducting losses
PC are calculated for one IGBT and one diode and depend
on the mean and the rms values of the current iV through the
valves. VCE,0 and VF,0 describe the threshold voltages and rCE
and rF the differential ohmic resistances of the IGBT and the
diode, respectively.
PCIGBT = VCE,0 īV + rCE ĩV2
(1)
PCdiode = VF,0 īV + rF ĩV2
(2)
The switching losses are a function of the switching frequency, voltage and current. However they depend also on the
chosen PWM-method and the switching loss energies of the
IGBT (Eon , Eo f f ) and the diode (Erec ). In datasheets these
information are only given for a reference voltage vre f and
current ire f . The switching power losses are given for the
continuous PWM depending on actual voltage vV and current
iV [12] [13].
PSIGBT =
1
vv i v
fs (Eon + Eo f f )
π
vre f ire f
(3)
vv iv
1
fs Erec
π
vre f ire f
(4)
PSdiode =
B. Power Losses VSI+BC
The derivation of the power losses for the VSI+BC- topology are performed in [14] and [10]. Therefore only the final
results are presented here. Based on equation (1) and (2) the
conducting losses of the voltage source inverter with IGBTs
are derived:
IGBT
PC,V
SI =
725
VCE,0 îL
Mπ
cos ϕ +
1+
2π
4
rCE î2L π
2
+M
cos ϕ
2π
4
3
(5)
Diode
PC,V
SI =
VF,0 îL
Mπ
1−
cos ϕ +
2π
4
rF î2L π
2
−M
cos ϕ
2π 4
3
(6)
waveform is the sum of the sinusoidal grid current and the
shoot-through peaks, which are non-linear. The mean and rms
values of the shoot-through current through one IGBT are:
īIGBT
ST =
They depend on the line current iL , the modulation index M
and on the power factor cos ϕ. The switching losses are given
in (3) and (4) by subsituting the actual vv by Vdc and iv by iL .
The losses of the boost converter depend on the input current
iin and the modulation index a that is defined as:
Vin
Ton
= 1−
a=
Ts
Vdc
(8)
(9)
The switching losses of the semiconductors of the boost
converter are calculated by (3) and (4) with vv = Vdc and iv =
iin .
C. Power Losses NPC
The power losses of the boost converter with IGBT of
the NPC topology are derived according to (8) and (9). The
conducting losses of the NPC inverter with MOSFETsare
given in the following equations for the first leg and half a
fundamental period referening to (1), (2) and [15].
î2 RDS,on M
v1
Pcon
= L
(1 + cos ϕ)2
6π
î2 RDS,on M 3π
v2
Pcon
= L
+ 4 cos ϕ − cos 2ϕ − 3
12π
M
(10)
(11)
V f îL M
î2 R f M
(sin ϕ − ϕ cos ϕ) + L
(1 − cos ϕ)2 (12)
4π
6π
îLV f M 4
D1
Pcon =
+ 2ϕ cos ϕ − π cos ϕ − sin ϕ +
4π
M
(13)
1 M
−
1 + cos2 ϕ
+î2L R f
4 3π
′
Pin VC Tst
−
+
Vin 2L 2
For the calculation of the losses of the Z-source inverter with
IGBT the two operating modes have to be distinguished. In
case that the ZSI is working as VSI because the input voltage
is above 750 V the losses can be calculated as for the VSI.
In case that it is working in boost mode the additional losses
of the shoot-through-states have to be considered as well. The
derivation of the losses is performed in [10]. The main issue
is to derive the current through the valves, since the current
VC Tst 1
+
L 2
3
(15)
VC
L
2
Tst2
3
"
There the +-sign is for the IGBT and the −-sign for the
diode. While the mean value of the current through one IGBT
is the sum of īIGBT
and īIGBT
the rms values cannot be
G
ST
summed. As proposed in [10] an approximation for calculating
the rms value can be applied by defining the rms current as
done in the last factor of the following equations:
2
= VCE,0 īIGBT
PCIGBT
+ īST + rCE īIGBT
+ ĩST
L
L
low
2
PCIGBT
= VCE,0 īIGBT
+ īST + rCE ĩIGBT
+ īST
L
L
high
(18)
(19)
Depending on the ratio of the input and output voltage
equation (18) or (19) has to be applied. If the higher losses
are chosen the error is always below 3%. The losses for the
diodes are given by
′
D. Power Losses ZSI
where D is the duty cycle of the shoot-through states. The
mean and rms values of the current through one IGBT and
one diode are:
r
πM
2 Pout
IGBT /Diode
īL
=
cos ϕ
(16)
1±
3 2πVout,l2l
4
s
2
2 Pout
2
π
IGBT /Diode
± M cos ϕ
(17)
ĩL
=
2
3 2πVout,l2l
4
3
v1 ,v2
=
Pcon
The switching losses are calculated by (3) and (4) applying
Vdc
2 for vv and iL for iv .
(14)
v
!
u
u4
Pin VC Tst 2
t
+
D
−
=
9
Vin 2L 2
(7)
The modulation index is a function of the ratio of the input
voltage to the output voltage that is in this case the dc link
voltage. The IGBT of the boost converter is turned on for the
time Ton . The conducting losses for the IGBT and the diode
are
PCIGBT = VCE,0 īV + rCE ĩV2 · a
PCdiode = VF,0 īV + rF ĩV2 · (1 − a)
ĩIGBT
ST
2 Pin
D
3 Vin
2 Diode
+
r
PCDiode = VF,0 īDiode
ĩ
(1 − DST )
F L
L
(20)
The conducting losses of the dc link diode and the switching
losses also based on (3) and (4) can be found in [10].
E. Leakage Current
One of the main issues of transformerless solar inverters is
the leakage current at the pv array. It arises due to variation of
the dc link potential to ground that derives from the switching
pattern. Assuming that the load is y-connected the midpoint
of the dc link has four different potential during one switching
period. During one of the two zero-states all three phases of the
grid are short circuited by having all upper devices conducting
and the lower ones blocking or vice versa. In this state the
upper or lower rail of the dc link is connected to ground so
that the midpoint of the dc link is at ± V2dc . During active states
one device of each phase is conducting whereas at least one of
them is in the upper half and one is in the lower half. In case
726
that two upper device and one lower device is conducting two
phases are switched in parallel and connected to the upper dc
link rail. Thus the voltage drop across the load is only half of
the voltage drop of the phase that is connected to the lower
dc link rail. That leads to a midpoint voltage of the dc link
to ground of − V6dc and to V6dc in case that two device in the
lower half are conducting. To reduce the leakage current at
the panel one very effective way is to connect the midpoint to
CPV
.
ground. The leakage current is reduced by a factor of 2C
dc
valid for the proposed three phase four wire system.For the
NPC inverter the current passing through the clamping diodes
into the dc link has to be considered that leads to very long
equations. Calculations and simulations have shown that (22)
also lead to acceptable results for the NPC inverter. Beside the
current ripple caused by the inverter also the current ripple
of the boost converter has to be considered that is for both
inverters the same:
q
1
3 (1 − a) ∆iind 2 + 12 iin 2 a
6
īBC = (1 − a) iin
r
1
ĩC,BC =
(1 − a) ∆iind 2 + 12 iin 2 a
12
ĩBC =
F. Volume
The volume of the solar inverter is given by the size of
the discrete parts as heat sink, filter inductors and capacitors,
dc link capacitors, boost inductor, power semiconductors and
control section. In this paper the heat sink, the dc link
capacitors and the inductors are regarded.
1) Heat sink: The size of the heat sink is determined by its
ability to dissipate the power losses of the semiconductors Ptot .
The heat dissipation is proportional to the thermal resistance
Rth,HA between the heat sink and the ambient. The maximum
thermal resistance that limits the junction temperature of
the power device to their maximum temperature T j,max is
calculated by [16]
Rth,HA,max =
T j,max − TA
− Rth,tot
Ptot
(21)
Here Rth,tot describes the total thermal resistance between
junction and heat sink. The volume of the heat sink is inversely
proportional to Rth,HA
2) DC Link Capacitors: The number of the electrolytic
capacitors in the dc link is determined by the maximum
allowed current ripple for a specified lifetime of the capacitors
and the maximum allowed voltage drop during load steps. For
solar applications the load steps are not a big issue, since the
power of the pv array changes slowly and the changes in the
grid voltage are occur infrequently. Therefore the number of
capacitors is derived due to a lifetime of 10 years. From the
datasheet of the capacitors its lifetime for a specific magnitude
of the rms value of the ripple current at 100 or 120 Hz can
be extracted. Higher frequencies have to be converted into its
equivalent 100 Hz frequency concerning the application notes.
In the following the current ripples for the different topologies
are calculated.
Current Ripple of the DC Link Capacitor for the BC+VSI
and BC+NPC
The ripple current for the VSI is calculated by
q
ĩ2dc − ī2dc
v !
""
!√
u
√
u
3
3
9M
+ cos2 ϕ
−
= îL tM
4π
π
16
ĩC,V SI =
(22)
The derivation of the ĩdc , īdc and (22) can be found in
[17]. Even though the equations are derived for a three phase
three wire system simulations have shown that they are also
(23)
Since the dc link capacitor decouples the ripple of the boost
converter and the VSI, it has to carry both ac components.
Typically ripple currents produced by the inverter and the
boost converter have different frequencies. For calculating the
lifetime of the capacitor the current ripple has to be transferred
to an equivalent current ripple at 100 Hz ĩ100 for the specific
capacitor by a factor given in the datasheet [18].
For the worst case when none of the ripples are canceled
out the rms of ac current is
q
(24)
ĩ100,C,tot = ĩ2100,C,V SI + ĩ2100,C,BC
Current Ripple of the DC Link Capacitors of the ZSI
The ZSI requires three capacitors and two inductors in the
dc link. In case the ZSI is not in boost operation the ripple
current for all four capacitors is the same and can be calculated
according to (22) since the high frequent current has to pass
through all four capacitors. Assuming that the inductor current
is constant, the ripple current through the boost capacitors C1
and C2 in boosting mode is
r
D
Vin
ĩC1,2 =
(25)
Pin 1 − D
For calculating the ĩ100 value, twice the switching frequency
has to be taken as a basis. Since the rms current from (25)
is for typical boost duty cycles (D = 0.1...0.3) much higher
than the rms value of the capacitor current due to the switching
transients calculated by (22), the last one can be neglected. The
inductances L1 and L2 are designed according to the maximum
allowed current ripple that is calculated for the maximum
boost modulation by
!
√ "
√
3D Vin
3
1
1−
D
(26)
∆iL1,2 = √
2L
2
2
fsw
3D − 1
and the input current.
Calculation of the required number of capacitors
The number of capacitors in parallel is determined by the required lifetime of the inverter. The lifetime L of the aluminum
electrolytic capacitors depend on the ambient temperature TA
and the standardized current ripple ĩ100,C,tot [18]:
727
L = L0 2
T0 −TA
10
2
− 1k ∆T0
ĩ100,C,tot
ĩC,rated
2
(27)
There L0 , T0 , k, ∆T0 and ĩC,rated can be found in the
datasheet. If the required lifetime is not reached the current
ripple per capacitor has to be reduced by connecting capacitors
in parallel. The volume of the capacitors depends on the dc
voltage and the capacitance. For the EPCOS B43501 with a
rated voltage of VR = 500V the volume can be approximated
by
VolCdc =
C
µF
2.5 cm
3
+ 27cm3
(28)
3) Inductances: Even though the grid filter is designed as
a LCL filter the volume of the capacitor will be neglected
in this paper since it will be designed similar for all three
inverters. The volume of the inductors is roughly proportional
to its stored energy W :
Figure 5. Leakage current of VSI, NPC and ZSI. Red line is the rms value
of the leakage current, Pin = 2500 W
1
(29)
VolL ≈ W = Lĩ2L
2
The line current through the grid filter is for all topologies
equivalent. For the VSI and ZSI also the same inductances may
be applied. For the NPC inverter only half the inductances are
required due to the three voltage levels. The inductances of
the boost converters in the dc link of the VSI and the NPC
inverter are designed similar. For the ZSI the sum of both the
dc link inductors must have a higher energy storage capability
as for the boost converter, since a boost of the dc link voltage
requires a reduction of the modulation index to achieve longer
shoot-through states on the one hand but also cause a buck
behavior of the inverter on the other hand.
Figure 6. Efficiency based on thermal simulation with PLECS (Matlab),
Input Voltage 650 V
III. C OMPARISON
Based on the equations derived in section 2, simulations
and measurements of the three topologies VSI, ZSI and NPC
inverter are compared concerning their leakage currents, their
efficiency and their volume.
Simulations (figure 5) and measurements have shown that
the rms value of the leakage currents is for all three topologies
similar and meets the relevant standards as VDE 0126-1-1.
The simulated and measured efficiency is shown in 6 and 7.
To achieve comaprable results the semiconductors are rated to
operate at maximum load at 120◦ C junction temperature and
80◦ C heat sink temperature. No semiconductors are connected
in parallel. The measured efficiencies are for all topologies
lower than the simulated ones. For low power it could be
identified that the waveform of the efficiencies derivate for all
topologies since the resistors to balance the dc link capacitors
have been neglected in simulations. However they produce
constant power losses of 10 W for the NPC and VSI and
30 W for the ZSI. The volumes of the inverters are roughly
compared in table II. The heat sink is designed according to
the maximum power losses as described in section II The NPC
and VSI require the same number of dc link capacitors while
for the ZSI a high number parallel capacitors is necessary due
Figure 7.
Efficiency based on measurements with DEWETRON 2010,
Accuracy 0.5% Vin = 525V
Table II
VOLUME
Heat sink
DC capacitance
Inductance dc link
Inductance grid filter
728
BC+NPC
+
+
+
+
BC+VSI
0
+
+
0
ZSI
0
to the high shoot through current ripple. For the same reason
two larger dc link inductors are needed for the ZSI. The grid
filter is the same for VSI and ZSI while the NPC has the same
THD value with less inductance due to the third voltage level.
IV. C ONCLUSION
Three transformerless three phase topologies for solar inverters have been analyzed by simulation and measurements
concerning their efficiency, leakage current and volume. It can
be concluded that all of them meet the requirements of the
standards in view of the leakage currents at the pv array.
Concerning the efficiency the neutral point clamped inverter
linked with a boost converter shows the best results followed
by the voltage source inverter with boost converter. The Zsource inverter has the lowest efficiency even though it has
the fewest power semiconductor devices. The reasons are the
high switching losses for the shoot-through-states. The size
of the inverters is mostly depending on the passive elements
and the heat sink. The number of power devices is secondary.
Due to that the NPC inverter is the smallest since it has the
smallest heat sink and the smallest filter elements. Again it is
followed by the VSI+BC.
ACKNOWLEDGMENT
This work is sponsored by the Rainer Lemoine Stiftung
(RLS).
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