DATASHEET
TSMC STANDARD CELL LIBRARIES
Standard cell libraries are the basic building blocks for today’s advanced submicron IC design. TSMC’s standard cell libraries are developed in conjunction with
process technology through daily interaction between process developers and
library engineers. Frequent updates and repeated benchmarking produce current,
efficient design building blocks for designers targeting 90nm, 0.13-micron and
0.15-micron TSMC processes.
OVERVIEW
Library densities of 448/243/182
Kgate/mm2 for 90nm, 0.13-micron and
0.15-micron process technologies,
respectively, are industry competitive,
while maintaining rigorous TSMC 9000
compliance. To ensure fast, easy
integration into IC design flows, these
libraries have been validated using
TSMC’s Reference Flow. Each library
contains a design kit with associated
views for leading design tools. For
more flexible and efficient SoC power
designs, multiple transistor threshold
options are available for the library
standard cells.
FEATURES
– CLN90G, CLN90LP and CLN90HS
nodes for 90nm
TSMC STANDARD CELL FEATURES
– High-Low-Vt libraries for speed/
power optimization (0.13µm, 90nm)
• Highly routable with high gate density:
– P&R routed density of 182/243/448
K-gates/mm2 for 0.15µm/0.13µm/90nm
• Wide Driving Strength range:
– BUFFDx/INVDx/CKBDx : up to D24
– Simple Logic/Storage Cells : D0, D1,
D2, D4
– Other Cells : D0, D1, D2, D4, D8
• Comprehensive library list for all
process derivatives:
– CL015G and CL015LV nodes for 0.15µm
– CL013G, CL013LV and CL013LP nodes
for 0.13µm
• TSMC Reference Flow certified for
0.15µm and below
0.13µM/90NM STANDARD CELL
FEATURES
• A new cell architecture that improves
performance with 30% more transistor
drive compared to prior generation
• P/N ratio optimized for inverter, nand
and nor gate delays
• High quality library data in leakage,
power and timing:
– Complete leakage data including
gate leakage for all input states
– Setup/hold time keeps a positive
metastability window
– Built in antenna diode in clock
buffers, CKBDx
• Wire-load tables derived from Placeand-Routing results
• All layers of copper metal and Low-K
dielectric material
HIGH PERFORMANCE FEATURES
• High gate density with 448K routed gates per mm2
• Optimized for density/performance/yield
• Wide driver strength range
• Optimized 1X driver for inverter, nand and nor delays
• Aggressive in cell size while maximizing routing resources
• Manufacturability considered in layout
• Wide-wire routing support for signalEM and critical path timing in high
drive cells
TSMC FOUNDRY-VALIDATED DESIGN
• Part of TSMC’s advanced technology
development
• Early integration of customer’s design
into real silicon
Cell family
Cell type
0.15µm
Drive
strength
0.13µm/
90nm
(AND/NAND)/(OR/NOR)/(XOR/XNOR)
3 each
3 each
5/6/4 each
Buffer/3-state Buffer w/ & w/o enable/Inverter
1 each
1 each
11 each
AOI/OAI/AO/OA/MAO/MOAI
12 each
39
4 each
Half/Full Adder
1 each
2
3 each
Mux with/without inverted output
3 each
6
4 each
Clock Buffer/Inverted Clock Buffer/Gated Clock Latch
1 each
1 each
11/11/10 each
• Support of comprehensive EDA tools
DFF: pos-edge, neg-edge, async/sync R/S, w/o R/S
15
15
3 each
• Proven track record — multiple
customer tapeouts
Enable DFF; async/sync R, w/o R
6
6
3 each
Scan version of all DFFs
21
21
3 each
Latch: active high/low enable, async R/S
8
8
3 each
Balanced Rise/Fall INV/NAND/AND/MUX/XOR
1 each
5
4 each
Dlay/Tie-High/Tie-Low
1 each
4
4/1/1 (5/1/1)
N/A
• Based on silicon-proven standard cell
architecture
Antenna cell/Decoupling cells
2, 7
7
Total Cell Number
514
557
TSMC STANDARD CELL CATEGORIES
Technology
(process)
Product
P&R gate
density
(Kgates/mm2)
Leakage
(nW)
Internal
power
(nW/MHz)
Speed
(ns)
90 nm
General Purpose (G)
G/Over Drive (OD)
G/High Vt (HVT)
G/Low Vt (LVT)
G/Over Drive/High Vt (HVT)
G/Over Drive/Low Vt (LVT)
Low Power (LP)
High Speed (HS)
448
0.02–61.8
1.9–16.7
0.022–0.053
0.13µm
General Purpose (G)
G/High-Vt (HVT)
G/Low-Vt (LVT)
Low Voltage (LV)
LV/High-Vt (HVT)
LV/Over Drive (OD)
Low Power (LP)
LP/Low Vt (LVT)
243
0.008–12.5
3.3–8.5
0.034–0.065
0.15µm
General Purpose (G)
Low Voltage (LV)
182
0.058–0.51
6.1–9.8
0.05–0.054
© 2003 Cadence Design Systems, Inc. All rights reserved.
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of their respective holders.
4456B 04/03