Ioannis Karampoikis
DEVELOPING AND
INVESTIGATION OF A DIODE
CLAMPED THREE LEVEL
INVERTER-LEG WITH PASSIVE
UNDELAND SNUBBER
Master Thesis, August 2011
Ioannis Karampoikis
DEVELOPING AND
INVESTIGATION OF A DIODE
CLAMPED THREE LEVEL
INVERTER-LEG WITH PASSIVE
UNDELAND SNUBBER
Master Thesis, August 2011
DEVELOPING AND INVESTIGATION OF A DIODE CLAMPED THREE LEVEL INVERTER-LEG
WITH PASSIVE UNDELAND SNUBBER
Author:
Ioannis Karampoikis
Supervisor(s):
Associate professor, Tonny W. Rasmussen
Department of Electrical Engineering
Centre for Electric Technology (CET)
Technical University of Denmark
Elektrovej 325
DK-2800 Kgs. Lyngby
Denmark
www.elektro.dtu.dk/cet
Tel: (+45) 45 25 35 00
Fax: (+45) 45 88 61 11
E-mail: cet@elektro.dtu.dk
Release date:
2011 August 12
Class:
1 (public)
Edition:
1.
Comments:
This report is a part of the requirements to achieve in
Engineering (MSc) at Technical University of Denmark.
The report represents 35 ECTS points.
Rights:
© Ioannis Karampoikis,
Table of Contents
ABSTRACT...................................................................................................................................................5
ACKNOWLEDGMENTS .............................................................................................................................6
LIST OF ABBREVIATIONS........................................................................................................................7
INTRODUCTION..........................................................................................................................................8
I.1 Problem Formulation...........................................................................................................................8
I.2 Project Description...............................................................................................................................8
CHAPTER 1.................................................................................................................................................11
Diode Clamped Three Level Inverter...........................................................................................................11
1.1 High Power Electronics......................................................................................................................11
1.2 Nature of Electrical Power Networks.................................................................................................13
1.2.1 Harmonic Voltages and Currents...............................................................................................14
1.2.2 Compensation of Reactive Power...............................................................................................14
1.3 Power Inverters and Converters.........................................................................................................16
1.4 Asymmetrical Inverter Leg................................................................................................................19
1.5 Diode Clamped Three Level Inverter ...............................................................................................20
1.6 Undeland Snubber Circuit .............................................................................................................23
1.7 Modulation Of Diode Clamped Three Level Inverter.......................................................................25
CHAPTER 2................................................................................................................................................28
Introduction.............................................................................................................................................28
2.1 Components Selection Criteria..........................................................................................................28
2.2 Calculation Of Snubber Circuit Components....................................................................................29
2.2.1 Asymdim....................................................................................................................................29
2.2.2 Data Classification .................................................................................................................31
2.2.3 Calculation Of Inductance.........................................................................................................32
2.2.4 Computation Of Diode Characteristics.....................................................................................33
2.2.5 Estimation of Capacitor (C0).....................................................................................................35
2.2.6 Estimation of RS And CS .........................................................................................................37
2.3 Calculation Of Semiconductors Characteristics................................................................................44
2.3.1 Clamped Diode..........................................................................................................................46
2.3.2 IGBT Module............................................................................................................................48
2.3.3 Snubber Diodes.........................................................................................................................52
2.4 Thermal Design Of Semiconductors ...........................................................................................54
2.4.1 IGBT Module.............................................................................................................................55
2.4.2 Snubber Diode...........................................................................................................................59
2.4.3 Clamp Diode..............................................................................................................................61
2.5 Summary of Results..........................................................................................................................65
CHAPTER 3 ...............................................................................................................................................68
P­SPICE Investigation Of DCVSI................................................................................................................68
3.1 Building of the DCVSI in P­SPICE...................................................................................................68
3.2 Positive Current Simulations.............................................................................................................70
3.2.1 ''Turn­on'' and ''Turn­off'' of Units S1 and S2 (State “0”)..........................................................70
3.2.2 ''Turn­on'' and ''Turn­off'' of Units S2 and S3 (State “1”)..........................................................75
3.2.3 ''Turn­on'' and ''Turn­off'' of Units S3 and S4 (State “2”)..........................................................81
3.2.4 ''Turn­on'' and ''Turn­off'' of units S3 and S2 (State “3”)...........................................................86
3.3 Negative Current Simulations...........................................................................................................90
3.3.1 ''Turn­on'' and ''Turn­off'' of the two upper IGBT units (State “0”)...........................................91
3.3.1 ''Turn­on'' and ''Turn­off'' of two middle IGBT units (State “1”)...............................................93
3.4 Estimation of Losses.........................................................................................................................94
3.4.1 Conduction Losses.....................................................................................................................95
3.4.2 Switching Losses.......................................................................................................................96
3.4.3 Power Losses in Snubber Resistors...........................................................................................99
CHAPTER 4...............................................................................................................................................101
Laboratory Investigation Of DCVSI...........................................................................................................101
4.1 Design Process Of Inverter's Hardware...........................................................................................101
4.1.1 Inductor Design ................................................................................................................102
4.2 Overview Of Inverter's Hardware....................................................................................................106
4.2.1 Pulse Generator........................................................................................................................106
4.2.2 Gate Driver .............................................................................................................................109
4.2.3 Hardware of the Diode Clamped Three Level Inverter ...........................................................111
4.3 Experimental Results.......................................................................................................................113
4.3.1 Voltage Spike Occurrence........................................................................................................113
4.3.2 Results Using an L = 4,66mH..................................................................................................115
4.4 Discussions .....................................................................................................................................120
CONCLUSION..........................................................................................................................................121
FUTURE WORK.......................................................................................................................................123
REFERENCES...........................................................................................................................................124
APPENDIXES...........................................................................................................................................125
A.1 Estimation Of Junction to Ambient RTH.......................................................................................125
A.2 N87 Inductor Core characteristics..................................................................................................126
A.3 Observations For A Positive Current Direction..............................................................................127
A.4 Negative Current Direction – Waveforms.......................................................................................128
A.5 Current Flow through lower IGBT module....................................................................................137
A.6 Positive Current Direction – Waveforms......................................................................................140
A.7 Evaluation of Snubber Diodes Switching Losses...........................................................................149
ABSTRACT MSc Thesis ­ Spring 2011 ABSTRACT
The subject of this Master Thesis concerns the development and investigation of a
single phase diode clamped three level inverter including for snubber circuit a passive
Undeland snubber. Primarily, the inverter is designed theoretically using P-Spice and
Asymdim simulation softwares. The system's switching behavior is analyzed in order to
appoint the critical points and its total losses are estimated. A pragmatic model of the
inverter is also constructed and its experimental behavior is analyzed with the main intention
to compare the experimental to the theoretical results. Additionally, the usefulness of using
the clamp resistor had to be investigated.
5 of 149 ACKNOWLEDGMENTS MSc Thesis ­ Spring 2011 ACKNOWLEDGMENTS
I wish to thank the following persons for their contribution during the accomplishment
of this Master Thesis:
My head supervisor associate professor Tonny W. Rasmussen
for his guidance,
assistance, and valuable discussions throughout this Master Project. His aid in the
experimental part of the project was crucial.
My student mates but most of all friends, Stauros, Ioannis, Ahmed, Walid and Sally for
their support during this semester.
6 of 149 LIST OF ABBREVIATIONS MSc Thesis ­ Spring 2011 LIST OF ABBREVIATIONS
AL: Inductance factor
ASVC: Advanced Static Var Compensator
DCTLI: Diode Clamped Three Level Inverter
DCVSI: Diode Clamped Voltage Source Inverter
DFR_S1 : Anti-parallel free-wheeling diode of IGBT unit S1
DFR_S2 : Anti-parallel free-wheeling diode of IGBT unit S2
DTU: Technical University of Denmark
g: Air-gap distance of the core
IGBT: Insulated Gate Bipolar Transistor
Lower IGBT Module: An IGBT module which contains the two IGBT units S3 and S4
P-Spice: Personal Computer Simulation Program with Integrated Circuit
Emphasis
PCB: Printed Circuit Board
Pcon: Conducting Losses
RD: Dynamic Resistance
RTH: Thermal resistance
S1: IGBT unit which includes an IGBT switch in parallel with a freewheeling diode
S2: IGBT unit which includes an IGBT switch in parallel with a freewheeling diode
S3: IGBT unit which includes an IGBT switch in parallel with a freewheeling diode
S4: IGBT unit which includes an IGBT switch in parallel with a freewheeling diode
Tj: Maximum junction temperature
Upper IGBT Module: An IGBT module which contains the two IGBT units S1 and S2
VSI: Voltage Source Inverter
7 of 149 INTRODUCTION MSc Thesis ­ Spring 2011 INTRODUCTION
I.1 Problem Formulation
Applications of high-efficiency switching converters cover a wide range of power
levels. Considering applications of less than one watt, converters can be found within
battery-operated portable equipment. In a range of tens, hundreds or thousands of watt
converters within power supplies for computer and office equipment can be found. The use of
power electronic converters extends to larger power level ranges up to roughly 1000
Megawatts in the rectifiers and inverters that interface DC transmission lines to the AC
utility power system [Erickson and Maksimovic, 2001] .
Thereby, the voltage limitation of the IGBT'S, semiconductors transistors or
alternatively electronic switches, in high power applications composed the problem
formulation of this project. More specifically, when converters for high power has to be
designed each IGBT has a voltage limit of U = 6.5 kV which is inadequate since higher
voltage levels are required. Higher voltages can be achieved by utilizing a series connection
of several IGBT units. One way to attain high voltage levels is by using a clamp diode three
level inverter leg. The principle of operation of this inverter is based on the asymmetrical
type of an inverter leg.
I.2 Project Description
This thesis concerns the development and investigation of a single phase, three level
diode clamped inverter leg, DCTLI, which is equipped with a passive Undeland snubber
circuit. The electronic circuit of the system is depicted in figure I1 .
The word investigation corresponds to the theoretical analysis of the inverter system.
Through this analysis several aspects such as, the importance of using the Undeland snubber
circuit, knowledge about switching and conducting loses as well as inverter's switching
behavior in order to point out critical connections, will be covered. Additionally, analysis will
8 of 149 INTRODUCTION MSc Thesis ­ Spring 2011 be implemented regarding the usefulness of the clamped resistor, Rcl. The theoretical
analysis will be covered using the computer aided softwares “Orcad P-Spice” and
“Asymdim”.
Figure I1: Three level diode clamped inverter leg
The word development corresponds to the construction of a laboratory model of the
depicted inverter leg. Thus, an electronic printed circuit board, PCB, will be constructed in
the laboratory with the main intention to verify the theoretical operational behavior of the
inverter, derived using Orcad P-Spice software. In order to create a liturgical pragmatic
model of the DCTLI additional hardware had to be designed, such as a gate driver and a
pulse generator.
The inverter consists of a ±400V DC voltage side and it delivers a peak load current
of 42,5 A. For the experimental investigation of the model as well as calculation purposes a
9 of 149 INTRODUCTION MSc Thesis ­ Spring 2011 switching frequency of 10kHz was chosen to be followed.
The switching part of the pragmatic model of the DCTLI will be constituted by two
“2MBI150U2A-060 , 600V 150A” IGBT modules provided by “Front Runners”. All the
other components that are incorporated in the inverter will have to be determined through
theoretical analysis.
Throughout this thesis, reference to the several components of the inverter have been
implemented using the names depicted in the above figure. Additionally, at this point it is
nice to mention that the term IGBT module corresponds to the device which “houses” two
IGBT switches with their corresponding anti-parallel free-wheeling diodes. In the above
figure two IGBT modules in total can be found, upper and lower. Moreover, the various
IGBT switches with the anti-parallel diodes will be referred as IGBT units. Similarly, in
figure I1
four in total IGBT units present, S1, S2, S3 and S4. The latter term discrimination
was implemented with the main intention to avoid any possible confusion.
10 of 149 CHAPTER 1 MSc Thesis ­ Spring 2011 CHAPTER 1
Diode Clamped Three Level Inverter
This main intention of this chapter is to present and analyze the objective of this
Master Thesis, the diode clamped three level inverter. Prior reaching the main objective the
chapter begins by briefly introducing high power electronics and their importance in
electrical systems and networks. Thus, anaphora will be presented in basic electronic
circuits, such as the inverter-leg and the Undeland snubber, and in the technology of power
converters.
Thereinafter, the chapter focuses on the clamped diode three level inverter by
describing its equivalent circuit and by elucidating some of its basic operational aspects. At
last, this chapters makes a briefly anaphora about modulation techniques of inverters
outputs. Additionally, the voltage output of the DCTLI is modulated using the fixed pulse
pattern modulation technique where the third harmonic voltage is eliminated.
1.1 High Power Electronics
Nowadays, the field of power electronics possesses a substantial role within the
operation of electrical power systems. Power electronics history originated at the beginning
of the twentieth century but its technologies have gained an intense evolution during the
last forty years. The rapid development in devices, circuits, components, controls and
systems have caused power electronics to emerge as a significant and necessary technology
within the electrical power networks [Ying-Yu Tzou, 1996] .
Electronics field could be defined as an enabling technology, which provides the
needed interface between an electrical source and the necessary consumption unit, an
electrical load. An equivalent circuit can be seen in figure 1.1 . In many cases the electrical
sources and loads differ in frequency, voltage amplitudes and the number of phases. The
power electronics interface facilitates the transfer of power from the source to the load by
11 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 converting voltages and currents from one form to another. The power transfer process can
be managed by using a controller unit which ensures that the conversion of voltage and
current will be achieved with high energy efficiency and power density [Mohan, 2007] .
Figure 1.1. Simple representation of power electronics interface within an electrical system
Power electronics incorporate concepts from a diverse set of fields such as, analog
circuits, electronic devices, control systems power systems, magnetics, electric machines
and numerical simulation and their practice requires a broad electrical engineering
background [Erickson and Maksimovic, 2001] . The latter fact was experienced in this project
since in order to construct the various hardware regarding the experimental investigation of
the three level inverter, analogue electronics knowledge was also required.
Additionally, they cover a wide array of applications such us power the information
technology, robotics and flexible production, power transfer and energy conversion.
Nowadays, renewable energy sources such as solar, wind and biomass, have gain a significant
advantage over conventional methods of energy production due to their unlimited existence
and environmental friendly nature [Yang Chen and Smedley, 2004] . In renewable energy
technologies power electronics can be found in a photovoltaic system in order to convert the
produced DC power to useful, for household applications, AC power. Moreover, power
electronics can be also found in wind turbine technology in order to synchronize the variable
frequency AC voltage, produced by an induction generator, to the line frequency voltage of
the utility grid [ Mohan. 2007] .
12 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 1.2 Nature of Electrical Power Networks
Electrical networks are not free of various form of disturbances. Their occurrence can
be a result of the grid's reactive nature, existence of harmonic voltages and currents and the
continuous increase of power demand by the consumers. Between 1971 and 2003 the world's
primary energy demand almost doubled and a further increase in the order of 40 per cent it
is expected to happen by 2020 [Brendan et al, 2007] . Increase in power demand creates
higher voltage and current harmonics.
Furthermore, renewable energy sources have
gained a significant advantage over
conventional energy production methods. In 2003 renewable energy contributed 13.5 per
cent of the world's total primary energy. Although the capacity of world's hydro plant is
much larger than wind power capacity, 800GW of power produced by hydro plants and
60GW produced by wind turbines, most of the renewable energy activities centered in wind
turbine technology [Brendan et al, 2007] . In wind and solar power technologies high power
electronics hold a significant importance. Most of the generators types, usually
asynchronous induction generators, within the nacelle of the wind turbines require reactive
power in order to energize its magnetics circuits. This needed amount of reactive power is
produced by the power plants and it is thus drawn from the network. However, is it always
desirable to produce the reactive power at the grid point where is needed since otherwise
transmission grid losses increase which in turns might lead to voltage instabilities. Hence
compensation of reactive power is often implemented for single win turbines or for an entire
wind farm. Different types of irregularities that can be compensated using power electronics
applications are listed below [Rasmussen et al, 2010] :
➔ Harmonic currents
➔ Harmonic voltages
➔ Reactive current
➔ Long interruptions
➔ Voltage stability
➔ Over and under voltages
13 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 1.2.1 Harmonic Voltages and Currents
Harmonic content within current's waveform develops by non-linear loads such as a
diode rectifier in parallel with a smooth capacitor. Diode rectifiers are widely found in low
voltage level networks, used to produce high voltage DC to a switch-mode converter. The
content of higher harmonics within a current waveform is given in percentage by the so
called total harmonic distortion, THD. It is defined as the square root of the sum of the
squares of the harmonic currents divided by the fundamental current, and it is given by the
following equation:
√(I
THD=
2
2
+I 23+I 24+........+I 2n)
⋅100
I1
(1.1)
What is more, electrical loads are characterized by their power factor, PF or cosφ,
which shows its ability to limit the harmonic currents. It is defined as the ratio of the active
power, P, divided by the apparent power, S [Rasmussen et al, 2010] :
cosφ=
P
U RMS⋅I RMS
(1.2)
Where,
URMS: The root mean square value of the voltage
IRMS: The root mean square value of the current
As a result of high harmonic currents is the reduction of load's power factor which in
turns increase the transmission grid losses. The harmonic currents can be removed by filters
or they can be compensated up to a high frequency at a given point in the grid and thus, the
non-linear loads no longer send harmonic currents into the grid [Rasmussen et al, 2010] .
1.2.2 Compensation of Reactive Power
Reactive power is the maximum value of the instantaneous power absorbed by the
reactive component of an electrical load [Glover et al, 2008] . It can be determined by the
following equation:
14 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 Q=U⋅I⋅sinφ
(1.3)
Where,
U: The fundamental phase to neutral voltage
I: The fundamental phase current
φ: The angle between the voltage and the current
This type of power is generated or absorbed all over in the grid from inductive or
capacitive loads and thus, when a resistive load presents, only active power is exchanged
between the load and the source.
Reactive power can be also generated from the grid itself where overhead lines and the
leaking in the transformers give a reactive inductive power as a result of their inductive
nature. Additionally, cables give capacitive reactive power because of their capacitive
nature. Large amounts of reactive power reduce the power factor of the loads, causes
voltage drops across the busbar points of the network and consequently affect the stability
of the power system. Generally speaking, the inductive reactive power absorbed by the load
can be compensated using capacitors and on the contrary capacitive reactive power can be
compensated using inductors [Rasmussen et al, 2010] .
Compensation of reactive power can
be achieved using several power electronics
applications such as, a thyristor switch capacitor, a static var compensator, an advanced
static var compensator, series capacitor method, Line conditioner etc. An advanced static
compensator is depicted in figure 1.2 .
Using such a compensator it is possible to generate a symmetrical three phase voltage
pulse pattern in the inverter side of the system. The other side of the system corresponds to
the power grid. By generating the right inverter's voltage and angle it is possible to control
its DC voltage and the current through the reactors and hereby, the sending reactive power.
In the next section the relation between inverter's and grid's voltage as well as the meaning
of angle “δ” are introduced. Furthermore, in the figure of the ASVC it can be observed the
difference in the meaning of the widely used terms “inverter” and “converter”. The term
converter contains the whole power electronics system plus the reactors between the grid
and the inverter while only the power electronics part of the system represents the inverter.
15 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 Figure 1.2: Description of a six pulse voltage source advanced static var compensator [Rasmussen et al, 2010]
1.3 Power Inverters and Converters
Generally speaking an inverter is can be defined as an electrical device which converts
the direct current, DC, to alternating current, AC. This property of the inverters appoint
them very useful for the cases where AC power is not available. Examples include operating
appliances in mobile homes as well as audio, video and computing equipment in remote areas
[Jaycar Electronics, 2000] .
The principle of operation of an inverter is based on the “inverter leg”. Its principal
construction is depicted in figure 1.3 . As it can be seen, using a pair of IGBT units the DC
power can be easily converted into AC power. The inverter leg consists of two controllable
semiconductors S1 and S2, in this example two IGBT units are shown, with their
corresponding free-wheeling diodes.
16 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 Figure 1.3: Principal construction of an inverter leg including two IGBT units
The DC voltage side of the inverter is split in two parts and the middle point is used
as the voltage reference. The output voltage, u, measured on the AC side of the inverter
mainly depends on the state condition of the switches. When, the upper IGBT unit is
turned-on then a +U/2 V output is obtained. On the contrary, when the lower IGBT is
turned-on while the upper is turned-off, the output voltage is measured to be -U/2 V
[Rasmussen et al, 2010] .
Moreover, an inverter could be defined as a voltage source inverter which means that
it could be seen as an AC voltage source connected to the grid with an impedance placed in
between, figure 1.4 .
Figure 1.4: Representation of a Voltage Source Inverter
In figure 1.5 the inverter's current compared with the grid voltage as a function of the
phase and amplitude of the inverter voltage UC is described. Additionally, the four different
17 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 modes of an inverter wherein active and reactive power is exchanged are depicted. The
relationship between grid's and converter's voltage is of significant importance and the
phase difference between them is described by the angle “δ”.
Figure1.5: Vector diagram of a Voltage Source Inverter [Rasmussen et al, 2010]
When the inverter's voltage is in phase with the grid voltage, δ=0º, then the
inverter's current is either leading, capacitive mode, or lagging, inductive mode, to the grid
voltage. The latter is defined based on the amplitude of the two voltages. During inductive
mode the grid voltage amplitude is greater than inverter's voltage and thus consumption of
reactive power is performed. On the contrary, in capacitive mode the grid voltage amplitude
is less than inverter's voltage and emission of reactive power is implemented. Additionally,
in both conditions no active power is exchanged between the grid and the inverter which is
known as the stationary or lossless condition.
Furthermore, when the grid voltage is in phase difference with the inverter's voltage,
δ≠0º, then active power is also exchanged. This active power is used to cover the losses
in the inverter. Under phase difference between the two voltages one could see that when
the grid voltage is larger active power is consumed by the inverter whilst when the inverter's
18 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 voltage is larger then inverter emits active power to the grid.
To date within the electronics industry a various number of inverter topologies has
been developed. The several topologies can be divided into groups using as main criterion
the total number of voltage output levels. In general base, inverters can be discriminated in
two level, three level and multi-level topologies. As it has been already mentioned the
subject of investigation in this thesis is a diode clamped three level inverter.
1.4 Asymmetrical Inverter Leg
Through the previous sub-clause power converters and their building block, the
inverter leg, were introduced. An inverter leg can be either symmetrical or asymmetrical.
The main objective of this Thesis is the analysis of the diode clamped three level inverter.
The operation of such an inverter is based on the asymmetrical inverter leg and its
equivalent circuit can be seen in figure 1.6 which is taken by the lecture book of High Power
Electronics in DTU [Rasmussen et al, 2010] .
Figure 1.6: Equivalent of an Asymmetrical Inverter Leg [Rasmussen et al, 2010]
More specifically, the above figure depicts an asymmetrical inverter leg equipped with a
19 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 number of snubber components. These components are used in order to ensure a smooth
operation during turn-on and turn-off of the switches. As it was previously mentioned the
operation of the DCTLI is based on the asymmetrical inverter leg and by comparing the
above figure to figure I1 , it is deduced that, to all intents the DCTLI is compromised by two
asymmetrical nature inverter legs where each has been ''shielded'' by a corresponding
snubber circuit respectively. Such an inverter leg type, can be effectively designed using the
software called Asymdim. It is also facilitate the design process of it where, identification of
the snubber components has to be implemented.
The reason of using Asymdim software was the evaluation of the appropriate turn-on and
turn-off times that in turn would yield low energy losses through the snubber resistor. A
more analytical description regarding Asymdim can be found further in this project.
Using an Asymmetrical type of inverter several IGBT modules can be connected in
series, which means operation at higher voltages, since the snubber inductor is not
connected between the IGBT modules. The latter fact is not valid for a symmetrical type of
inverter since the inductor has to be split up in two parts between the two IGBT modules.
This gives a significant disadvantage when IGBT modules, that contain more than one IGBT
units, are used [Rasmussen et al, 2010] .
1.5 Diode Clamped Three Level Inverter
The diode clamped three level inverter system will be analyzed in this Master Thesis.
The circuit to be investigated theoretically and experimentally is the one depicted in figure
I1 .
This type of inverter corresponds to a three level topology which means that the output
voltage from one inverter leg, measured using the DC midpoint, M, as a reference, can get
three different values, a positive voltage, +UDC, a negative voltage, -UDC and a zero voltage
or state. The single phase equivalent circuit of the diode clamped three level inverter can be
found in figure I1, where only the one inverter leg is depicted. Below in figure 1.7 a three
phase diode clamped inverter is depicted where no snubber circuit is included [Rasmussen et
al, 2010] .
20 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 Figure 1.7: Three phase diode clamped inverter system connected to power grid [Rasmussen
et al, 2010]
This type of inverter was designed in order to overcome the problem caused by the
voltage limitation of an IGBT switch which currently reaches a maximum voltage level of
6.5kV with a maximum current of 600A. Using the above topology several IGBTs can be
connected in series and thus the inverter legs can be used at higher DC and AC voltages
and thus larger amount of power is exchanged with the power grid [Rasmussen et al, 2010] .
The inverter is named as «diode clamped», which is derived from the two clamped
diodes, Dcl1 and Dcl2, that exist in the single phase circuit of the inverter, figure I1 . These
diodes are connected to the reference point of the circuit, M midpoint, in order to ensure
that no overvoltages, comparing to the DC voltage, will be developed across the IGBTs.
Alternatively one could say that the diodes are used as voltage regulators and thereby clamp
the voltage across a switch to the DC voltage. In order to fulfill the latter clamped diodes of
low forward voltage drop and very fast switching action, comparing to the IGBTs, should be
selected [Rasmussen et al, 2010] .
What is more, regarding the single phase circuit, the inverter leg is equipped with four
IGBTs, S1 to S4, connected in series and two DC capacitors, C1 and C2, representing the DC
source of the inverter. Each arm of the inverter, positive and negative arm, is equipped by
21 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 one snubber circuit which aims to improve the efficiency of the inverter. At last, a resistor is
also connected between the two clamped diodes and its use had to be investigated. This
resistor is known as clamped resistor, Rcl.
The pulse pattern of a three level inverter is presented in figure 1.8 . This type of
inverter
Figure 1.8: Pulse pattern of a three level inverter [Rasmussen et al, 2010]
Using figure 1.9 the principle of operation of the inverter can be clearly elucidated.
Having two different current directions, positive and negative, and three different output
voltages it is deduced that six current paths are available [Rasmussen et al, 2010] .
Figure 1.9: Current paths diagram of the diode clamped inverter the states of the IGBTs
In the above figure the current path depends on the state of each switch of the inverter.
Below the current path is further explained for both current directions, positive and negative
where, the components names are based on figure I1 .
Positive Current direction:
A. When the switches, S1 and S2 are turned-on the current is flowing through the freewheeling diodes, DFR_S1 and DFR_S2, and reaches the positive side of the capacitor.
22 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 The measured output voltage is +UDC.
B. When the two middle switches, S2 and S3, are turned on, current initially flows
through the collector of the lower switch, S3, and eventually through the lower
clamped diode, Dcl2, reaches the DC midpoint. The measured output voltage is 0.
C. When the two lower switches, S3 and S4, are turned on current flows through the
collectors of the two IGBTS and eventually reaches the negative plate of the
capacitor C2. The latter yields a voltage output -UDC.
Negative Current direction:
D. When the two upper switches, S1 and S2, are turned on, the current originates from
the upper capacitor, C1, and flows through the collectors of the IGBTs towards the
output. The latter gives a positive DC voltage, +UDC.
E. In this state, the two middle switches, S2 and S3, are turned on and the current runs
from the DC midpoint through the upper clamped diode, Dcl1, and through the
collector of S2 to the output. The measured output voltage is 0.
F. In this state the two lower switches, are turned on. The current runs through the
free-wheeling diodes of, S3 and S4, to the output and the measured voltage is
negative, -UDC.
From the above analysis it is deduced that the various state sequences of the switches
yield a specific output voltage independently of current direction.
1.6 Undeland Snubber Circuit
In figure 1.10 the single phase equivalent circuit of the three level diode clamped
inverter is reintroduced where two parts of it have been highlighted, red dotted line, with
the intention to clearly indicate the two snubber circuits that are used for protection
purposes. Power semiconductors constitute the heart of power electronics equipment. In
simple words «snubbers» are circuits placed across semiconductor devices for protection
and to improve performance [Severns, 2005] .
Among various snubbers two snubber circuits are most well-known for applications in
23 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 power inverters. These are the Undeland and the McMurray snubber circuits [Rashid, 2007] .
The snubber circuit in figure 1.10 makes use of a passive ''Undeland Snubber'' as basic
snubber unit.
Figure 1.10: Disaggregation of the Undeland snubber circuits
Generally speaking, in electronic circuits snubbers offer the following [Severns, 2005] :
 Reduce or eliminate voltage or current spikes
 limitation of di/dt and du/dt
 Transfer power dissipation from the switch to a resistor or a useful load
 Reduce total switching losses
The Undeland snubber is an asymmetrical snubber circuit with one turn-on inductor,
Ls, and one turn-off capacitor, Cs [Rashid, 2007] . The latter capacitor is used for du/dt
limitation during turn-off of the IGBT whilst the inductor is needed for di/dt limitation
24 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 during the turn-on process. The capacitor C0 is used for overvoltage clamping and snubber
energy recovery while the resistor Rs acts as a discharging resistor
which resets the
snubber capacitor and inductor. What is more snubber diodes are also used. The snubber
resistor is not directly involved in snubbing action and thus mechanical arrangements of
components and cooling are much easier and simpler. Furthermore, thanks to the capability
of clamping overvoltage at turn-off and the no unbalance problem of overvoltage this
snubber circuit, Undeland, is appointed as a good candidate for multilevel inverters [InDong et al, 1998] .
It's usefulness will be further analyzed in Chapters 3 and 4 where
theoretical and experimental investigation have been implemented respectively.
Considering the snubber circuit of figure 1.10 and according to [Rasmussen et al,
2010]
the aforementioned snubber components had to be determined carefully and correctly
so that the following critical values would not exceeded :
 The maximum value of the current in each IGBT
 Maximum value of the voltage across the IGBT's during switch-on
 Maximum value of the voltage across the IGBT's during switch-off,
 Maximum value of duCs/dt for the capacitor voltage uCs
 Maximum value of duC0/dt for the capacitor voltage uC0
 Maximum value of duSW/dt for the voltage across the switches
The determination process of the whole snubber circuit was implemented using the
computer aided software called “Asymdim” and it has been analyzed in Chapter 2 of this
thesis.
1.7 Modulation Of Diode Clamped Three Level Inverter
In section §1.5 , it was presented that the output voltage of the DCTLI is a square
shape waveform. Generally speaking, the voltage output of an inverter is no free of
disturbances since it includes all the odd harmonics. However, this square-shaped waveform
of inverters, multi-level inverters present several steps at different voltage levels, can be
used for harmonics elimination. Fourier analysis states that a periodic signal can always be
25 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 represented as a sum of sinusoids and cosines signals and it contains only odd harmonics
such as, 3rd, 5th, 7th, etc. [Perreault, 2007] . The peak voltages of these harmonics can be
calculated using the following equation [Rasmussen et al, 2010] :
U n=
4⋅U DC
2⋅n⋅π
(1.4)
Where,
Un: Amplitude of harmonic voltage
n: The number of harmonic
UDC: DC voltage of the inverter
Harmonic elimination techniques are usually employed when the lowest harmonics have
to be removed, since they constitute a more cost-effective solution. Filtering is much more
practical at high frequencies where filter components can be much smaller and costeffective. The lower harmonics constitute the ones that exhibit high amplitudes and thus
filters of low cut frequency are often employed with the intention of eliminating them. Some
of the modulation strategies or elimination techniques are listed below [Rasmussen et al,
2010] :
I. Fixed Pulse Pattern with elimination of specific harmonics
II. Pulse Width Modulation, PWM, for low switching frequencies, f ≤ 400Hz
III. PWM with high switching frequency, f ≥ 2kHz
IV. Space Vector Modulation, SVM, for switching frequencies above 2kHz
Following the fixed pulse pattern modulation strategy, the three levels of the inverter's
pulse pattern, figure 1.8 §1.5 , give in total one angle, α1, which can be used to eliminate
one harmonic. In consultation with Tonny W. Rasmussen it was decided to perform the
calculations for eliminating the third harmonic. The peak amplitudes of the odd harmonics
can be calculated using the below equation:
b n=
4
⋅(1−2⋅cos(n⋅α 1 )+2⋅cos (n⋅α 2))−......−2⋅(cos (n⋅α m −1)+2⋅cos( n⋅α m))
2⋅n⋅π
26 of 149 Diode Clamped Three Level Inverter MSc Thesis ­ Spring 2011 (1.5)
Where,
α1 to αm: The angles of extra shifts on the pulse pattern
bn: The peak value of the nth harmonic
In the case of the three level inverter the above equation had to be modified since
elimination of only one harmonic had to be accomplished:
b n=
4
⋅(cos ( n⋅α 1 ))
2⋅n⋅π
(1.6)
Thus the switching angle was then calculated as it follows,
4
⋅cos (3⋅α 1 )⇒
2⋅3⋅π
4
0=
⋅cos (3⋅α 1 )⇒
2⋅3⋅π
b 3=
π
α 1= ⇒α=30 ˚
6
Switching at this angle can be used for eliminating the third harmonic. During the
experimental analysis of the inverter this value had to be considered. Regarding the
pragmatic model this value corresponds to a specific time in which the switch should be
implemented. The definition of this time was based on the switching frequency used for the
model and more details can be found in Chapter 4.
27 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 CHAPTER 2
Introduction
The intention of this chapter is to allocate all the electrical and electronic components
of the DCTLI, figure I1 . In other words, this chapter aims to theoretically design the
inverter system. One can say, that this part of the project its of significant importance since
the theoretical and experimental investigations are based on this preliminary design. Several
aspects, such as the determination of the snubber circuit, calculation of mean and RMS
current values in order to choose the appropriate types of components and thermal design of
the devices will be covered through this part. It was known that a possible inappropriate
theoretical design would have a great impact in the farther analysis of the inverter.
2.1 Components Selection Criteria
The intention of this chapter was to identify the several electronic and electrical
components of the inverter system. Thus, this procedure involved the need of setting the
appropriate selection criteria. The power electronics market has been evolved through the
decades covering a wide range of electronic devices that they can handle voltages and
currents in kVs and kAs respectively, and operate with fast switching speeds from a few tens
of ns to a few μs.
The basic criteria used when selecting of power components is need are listed below
[Mohan, 2007] :
1. Blocking voltage capability: The maximum instantaneous voltage that the device
should be able to block when is turned-off. If this value is exceeded an irreversible
damage occurs.
2. Nominal Current: The maximum allowable current which would flow through the
device when is turned-on. In the data-sheet of the components current is expressed
as instantaneous, RMS and average. If this value is exceeded then heat is also
28 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 increased which in turns can destroy the component.
3. Switching Speed: The speed which defines the time that it takes for an electronic
component to complete the transition from turn-on to turn-off or vice-versa. The
switching losses of a switch depend on the this parameter. Fast devices yield less
losses.
2.2 Calculation Of Snubber Circuit Components
The determination of characteristics of the various power components and electronic
switches of the clamped diode three level inverter, figure I1 , constitutes the intention of this
part. Primarily the investigation was focused on the determination of the Undeland snubber
circuit, §1.6; . More precisely, estimation of the Undeland snubber circuit was achieved in
two parts. Initially, the values of snubber inductor, L, snubber capacitor, C0, and all the
necessary input data were determined as required in Asymdim software. Thereafter, the rest
of the snubber circuit was specified by using the software. After the snubber circuit had
been designed the rest of the components, diodes and switches, incorporated by the diode
clamped three level inverter leg were determined by calculating their maximum currents and
voltages.
At this point it should be noted that since the value size of the components of either
the upper or the lower snubber circuit would be the same the calculation process was
confined only in the upper snubber circuit.
2.2.1 Asymdim
The computer aided software Asymdim, designed for Microsoft Windows operating
systems, it was invested in the Electrical Power Engineering department of DTU, Technical
University Of Denmark, and constitutes an essential tool in designation of an asymmetrical
inverter leg. The intention of using Asymdim software was the estimation of snubber circuit
components, getting an idea of energy losses in the snubber resistors, RS, and the evaluation
29 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 of that switching sequence duration of the snubber circuit which would yield the smaller
losses across the resistors.
The program required as input parameters several factors. Some were known from
project description and others had to be determined during the snubber circuit
determination. Since all the input parameters were known the program could then calculate
the boundaries that defined an enclosed space where solutions were useful for the critical
values, Chapter 1 . This space is often called a “solution space”. Within the solution space
other properties so called value criteria could be decided. The borders were calculated with
L and C0 as parameters and were illustrated in a Cs-R diagram. As it was mentioned above,
using Asymdim the switch-on and switch-off times of the snubber circuit could be also
obtained. That is, for a chosen point within the solution space, the program yielded
information about the duration of the switching sequences. A satisfactory solution was
obtained when the following two criteria were fulfilled [Rasmussen et al, 2010] :
➢ Short switching times
➢ Minimum energy losses on the resistor, WR
At this point it should be noted that within the Cs-R diagram a dotted line was
expected to be displayed. The dotted line was indicate the places where:
R=
√
L
C 0+C S
(2.1)
and according to [Rasmussen et al, 2010] solution points near this line would empirically give
relatively short switching sequences and thus, candidate solution points. Various input
parameters were required to use the software. These parameters have been classified in
table 2.1
below.
30 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 ASYMDIM Input Parameters
UC: DC Supply Voltage
IL: Peak Load Current
Ls: Value of Inductance
C0: Value of the overvoltage capacitor
IMAX: Maximum Current through the IGBT
UMAX: Maximum blocking voltage of the IGBT
Ir: Reverse recovery current of the free-wheeling diode
dUCs/dt: Rate of change of voltage across capacitor CS
dUC0/dt: Rate of change of voltage across capacitor C0
dUSW/dt: Rate of change of voltage across each IGBT
Table 2.1: Input parameters required by ASYMDIM software
2.2.2 Data Classification
Prior to the calculation procedure of the Asymdim input data, a classification of the
known parameters was implemented. From thesis description it was known that the switching
part of the inverter leg would consist of two separate “2MBI150U2A-060 , 600V 150A”,
IGBT modules. The DC voltage supply of the inverter equals ±400V while the peak load
current was 42,5 A. The root mean square value of the current was then determined as it
follows:
I RMS =
I peak
⇒ I RMS=30A
√2
(2.2)
In the table below the maximum values of turn-on, tr, and turn-off, tf, times are
depicted. What is more, the maximum voltage that each IGBT module can handle equals
600V and the maximum continuous collector current equals 150A. Using the data-sheet of
the module and the data from project description all the necessary values needed for the
calculation process of the snubber circuit were classified in table 2.2 .
31 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Data Classification
Supply Voltage, UC:
RMS value of Load Current, IRMS:
±400 V
30 A
Rise time for current in the IGBT, tr:
0,60 μS
Fall time for current in the IGBT, tf:
0,45 μS
IGBT Maximum Current, IMAX:
300 A
IGBT Maximum Voltage, UMAX:
600 V
Collector Current, IC:
150 A
Peak value of Load Current ILoad:
42,5 A
Table 2.2: Data classification using known parameters from project's description and datasheet of IGBT modules.
Comparing the above table with the one introduced in the previous sub-clause,
§2.2.1 ,
it is obvious that some of the input parameters that Asymdim software required
were known from the project description.
2.2.3 Calculation Of Inductance
In the Undeland snubber circuits the inductors are used to reduce the turn-on losses in the
IGBTs near to zero value. That is, when the IGBT switch-on the whole voltage drop is
placed across the the inductance. Additionally, the use of the inductor makes the control of
rate of change of current, di/dt, feasible. The larger the inductance the slower is the rate of
change of current. The voltage across the upper inductor, Ls1, is given by:
U Ls1 =L s1⋅
di S1
dt
(2.3)
Using the data-sheet of the IGBT it was obtained that maximum rise time of the current
should not exceed 0,60 μS. Thus, an inductor which would fulfill the latter condition had to
be determined and this was done revising the above equation:
L s1=
U⋅t r
IC
(2.4)
Then, by substituting in the above equation:
32 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 L s1 =
U⋅t r
400V⋅0.60μS
⇒ Ls1=
⇒
IC
150A
L s1=1.6μH
The above result corresponds to the minimum possible which the inductor could get
and additionally fulfills the requirement of the current rise time in the IGBT. This minimum
value was primarily decided to be used through the rest design process of the snubber
circuit. An inverter of low inductance, which means high di/dt, avoid voltage stress on the
components during the switching sequences and consequently reduces the power loss in the
system. Thus, a low inductance inverter is always desirable. If the chosen value of the
inductance could not yield a satisfactory solution space using Asymdim, a larger value had to
be considered.
2.2.4 Computation Of Diode Characteristics
In figure I1 , it can be seen that each IGBT is equipped with an anti-parallel freewheeling diode which is the same for all of the switches. As a next step in the calculation
process of Asymdim input data, the characteristics of the free-wheeling diode had to be
determined using information provided by the data-sheet of the IGBT.
Primarily, the rate of change of current could be determined using the maximum
current rise time and the collector current, table 2.2 . Since the latter parameters were
known, using the following equation the di/dt of the IGBT was calculated:
di 150A
di
=
⇒ =250μS
dt 0.60μS dt
(2.5)
According to [Rasmussen et al, 2010] the reverse recovery current of the diode could
be determined using equation 2.6 .
√
di
I r= 2⋅Q r⋅∣ ∣
dt
(2.6)
Where,
Ir: Reverse recovery current of the free-wheeling diode
Qr: Reverse recovery charge of the free-wheeling diode
33 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 di/dt: Change of rate of current of the IGBT
Equation 2.6
could not be used since the data-sheet of the IGBT were not providing
information about reverse recovery charge, Qr, of the diode. Alternatively, in the data-sheet
of the IGBT the value for the reverse recovery current, Ir, could be determined indirectly
using figure 2.1 .
Figure 2.1: Diode reverse recovery current as a function of forward current [Data-sheets]
The above figure determines the reverse recovery current for a given forward current
at temperature conditions of 125ºC and 25ºC. For a forward current of 42,5A, peak value of
load current, Ir corresponds to approximately 50A:
I r=50A
Thereafter, the reverse recovery charge had to be estimated by solving equation 2.6
34 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 for Qr. Substituting all the known parameters the following was obtained:
(I r )2
(50A) 2
Qr =
⇒ Qr =
2⋅di / dt
500 A/ μS
(2.7)
Qr =5 μC
The lifetime of the diode was afterwards computed as it follows:
τ=
Qr
5μC
⇒τ=
I Load
42,5 A
(2.8)
τ =0.12 μS
Moreover, at this point it had to be verified that the maximum current in the IGBT is
greater than the sum of the reverse current and load current [Rasmussen et al, 2010] :
I MAX >I r+I Load
(2.9)
Where,
Ir: Reverse recovery current of the free-wheeling diode
IMAX: Maximum allowable current through the IGBT
ILoad: Peak value of the load current
If the above condition was not fulfilled then a modification of the value of the inductor
would have to be implemented. Table ;; indicates that the maximum allowable current
through the IGBT equals 300A which is larger comparing the sum of Ir and Iload and thus no
modification of the inductor was needed:
300A>50A+42,5 A
2.2.5 Estimation of Capacitor (C0)
Proceeding further in the calculation process of the Asymdim parameters the value of
overvoltage clamping capacitor, C0, had to be calculated. According to [Rasmussen et al
2010, Appendix 2.4]
Ir
the range of values of the capacitor is given by equation 2.10 .
2
I −I
⩽C 0⩽ MAX Load ⋅L
duC 0 /dt
U MAX −U C
(
)
(2.10)
In the above equation the only unknown parameter was the rate of change of voltage across
35 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 C0. Primarily, regarding the value of the capacitor, a choice based on assumption had to be
made using the data-sheet of the polypropylene (PP) capacitors, offered by the electronic
components company “WIMA”, as a reference. A du/dt of 56kV/μS was chosen as a first
step. According to WIMA data-sheet this value of du/dt corresponded to capacitors within
a range of 100pF to 600pF. Using equation 2.10 the following results were obtained:
Ir
50A
≤C 0 ⇒
⇒0,9 nF ≤C0
duco /dt
56 kV / μsec
(
C 0≤
I MAX −I Load 2
300A −42,5 A 2
⋅L⇒ C0 ≤
⋅1,6 μH ⇒C 0≤2,65 μF
U max−U L
600−400
)
(
)
900 pF ≤C 0 ≤2.65 μF
Capacitors within the above range cannot offer a du/dt of 56kV/μS. Thereby, the
range of the values for C0 was recalculated using a du/dt equals to 51kV/μS and the
results can be found below.
•
I rr
50A
≤C 0 ⇒
⇒ 0,98 nF≤C 0
duco /dt
51 kV /μsec
•
I −I
300A−42,5 A
C 0≤ MAX L ⋅L ⇒C 0≤
⋅1,6 μH ⇒ C0 ≤2,65 μF
U max −U L
600−400

2


2

Thus, the range of possible values for the capacitor C0 is:
980 pF≤C 0≤2,65 μF
According to WIMA data-sheet, capacitors within the above range of values could
offer the chosen du/dt and thus, as a next step a specific value of capacitor C0 which would
yield a satisfactory solution space in Asymdim had to be determined. The following
parameters were considered as the capacitor selection criteria:
➢ Availability characteristics of the components in the semiconductors market.
➢ du/dt characteristic of each capacitor, higher du/dt was preferable
➢ Rated voltages of the given capacitors in data-sheet
Prior to the final estimation of C0 the rest of the input parameters that Asymdim
software required had to be defined since the latter could be used to inspect the extend of
accuracy of C0 value. Apart of C0 and its corresponding duC0/dt the missing parameters were
36 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 the duSW/dt and duCs/dt. The rate of change of voltage across the switches was set to a
large value of 51000 kV/μS since new developed switches offer no du/dt limitations. The
value of duCs/dt was primarily set based on assumption since the size of this capacitor was
still unknown. Thus, the maximum rate of change of voltage that a polypropylene capacitor
could give, 56kV/μS was chosen. This was decided based on the circuit position of CS
(connected across the switch for du/dt limitation).
Proceeding further to C0 estimation, initially capacitors with high du/dt were selected.
That is to say,
 C0 = 1nF
 duC0/dt = 51kV/μS.
The first simulation in Asymdim was implemented using the above values in
conjunction with the calculated parameters that table 2.1 in §2.2.1 indicates. This attempt
yielded no solution space and thus modification of capacitor's value had to be accomplished.
Several simulations were performed moving from capacitors of large du/dt towards
capacitors of smaller du/dt.. Eventually, it was obtained that a good solution space was
derived when large capacitors within the range of 0.033μF to 0.068μF were used. These
capacitors were rated with a maximum du/dt of 11kV/μS. Thereby a capacitor equals to
0,068μF was selected. The input parameters that yielded the satisfactory solution space
are indicated in table 2.3 .
Asymdim Input Parameters
U=400V
C0=0,068μF
Ir=50A
IL=42,5A
UMAX=600V
L=1,6μH
IMAX=300A
duCS/dt=56 kV/μS
duCO/dt=51 kV/μS
duSW/dt=51000 kV/μS
Table 2.3: Asymdim input parameters that yield a solution space
2.2.6 Estimation of R S And C S
In sub-clauses 2.2.2 through 2.2.5 the input parameters of Asymdim were determined
with the aim to estimate the snubber resistor, Rs, and snubber capacitor, Cs. Thereby, the
37 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 solution space, Cs-R diagram, which was obtained using table 2.3 can be seen in figure 2.2 .
Within the diagram the solution space is represented by the no-dotted area. At this point it
should be reminded that using the solution space the values of snubber capacitor, Cs, and
snubber resistor, R, could be determined. Additionally, the dotted line, mentioned in
§2.2.1 ,
is also included within the derived solution space. It was known that a solution point
close to this line would yield short switching times and less energy losses in the resistor
[Rasmussen et al, 2010] .
Eventually, a solution point, close to the dotted line, was selected
and the following values were obtained:
 Cs = 1nF
 R = 5Ω
The corresponding, on the above combination of values, switching sequences of the
upper IGBT module are depicted in figure 2.3 . Comparing to other solutions, obtained by
selecting different points within the solution space, a satisfactory short switching time was
obtained when the above mentioned values were chosen.
However, as a next step the solution space had to be re-estimated using the
appropriate du/dt for CS according to the data-sheet of the polypropylene (PP) capacitors.
For the second run in Asymdim the input parameters that table 2.3 indicates were re-used
including the new value of duCS/dt, which was equal to 51kV/μS.
The new solution space can be found in figure 2.4 . By comparison of figures 2.2 and
2.4
it was observed that slight difference occurred regarding the size of the solution space.
Figure 2.4
presents a more shrink no-dotted area since the du/dt of CS capacitor was
reduced. Within the “new” solution space the pair of values of CS and R which was selected
previously was again constituted a good solution. Thus, the same values were selected and
by double clicking on this point the switching sequences were obtained and they can be
found in figure 2.5 .
More specifically and based on figure 2.5 , the total duration of a switching sequence,
turn-on and turn-off, was equal to 2,30μS. What is more, the energy loss in the resistor
was kept at minimum compared to other solution points, WR = 6,96mJ.
38 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 In figure 2.5 the two upper graphs show the duration of the switch-on and switch-off
sequences. The two lower graphs depict the voltage, across the snubber capacitors, and
current, through the circuit, variation for each state of the two switches, S 1 and S2, figure
I1 .
39 of 149 Figure 2.2: Solution space obtained using Asymdim and the input parameters of table2.3
Figure 2.3: Duration of switching sequences of one IGBT module obtained using Asymdim
Figure 2.4: Solution space obtained through the second “run” in Asymdim
Figure 2.5: Duration of switching sequences of one IGBT module obtained through second “run” in Asymdim
CHAPTER 2 MSc Thesis ­ Spring 2011 Table 2.4
summarizes the values of the snubber circuit components that were obtained
through this section of the project. These components will constitute the snubber circuit
during the theoretical and experimental investigation of the inverter.
Snubber Circuit Characteristics
Snubber Inductor, Ls1:
1,6μH
Snubber Inductor, Ls2:
1,6μH
Snubber Capacitor, C01:
0,068μF
Snubber Capacitor, C02:
0,068μF
Snubber Capacitor, CS1:
1nF
Snubber Capacitor, CS2:
1nF
Snubber Resistor, RS1:
5Ω
Snubber Resistor, RS2:
5Ω
Table 2.4: Summarization of the characteristics of the Snubber circuit components that were
determined using Asymdim software.
Additional information regarding the snubber inductor can be found in Chapter 4
where, its construction process have been introduced. All the snubber capacitors were
provided by “WIMA” and their nominal DC voltage was equal to 2000VDC. Two parallel
10Ω TO-220, 50W, power resistors were chosen as the snubber resistor of the circuit.
More information regarding the choice of the snubber resistor has been given in Chapter 3 .
2.3 Calculation Of Semiconductors Characteristics
Through the previous sub-clause all the snubber components but the snubber diode
were determined using Asymdim software. In this sub-clause focus was given on the
determination of the following semiconductors components:
•
Snubber Diodes, D1 to D4
•
Clamped Diodes, Dcl1 and Dcl2
•
IGBT switches
44 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 From the introduction of this Master Thesis it was known that the inverter would make
use of two “2MBI150U2A-060 , 600V 150A”, IGBT modules. Thus, most of the design
parameters, necessary for performing the investigation, such as load current and inverter's
DC voltage were defined based on the characteristics of the IGBT module, table 2.2 .
However, an analysis of the mean and RMS current values through the IGBTs was
introduced for explication reasons but mainly because these values were needed for the
thermal design process of the latter.
Furthermore, this section aims to allocate an appropriate diode type for the snubber
and clamped diodes and to determine if heat sinks are required. Once the aforementioned
semiconductors were determined the whole diode clamped inverter would have been
estimated. This would allow the theoretical, P-Spice, and experimental, laboratory,
investigation of the inverter's behavior.
The blocking voltage capability and the current limitation constituted the main criteria
to select the semiconductor components. Figure 2.6 depicts the pulse pattern of a three
level inverter in conjunction with the current waveform which flows through each voltage
level. As it can be seen, the inverter is in capacitive mode which means that the current
leads the converter voltage by 90°, and thus, the inverter emits reactive power to the
load.
Figure 2.6: Current flowing into each voltage level when the current is 90° leading the
inverter voltage
The switching angle α1 is also depicted in the above figure. This angle was used to
eliminate one harmonic, the third voltage harmonic.
Using the above figure and figure 1.9 , which depicts the current path through the
45 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 inverter based on the state of the switches, the mean and RMS current values of each
semiconductor were calculated using the following equations
2π
1
I AV =
⋅∫ î⋅cos( x) dx
2⋅π 0
√
(2.11)
2π
1
I RMS =
⋅∫ (î⋅cosx)2 dx
2⋅π 0
(2.12)
Knowing the latter parameters the current limitations were determined. The voltage
limitation was restrained by the DC voltage of each inverter arm, 400V. As it will be seen
the mean and RMS values of the current were also used further in this project, heat sink
analysis. Therefore, in the following sub-clauses the current determination is presented for
each semiconductor separately.
2.3.1 Clamped Diode
The intention of this sub-clause was the selection of an appropriate diode type for Dcl1 and
Dcl2 based on the current and voltage limitations. In order to achieve that purpose figure 2.6
was used. This figure depicts the pulse pattern and the current of the DCTLI. It can be seen
how the current is flowing into each output voltage level for a whole period, 0 to 2π
radians.
In section Chapter 1 , it was yielded that Dcl1 conducts when the current is negative
and switches S2 and S3 are turned-on, which in turns produces a zero output voltage.
Similarly, Dcl2 conducts under the aforementioned switching conditions but when current is
positive. The latter is graphically depicted in figures 2.7a and 2.7b respectively, where the
conduction time intervals of Dcl1 and Dcl2 represented by the bold red sections. That is, the
values of the mean and RMS currents for both diodes had to be estimated at this state of the
system. As it can be seen, during the conduction of the clamp diodes the current reaches its
peak value.
46 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 a)
b)
Figure2.7: Conduction time interval of a) clamp diode one and b) clamp diode two
In figure 2.7a the conduction occurs at the interval between “π-α1” and “π+α1”
in which the mean and RMS value of the current had to be calculated. The calculation of the
current values was confined only for the case of the clamp diode one. Therefore, using
and 2.12 the unknown values were determined as it follows:
equations 2.11
2π
π +α1
1
1
I AV =
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos( x)dx
2⋅π 0
2⋅π π −α1
I AV =6,764 A
√
2π
√
π+α1
1
1
I RMS =
⋅∫ (î⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ ( 42,5 A⋅cosx)2 dx
2⋅π 0
2⋅π π−α1
I RMS =16,58 A
The criteria used in the selection of an appropriate diode type are listed below:
I. Maximum voltage across the clamp diode, 400 V
II. RMS value of the current, 16,58 A
47 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 III. trr switching speed. A diode of higher speed than the IGBTs was required to ensure
that the voltage across the IGBT does not get bigger than the DC voltage supply.
The ultrafast diode “RURG5060”
provided by FAIRCHILD semiconductor was
selected to be used for the clamping purposes of the inverter. Switching speed from nonconducting to conducting mode is at 65ns. This diode is able to block a maximum voltage of
600V and to conduct a maximum forward current of 50A.
2.3.2 IGBT Module
Eventhough, the type of the IGBT module was known the mean and RMS values of the
current through its units had to be determined since they were needed throughout the
thermal design process for the estimation of the conducting losses. Thus, in this sub-clause
an analysis of the module's current limitation based on theoretical terms was implemented.
Figures 2.8a
through figure 2.8d aim to give a clear picture of how the current flows
through the four IGBT units within a full period. Using the current flow analysis which was
implemented in Chapter 1 , in combination with the following figures the maximum currents
that would flow through the devices of an IGBT module could be estimated. As it can be
seen in main figure, figure I1 , the upper and lower modules contain S1, S2 and S3, S4 IGBT
units respectively. In this section the goal was to estimate the current loading of the IGBT
units that were incorporated in the same house of an IGBT module which means, considering
of the switches as a module. The distribution of the current in the two IGBT modules was
symmetrical and thus the analysis was confined in the upper one.
A. Positive Current and Positive Voltage Output
In this case the current flows through the free-wheeling diodes of the IGBT unit and it
is depicted in figure 2.8a . As it can be seen, the conduction interval is from “α1” to
“π/2”. The current values was then calculated as it follows:
2π
I AV =
π/2
1
1
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅∫ 42,5⋅cos (x )dx
2⋅π 0
2⋅π α1
48 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 I AV =3,382 A
√
2π
√
π/2
1
1
I RMS =
⋅∫ (i peak⋅cosx)2 dx ⇒ I RMS =
⋅∫ (42,5⋅cosx)2 dx
2⋅π 0
2⋅π α1
I RMS =9,936 A
B. Negative Current and Positive Voltage Output
During this state of the circuit, the current flows through the switches of the IGBT
units, S1 and S2, figure 2.8b . In this case the conduction interval is from “π/2” to “πα1”.Similarly, to the previous case the current values were calculated as it follows:
2π
I AV =
π −α1
1
1
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos( x)dx
2⋅π 0
2⋅π π /2
I AV =3,382 A
I RMS =
√
2π
√
π −α1
1
1
⋅∫ (i ⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ ( 42,5⋅cosx)2 dx
2⋅π 0 peak
2⋅π π /2
I RMS =9,396 A
49 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 a)
b)
c)
d)
Figure 2.8: Current flowing indication through IGBT modules when a) S 1 and S 2 are turnedon and current is positive b) S 1 and S 2 are turned-on and current is negative c) S 2 and S 3 are
turned-on and current is negative d) Conduction of switch S 2 – most loaded device
50 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 C. Negative Current and Zero Voltage Output
In this case the current follows a path through the IGBT switch, S 2, of the unit. This is
depicted in figure 2.8c and the conduction interval is from “π-α1” to “π+α1”. This
switch carries current for two consecutive states and thus constitutes the most loaded
component of the module. The latter is depicted in figure 2.8d . The calculation of the mean
and RMS values are presented below:
2π
I AV =
π +α1
1
1
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos( x)dx
2⋅π 0
2⋅π π −α1
I AV =6,764 A
I RMS =
√
2π
√
π +α1
1
1
⋅∫ (i ⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ ( 42,5⋅cosx)2 dx
2⋅π 0 peak
2⋅π π −α1
I RMS =16,583 A
The IGBT module “2MBI150U2A-060”offered by “Front runners” constitutes a high
speed switching device which additionally presents a low inductance structure. It can allow
the pass of a maximum continuous current of 150A, and a maximum voltage of 600V can be
applied across its collector-emitter terminals. The equivalent circuit of the module can be
found in figure 2.9 .
Figure 2.9: Equivalent circuit of the IGBT module “2MBI150U2A-060”[Data-sheet of
module]
51 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 2.3.3 Snubber Diodes
The mean and RMS current values through the snubber diodes were determined using
P-Spice software. The calculation was done using the integrals of the current and square
current. What is more, the mean and RMS values were obtained for both current directions
for each diode separately in order to obtain the semiconductor which would conduct the
maximum current. A more detailed description about the inverter's schematic in P-Spice will
presented further in this project, Chapter 3 . Thus, the following were obtained for each of
the four diodes:
Positive Current
➢
Snubber Diode one, D1:
10μs
∫ i D1⋅dt=39,631 μA S
0
IAV= 10 kHz * 39,631 μAS = 0,40 A
10μs
∫ i D12⋅dt=1,3963 mA2S
0
IRMS= 10 kHz * 1,3963 mAS2 = 13,96 A
Snubber Diode Two D2:
10μs
∫ i D2⋅dt =39,646 μAS
0
IAV= 10 kHz * 39,646 μAS = 0,40 A
10μs
∫ i D22⋅dt=1,3842 mA2S
0
IRMS= 25kHz * 1,3842 mAS2 = 13.84 A
Snubber Diode Three, D3:
10μs
∫ i D3⋅dt =22,343 μAS
0
IAV= 10 kHz * 22,343 μAS = 0,22 A
10μs
∫ i D32⋅dt=608,282 μA2S
0
IRMS= 10 kHz * 608,282 μAS2 = 6,08 A
Snubber Diode Three, D4:
10μs
∫ i D4⋅dt=22,341 μAS
0
IAV= 10 kHz * 22,341 μAS = 0,22 A
10μs
∫ i D42⋅dt =630,979 μA2S
0
IRMS= 10 kHz * 630,979 μAS2 = 6,31 A
52 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Negative Current
➢
Snubber Diode one, D1:
10μs
∫ i D1⋅dt=34,102 μAS
0
IAV= 10 kHz * 34,102 μAS = 0,34 A
10μs
∫ i D12⋅dt=1,0349 mA2S
0
IRMS= 10 kHz * 1,0349 mAS2 = 10,35 A
Snubber Diode Two D2:
10μs
∫ i D2⋅dt=34,102 μAS
0
IAV= 10 kHz * 34,102 μAS = 0,34 A
10μs
∫ i D22⋅dt=1,0245 mA2S
0
IRMS= 10 kHz * 1,0245 mAS2 = 10,24 A
Snubber Diode Three, D3:
10μs
∫ i D3⋅dt=17,70 μAS
0
IAV= 10 kHz * 17,70 μAS = 0,18 A
10μs
∫ i D32⋅dt=554,124 μA2S
0
IRMS= 10 kHz * 554,124 μAS2 = 5,54 A
Snubber Diode Three, D4:
10μs
∫ i D4⋅dt=17,314 μAS
0
IAV= 10 kHz * 17,314 μAS = 0,17 A
10μs
∫ i D42⋅dt=537,532 μA2S
0
IRMS= 10 kHz * 537,532 μAS2 = 5,38 A
In order to implement a satisfactory diode selection the worst case had to be
considered. Thus, based on the above calculations the larger current values were chosen to
constitute the current criterion. As it can be observed, the most loaded component was the
snubber diode one, D1, which, for a positive current direction conducted the following
current values:
IAV= 0,40A
IRMS= 13,96A
53 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Thus, the selection of the diode was based on the following criteria:
I.
The maximum developed voltage across the snubber diodes, 400 V
II.
The RMS value of the current, 13,96 A
III.
A fast speed diode was required
The ultrafast “STTH1212” offered by “ST” was selected to be the diode type of the
snubber diodes, four in total. This device can handle an RMS forward current of 30A and it
can withstand the develop of a maximum voltage of 1200V across its cathode and anode
terminals.
2.4 Thermal Design Of Semiconductors
The amount of power dissipated, in the form of heat, in any semiconductor and
magnetic devices must be removed to ambient in order to limit temperature rise in the
device. The latter can be feasible using a heat sink. The reliability of converters and their
life expectancy depend on the operating temperatures and thus, they should be kept well
below the maximum rates of the devices. Nevertheless, when operation under high
temperatures is decided, decrease in cost and size of the heat sinks is succeeded [Mohan,
2007] .
The ability of a heat sink to dissipate heat to the ambient depends on many physical
and geometrical factors that render its determination a complex procedure. However, the
whole phenomena can be represented by a single parameter called the thermal resistance,
RTH. Generally speaking the thermal resistance characterizes the relation between power and
temperature within a semiconductor. It defines how the temperature changes for each watt
of power dissipated and its unit is the K/W or ºC/W. Large thermal resistance makes the
flow of heat through the case of the device more difficult which in turn yields temperature
rise [Iskram, 2010] .
This section aims to investigate the need of thermal protection for the IGBT, snubber
diodes and clamp diodes components that were identified in the previous section, §2.3; . In
54 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 order to achieve this goal, the conduction losses, Pcon, of each semiconductor had to be
calculated by making use of the corresponding mean and RMS current values. Afterwards,
using the calculated losses in conjunction with the thermal equivalent diagram and the datasheets of the components a heat sink, if needed, could be selected. The analysis was
performed for each component separately.
2.4.1 IGBT Module
Prior to determination of an appropriate heat sink for the IGBT module, S1 and S2, the
conducting losses of it had to be determined. This was done by using the following General
Equation of Conducting Losses:
P Con=U T⋅I AV +R D⋅I 2RMS
(2.13)
Additionally, from the data-sheet of the IGBT module the following values were
extracted:
UT: 2,35V
RD: 1,39 mΩ
By substituting the above values in equation 2.13 and in conjunction with the current
values that were obtained through section §2.3 the conducting losses were calculated
separately for each case as it follows:
A. Positive Current and Positive Voltage Output
P Con=U T⋅I AV +R D⋅I 2RMS ⇒
P Con=(2,35 V⋅3,382 A)+(0.00139⋅9,936 A)⇒
P ConS2 =7,96 W
B. Negative Current and Positive Voltage Output
P Con=U T⋅I AV +R D⋅I 2RMS ⇒
P Con=(2,35 V⋅3,382 A)+(0.00139⋅9,936 A)⇒
P ConS1=7,96 W
C. Negative Current and Zero Voltage Output
55 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 P Con=U T⋅I AV +R D⋅I 2RMS ⇒
P Con=(2,35 V⋅6,764 A)+(0.00139⋅16,583 A)⇒
P ConS1=15,9W
UPPER IGBT MODULE (S 1 & S 2 )
Circuit
State
P I1
(Watts)
P I2
(Watts)
P D1
(Watts)
P D2
(Watts)
A.
0
0
7.96
7.96
B.
7,96
7.96
0
0
C. - S2
0
15.9
0
0
Total
7,96
23,86
7,96
7,96
Table 2.5: Conducting loses of the upper IGBT module for each circuit state
The above table summarizes the conducting losses of the upper IGBT module. It can
be seen that larger amount of losses occurred during the third circuit state, negative current
and zero voltage output. As it was explained S 2 conducted current for two consecutive
intervals and thus, its total losses were calculated by adding the conducting power of its
both states.
56 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Figure 2.10: Thermal equivalent diagram which emphasizes on the current flow through the
two IGBT units of the module.
The above figure depicts the thermal equivalent diagram of the upper IGBT module, Figure
I1 .
Using this diagram an appropriate heat sink could be estimated. Elucidation of the
several terms that are incorporated in figure 2.10 can be found below:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PI1: conducting losses of S1
PD: conducting losses DFR_S1
PI2: conducting losses of S2
PD2: conducting losses of DFR_S2
Θa: ambient temperature
ΘjI: temperature of the IGBT junction
ΘjD: temperature of the diode junction
RthH: thermal resistance of the heat sink
RthCH: thermal resistance between the module and the heat sink
Rj-c_I1: thermal resistance between the S1 junction and the house
Rj-c_D1: thermal resistance between the DFR_S1 and the house
Rj-c_I2: thermal resistance between S2 junction and the house
Rj-c_D2: thermal resistance between the DFR_S2 and the house
Ptotal: Total conducting loses
57 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 From the data-sheet of the IGBT module the following values were obtained:
RthI = 0,25 ºC/W
RthD = 0,46 ºC/W
RthCH = 0,05 ºC/W – When a thermal compound is used
ΘjImax = 150 ºC
ΘjDmax = 150 ºC
•
•
•
•
•
Assuming a temperature of Θa = 50 ºC, using equation 2.14 the RthH of the heat-sink
was evaluated:
RthH =
Θ jImax −Θα −( P I1⋅R j−cI1 )−(P D1⋅R j−cD1 )−(P I2⋅R j −cI2 )−( P D2⋅R j−cD2 )−( P total⋅RthCH )
P total
(2.14)
Using table 2.5 the total conducting losses were calculated:
P total= P I1+ P D1+P I2+ P D2 ⇒ P total =47,74 W
All the values required by the thermal equivalent were known and the calculation was
implemented as it follows:
150°C −50°C −( 7.96W⋅0,25
Rth =
−(7.96W⋅0,46
°C
°C
°C
)−(7,96 W⋅0,46
)−(23,86 W⋅0,25
)
W
W
W
47.74W
°C
°C
)−(0,05 ⋅47,74W )
W
W
47.74W
Rth =1,72
°C
W
It was known that the two IGBT modules would have to be mounted on the same heat sink.
Thus, the above value of thermal resistance had to be divided by two, the total number of
the IGBT modules used in the inverter. Thereby, a heat sink which could offer a thermal
resistance of 0,86 ºC/W for each module had to be selected. In the below figure the model of
the chosen heat sink is depicted. The graph on the right determines the thermal resistance
of the heat sink when the width dimensions of it are known. Eventually, the heat sink SK3380 provided by “Fischer Elektronik” of 80mm width was selected which yielded a total R th =
0,75ºC/W (Figure 2.11 ).
58 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Figure 2.11: Selected heat sink model for thermal protection purposes of the IGBT modules
2.4.2 Snubber Diode
According to the data-sheet of this diode, in order to evaluate the losses the following
equation had to be used:
2
P Con=1,5⋅I AV +0,033⋅I RMS
(2.15)
Through the previous section, §2.3; , it was calculated that the maximum current values
corresponded to D1:
IAV= 0,40A
IRMS= 13,96A
Thus,
P Con=1,5⋅0,40 A+0,033⋅13,96 A⇒
P Con ≃1,06 W
In order to determine if a heat sink protection was needed the following thermal
equivalent diagram was used (Figure 2.12 ).
59 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Figure 2.12: Equivalent thermal diagram for the snubber diode “STTH1212”
The above diagram depicts the thermal equivalent of the snubber diode “STTH1212”
and explication of the several symbols can be found below.
PCon: Conduction losses through the body of the diode
Rthj-c: Thermal resistance between the junction and the case of the diode
Rthc-α: Thermal resistance between the junction and the ambient
Θj: Junction temperature
Θα: Ambient temperature
Rthj-α: Thermal resistance between the junction and the ambient
Using the above diagram and the conducting losses, that were just previously
calculated, the goal was to estimate the maximum temperature which would be developed in
the junction of the diode. Afterwards, the obtained temperature value was compared to the
maximum temperature defined in the data-sheet of the component.
The following information were known from the data-sheet:
Tj= 175 ºC
Rthj-c= 1,6 ºC/W
Θα= 25 ºC
What is more, the Rthj-α was also provided indirectly within the data-sheet of the
component. More specifically, “figure 12” in data-sheet depicts the total thermal resistance
from junction to ambient as a function of copper surface, S cu, under the body of the
60 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 component, Appendix A.1 . This graph corresponded to a PCB copper thickness of 35μm, a
number which constitutes a very thin board and thus the worst case was considered. The
PCB which would be used in order to construct the inverter was known that it would be
much thicker than 35μm. Moreover, the surface under the body of the component it was
known, Scu=2,56 cm2 which corresponded to Rthj-α=40 ºC/W.
The left circuit in figure 2.12 represents a conventional heat path to ambient
representation. Since Rthj-α was known the right thermal equivalent circuit of the figure was
used.
The temperature difference equals to the dissipated power multiplied by the thermal
resistance [Iskram, 2010] . Thus, the following were applied:
Θ j −Θ α =P Con⋅Rthj−α ⇒
Θ j =Θ α +P Con⋅R thj−α ⇒
Θ j =25 °C+1.06W⋅40
°C
⇒
W
Θ j ≃67,4°C
The above value corresponds to the maximum temperature, 67,4 ºC, which will be
developed in the junction of the semiconductor when the power of 1.06 W will flow through
its body. As it was mentioned previously, given by the data-sheet, the snubber diode could
withstand a maximum junction temperature of 175 ºC and thus, it was decided that no
thermal protection should be applied for the four snubber diodes.
2.4.3 Clamp Diode
Through section §2.3.1 the mean and RMS values of the current through the body of
the clamp diode were calculated. Similarly, as in the previous cases, in order to evaluate the
conducting losses of this component, equation 2.13 had to be used. Therefore, the datasheet of this diode were not specifying the values of UT and RD. Thus, these values had to be
determined using an alternative way. According to Rasmussen et al, (2010) when the values
of UT and RD are not specified then, modeling of the diode's actual behavior using the
61 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 piecewise linear characteristic method should be implemented. This was done by
constructing the diode's conducting characteristic which consisted of the forward current,
IF, as a function of forward voltage, VF. Thereby, in the data-sheet of the “RURG5060”
diode, a figure with logarithmic scale, “figure 1” , which describes the forward current as a
function of the forward voltage for three different operational temperatures was provided.
This figure had to be modified as it can be seen in figure 2.13 . Using the latter the unknown
parameters could be determined. “Figure 1” taken by the data-sheet of the diode can be
also found in Appendix, A.2 ;. The method of piecewise linear characteristic approximates the
diode's characteristic curve as a series of linear segments. Looking into figure 2.13 the blue
waveform was created using the real values provided by the data-sheet of the component
while the green line constitutes the linear two-segment approximation. The real diode was
modeled as three components in series, a voltage source, a diode and a resistor. The sloped
line segment, second green line, was selected to be tangent to the diode's operation point.
As operation point, usually referred as Q-Point, it was selected the RMS current value of
the clamp diode, IRMS = 16,6A. Thus, for such an RMS value a threshold voltage of
approximately 0,68V was obtained. The dynamic resistance was then calculated:
R D=
0,68 V
⇒ R D=0,04 Ω
16,6 A
Thus using this modeling method the following values had been determined:
UT: 0,68V
RD: 0,04Ω
62 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Figure 2.13: Waveform made by using figure 1 which can be found in component's datasheet. This generated waveform depicts the diode's forward current as a function of forward
voltage.
As a next step the conducting losses of the clamp diodes were calculated:
P Con=U T⋅I AV +R D⋅I 2RMS
P Con=0,68⋅6,764 A+0,04⋅16,58 A⇒
P Con ≃5,26 W
Moreover, the following information were provided by the data-sheet of the clamp
diode:
Tj= 175 ºC
Rthj-c= 1,6 ºC/W
63 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 Due to the fact that no information about the Rthj-α were provided in the data-sheet, a
value, taken by diodes who were using the same house-body “TO-247” as the
“RURG5060”diode type, was used:
Rthj-α= 30 ºC/W
For an ambient temperature of Θα=25ºC the maximum junction temperature was then
calculated as it follows:
Θ j −Θα =P Con⋅Rthj−α ⇒
Θ j =Θα +P Con⋅R thj−α ⇒
°C
Θ j =25 °C+4,9W⋅30
⇒
W
Θ j =183°C
This value corresponded to the maximum temperature which would be developed in the
junction of the component. As it can be seen it is greater than the allowable value. Thus a
heat sink protection had to be used. At this point it should be noticed that the above
obtained value regarding the maximum junction temperature corresponded to the full load
operation of the inverter.
As in the case of the IGBT module, a heat sink provided by the “Fischer Elektronik”
company was selected. The overview as well as the thermal characteristics of the selected
heat sink are depicted in figure 2.14 .
Figure 2.14: Heat sink model selected to avoid overheating conditions of the clamp diodes
64 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 The length of the selected heat sink, SK114-44, was approximately 44 mm. Using the
above figure it was obtained that for such dimensions a thermal resistance of RTH = 8 K/W
could be offered. Since it was decided to make use of a heat sink the mean of temperature
transmission to ambient was changed. Thereby, the heat sink structure would replace the
junction to ambient temperature of the clamp diode. Therefore, the previous temperature
calculations had to be modified as it follows:
Θ j −Θ α =P Con⋅R H ⇒
Θ j =Θ α +P Con⋅R H ⇒
Θ j =25 °C+5,26 W⋅8
°C
⇒
W
Θ j =67° C
Eventually, using the SK114-44 heat sink model the maximum junction temperature of
the clamp diode was significantly reduced which means that a safe operation had been
ensured.
2.5 Summary of Results
The purpose of this chapter was to theoretically design the diode clamped three level
inverter. Once the various components of the inverter's schematic, figure I1 , were
identified, the theoretical and experimental investigation of it was then attainable. The
theoretical design was successfully implemented in three different stages.
Primarily, estimation of the snubber circuit components values was implemented using
the Asymdim software. The characteristics of the snubber components can be found in table
2.4 .
In the next design stage the semiconductor devices of the inverter's circuit had to be
estimated. These devices were the snubber diodes, clamp diodes and IGBT modules. The
accomplishment of this stage was based on the theoretical equations, the data-sheets of the
components and P-Spice software. The IGBT module type was known from the introduction
of this project and thus, its parameters constituted a significant tool in the estimation of
snubber and clamp diodes. The maximum currents that would flow through the devices as
65 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 well as the voltage limitations and switching speed constituted the main criteria for selecting
the type of the diodes. Thereby, the ultrafast diode “RURG5060” provided by FAIRCHILD
semiconductor and the ultrafast “STTH1212” offered by “ST” were selected as the clamp
and snubber diodes types respectively. The IGBT module type was known from the
introduction, and corresponds to a “2MBI150U2A-060” module type offered by “Front
runners”. A small characteristics description of the aforementioned components have been
presented within the sub-clauses of section §2.3 . Additionally, more detailed technical
information and nominal values of the components can be found in their official data-sheets.
In the third stage of the inverter's theoretical design the thermal aspects of the
components had to be considered. An investigation regarding the need of using thermal
protection means for the clamp and snubber diodes as well as the IGBT module was
accomplished. The knowledge about the currents that would flow through the components,
the data-sheets of the devices and the equivalent thermal representations constituted
substantial tools in this investigation. Therefore, it was obtained that no heat sinks had to
be applied for the snubber and clamp diodes since the maximum temperature which would
develop through their house-body was significantly lower than the maximum allowable,
stated in their data-sheet. More specifically, regarding the snubber diodes it was found that
for a conducting power of 1.06W a maximum temperature of 67,4ºC would be developed. The
maximum allowable temperature provided by the data-sheet was 175ºC, a value much higher
than the actual case and thus, no thermal protection was needed. Regarding the clamp
diodes, it was found that a junction temperature of 183 ºC would be developed. This value
was higher than the maximum allowable provided by the data-sheet of the component and
thus, a heat sink had to be chosen. Therefore, the SK114-44 heat sink type, figure 2.14 ,
could offer a heat path to ambient of only 8K/W. Thus, the junction temperature
calculations were repeated and it was obtained that by using this heat sink safe operation of
the diode was ensured, ΘJ = 67ºC. Moreover, a heat sink was decided to be applied for the
IGBT module. In order to determine its appropriate thermal resistance the thermal
equivalent diagram, figure 2.10 , in conjunction with equation 2.14 were used. Conclusively,
it was calculated that a heat sink of Rth=1,72ºC/W had to be used. Since the IGBT modules
66 of 149 CHAPTER 2 MSc Thesis ­ Spring 2011 had to be mounted on the same heat sink the latter value was divided by two which in turns
yielded an Rth = 0,86ºC/W for each IGBT module. The heat sink SK33-80 provided by
“Fischer-Elektronik” was chosen, figure 2.11 . This model could offer a maximum thermal
resistance of 0.75ºC/W. The latter analysis was covered throughout §2.4 .
67 of 149 CHAPTER 3 MSc Thesis ­ Spring 2011 CHAPTER 3
P-SPICE Investigation Of DCVSI
This chapter focuses on the investigation of the DCTLI using the simulation software
ORCAD P-Spice. All the components that are incorporated in the inverter were allocated,
and thus an equivalent model of this system was build in P-Spice with the intention to
implement an analysis of its overall operational behavior, switching behavior and estimation
of power losses. Additionally, an investigation regarding the meaning of using RClamped was
implemented. The acquired results from this chapter would then be compared to the results
obtained experimentally in Chapter 4 .
3.1 Building of the DCVSI in P-SPICE
The aim of this section was to introduce and describe the P-Spice model of the
inverter system. The type of the power components incorporated in the DCTLI were
specified, Chapter 2 , and thus the modeling of the circuit in PSpice was based on the
nominal characteristics of these components.
Figure 3.1: The P-Spice model of the three level inverter system
68 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 The complete form of the model can be seen in figure 3.1 . This model was designed by
following the main figure of the DCTLI, figure I1. Therefore, by comparing the two figures
various differences can be observed. Four voltage sources have been applied across each
IGBT unit of each module. These sources represented the gate driver circuit required by
each IGBT unit under pragmatic conditions. The intention of these sources was to simply,
turn-on and turn-off the IGBT for particular duty-ratios. In Chapter 2 , by using Asymdim
software it was found that the snubber circuits would act every 2.3μs. Thus each duty-ratio
of on IGBT unit was equal to 2.3μs. Thereupon, the switching sequence of the IGBTs of
the P-Spice model was set as it is described in table 3.1 .
Switching Sequence of the IGBT units defined for the P-Spice Model
Time Intervals (μS)
Switches
S1
S2
S3
S4
0 - 2,3
1
1
0
0
2,3 - 4,6
0
1
1
0
4,6 - 6,9
0
0
1
1
6,9 - 9,2
0
1
1
0
Table 3.1: Switching sequence of the IGBT switches of the P-Spice model
Sign “1” indicates that the device is turned-on whilst “2” indicates the turn-off
condition. Based on the above table it was decided that the time duration of each simulation
in P-Spice would be equal to 10μs. One could see that in the above model four diodes,
Dcoll_S1, have been connected at the collector of each IGBT unit. The goal by using these
diodes was to avoid the current flow through the Emitter-Collector path of IGBTs in the
case of positive current direction. In other words by placing the diode at this point it was
ensured that positive current would flow through the free-wheeling diodes of the
corresponding modules. These diodes were not considered under pragmatic condition,
experimental investigation of the model.
69 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Moreover, the peak current which would flow through the inverter is represented by a
current source. In order to cover both current directions, positive and negative §1.6 ., this
source was flipped around depending on the case analyzed. Thus, the inverter system was
analyzed separately for positive and negative current direction.
3.2 Positive Current Simulations
In this section the inverter's P-Spice model will be investigated for the case where the
current flows from the load towards the inverter. In section §3.1 the P-Spice model of the
three level inverter was introduced including the Rcl. Through this investigation this resistor
was not included.
Prior to the beginning of the simulations the initial conditions of the capacitors and
inductors had to be defined. It was assumed that before turning-on the two units of the
upper IGBT module the inverter's output voltage was “0”. This system's condition yielded
the following results regarding the initial conditions of the components:
➢ Inductors were set to a zero value since no current was flowing through them during
the zero voltage output state.
➢ The over-voltage clamp capacitors, C01 and C02, were assumed to be fully charged,
+400V.
➢ During the zero state of the system the du/dt limitation capacitor, C S1, was fully
charged and thus, it was set to +400V a value which equals the DC voltage of the
positive inverter's arm. Similarly, CS2, was to set to -400V corresponding to the DC
voltage of the negative inverter's arm.
The initial conditions were defined and thus the simulation process could be
implemented.
3.2.1 ''Turn-on'' and ''Turn-off'' of Units S 1 and S 2 (State “0”)
During this state the two units of the upper IGBT module were turned-on. This state
lasts from “0” to “2,3” microseconds. The system's state was change from zero output
70 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 voltage to +400V. The direction of the current was inwards, as it is also indicated by the
current source, and thus the current was flowing through the free-wheeling diodes of the
units. This can be seen in the below figure.
Figure 3.2: Current through S 1 and S 2 when these units are turned-on and the current has a
positive direction
The upper and lower waveforms depict the current through S 1 and S2 respectively. It
was assumed that the the switch is turned-on momentary which means that t r = 0. It can be
observed that DFR_S2 conducts the peak value of the load current, 42,5A. Similarly, D FR_S1
reaches a maximum value of approximately 46A with a small delay of 10ns. Moreover, the
reverse currents of the two diodes are also depicted. Their peaks reach the -50A a value
which corresponds to the one calculated in Chapter 2 . What it should be noticed is the fact
that the diodes continue their conducting state even after the reverse current has finished.
Especially DFR_S2 exhibits a large current spike which reaches a maximum value of 30A. This
is caused due to the new switching state of the system wherein S 2 IGBT unit continuous at
turn-on mode.
Returning to the analysis of state “0”, the blocking voltages of units S 3 and S4 during
the present state of the inverter can be found in the figure below. As it was expected, during
71 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 this state S3 unit is blocking a maximum voltage of approximately 520V. This surplus energy,
about 120V, was a result of the overcharging activity of C01 capacitor.
Figure 3.3: Blocking voltages of units S 3 and S 4 during zero state
Additionally, unit S4, lower waveform, also operates in blocking mode during this state
where it reaches a maximum value of 400V. This was due to the fact that during this state
the negative arm of the inverter was inactive.
The latter facts regarding the action of capacitors C 01 and C02 during this state can be
verified in figure 3.4 . The initial voltage value of C01 was set to 400V. This can be observed
in the next figure. During state “0” C 01 starts from a 400V and it overcharges up to a value
of 520V. On the contrary, the C 02 capacitor, connected in the negative arm of the inverter,
is inactive during this state and no additional current overcharges it. This can be observed
in the lower waveform.
72 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.4: Voltage conditions across C 01 and C 02 capacitors during state “0”
Due to its position in the clamping network, D cl2 was blocking a zero voltage during
this state. That was also known from the current analysis implemented in previous chapter.
The latter can be verified by figure 3.5 , lower waveform.
Figure 3.5: Voltage across clamp diodes during state “0” for a positive current direction
73 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 On the contrary, Dcl1 operates in blocking mode. It blocks a maximum voltage of 520V
which includes the overshoot voltage caused by the extra charging process of the C 01
capacitor. What is more, the voltages across CS1 and CS2 are depicted in figure 3.6 . For the
present inverter's state, at the moment when units S 1 and S2 are turned-on, the discharge
process of CS1 begins. This capacitor remains uncharged as long as the latter units sustain a
turn-on state.
Figure 3.6: Voltage across C S1 and C S2 capacitors during state “0” for a positive current
direction
Similarly, voltage across CS2 capacitor keeps the value of its initial condition +400V.
This is due to the fact that the negative arm of the inverter is still not active during this
state. Some small oscillations can be noticed, at 2,3μs but the amplitude of them appoint
them as not a sufficient disturbance.
74 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.7: Representation of inductor current in conjunction with the current through S 1
The initial conditions of the current through the inductor was set to zero. At the
moment where the two upper units are turned on the current through the freewheeling
diodes rises very fast whilst the current through the inductor takes some time, about
0,8μs, until it reaches the peak load current, -42,5A and then it stabilizes for the rest of
this state. The latter can be verified in figure 3.7 .
3.2.2 ''Turn-on'' and ''Turn-off'' of Units S2 and S3 (State “1”)
This state begins from the moment where the two upper IGBT units are turned-off and
the two in the middle are turned-on. The load current flows through the collector of S 3 unit
it continues through
Dcl2 and it concludes to the midpoint. The voltage output of the inverter in this case
equals to zero. Therefore, in this state the behavior of the components were analyzed for
the time interval between 2,3 to 4,6μs.
The load current flows through the free-wheeling diode and the collector of the S 2 and
75 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 S3 units respectively. This can be observed in the below figure.
Figure 3.8: Current conditions in the two middle units when the latter are turned on and the
current is positive
As it was mentioned previously this state begins at 2.3μs. Therefore, it is important
to notice the effect of the reverse currents on the turn-on process of IGBT unit S 3. It can
be observed that the forward current rises up to a maximum value close to 100A. The turnon process takes about 0,4μs to reach the peak value. Afterwards it jumps to a value about
15A and it then stabilizes to 42,5A. The upper waveform in the above figure shows the
current through the free-wheeling diode of S 2. As it was also mentioned during the analysis
of state “0”, after the reverse current finishes the diode enters in conducting mode, present
state, where it conducts an amount of 30A. What is more, in this state the upper and lower
IGBT units were turned-off and thus a blocking voltage was developed across their
collector-emitter parts, figure 3.9 . The upper waveform corresponds to the IGBT unit S 1
and it can be seen that its blocking voltage reaches a peak of 530V. This was caused
because the transition to to state “1” was implemented from the upper arm of the inverter in
which this unit is connected. Similarly, in the lower waveform, S 4, blocks a maximum value of
400V.
76 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.9: Blocking mode of IGBT units S1 and S4 when the two middle switches were
turned-on
The blocking voltage across clamp diode two is zero since during this state the diode
operates in conductive mode. On the contrary, the upper clamp diode blocks a zero voltage.
The waveforms of the clamp diodes can be found in figure 3.10 .
Figure 3.10: Voltage across the clamp diodes during state “1”
77 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 The current through the clamp diode two can be seen in the next figure. As it was
expected the current conditions through the diode are identical to the current conditions
through the collector part of S3.
Figure 3.11: Representation of the current through D cl2
Through the previous analysis, state “0”, it was shown that the current through the
inductor was increasing to a value equal to the peak value of the load current. During this
state, S1 has been turned-off. For the positive current direction this unit was conducting the
current through its diode part. Thus in the lower figure it can be observed that at this
moment, state “1”, the reverse current of this diode causes the current through the
inductor to increase more than the peak load current, to a maximum value of 50A. This
value corresponds to the peak reverse current of the free-wheeling diodes of the units S 1
and S2. Thereafter, during the rest of this state the current starts to decrease again towards
its initial condition, 0A.
78 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.12: Representation of the reverse current of unit S 1 in conjunction with the current
through the inductor during state “1”
As a next step, the behavior of the capacitors, C S1 and C01, located in the positive arm
of the inverter will be presented. During this state, the current flowing through the diode of
S2 was charging up the two aforementioned capacitors. This condition is depicted in figure
3.13 .
It is interesting to mention that the charging process of the capacitors does not begins
at 2,3μs, the time where middle units are switched-on, but contrarily it takes about 0,4μs.
Looking into figures 3.12 and 3.13 it can be see that the moment where the charging
process begins is the moment when the reverse current stops. Therefore, it is observed that
C01 begins from 400V and it reaches a value close to 540V and at the end of this state its
value decreases again to 400V. On the other hand, the charging process of CS1 capacitor
begins during this state. It charges from zero value to a peak value of 540V and then its
value also decreases to 400V at the end of this state.
79 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.13: Voltage conditions across capacitors C S1 and C 01 during state “1”
Similarly, the voltages across the capacitors, CS2 and C02, placed on the negative arm
of the inverter are depicted in the next figure. Both capacitors are fully charged throughout
all the time of this state.
Figure 3.14: Voltages across snubber capacitors C S2 and C 02 during state “1”
80 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 3.2.3 ''Turn-on'' and ''Turn-off'' of Units S 3 and S 4 (State “2”)
In the present state the negative arm of the inverter constitutes the active part of the
circuit. The two middle switches have been turned-off and the next transition is
implemented by turning-on the IGBT units S3 and S4. In the next figure the current through
the aforementioned switches can be observed. The voltage output in this state is -400V.
Figure 3.15: Representation of current through S 3 and S 4 when these units are turned-on,
state “2”
Upper waveform deduces that S3 IGBT unit remains in conducting mode from the
previous state. As in the previous case the current continuous flowing through the IGBT
part of the unit, collector-emitter path and its value is 42,5A. Correspondingly, the lower
waveform verifies the turn-on process of S4. The current reaches a peak value of 54A and its
path is the IGBT part of the unit. The lower snubber inductor provides a di/dt limitation for
this switch. The latter will be presented further. The peak value of the current through this
switch is higher than the peak load current. This additional energy is a result of the
capacitor's, CS2, discharge process. This can be showed using the next figure which depicts
the discharging process of CS2 in conjunction with the current through S4.
81 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Upper and middle waveform show the voltage and current of CS2 and the in lower
waveform the current through S4 has been added once more for elucidation purposes. As it
can be observed in this figure, capacitor C S2 is fully charged and no current flows through
that part of the circuit. At about 4.7μs a small discharge process, approximately 10A
appears. This amount of energy causes the current through S 4 to further increase to the
value which was mentioned previously, 54A.
Furthermore, the voltage waveforms across the snubber overvoltage capacitors C 01 and
C02 are depicted in figure 3.17 . The upper waveform shows the voltage of C 01 and as it is
observed the discharge process, originated during state “1”, continuous until it reaches its
initial condition, +400V. In the lower waveform of the same figure it is obtained that the
voltage across C02 increases, about 30V, as a result of the energy released from the
discharging process of CS2 which was previously described. This can be verified by comparing
figure 3.18 ,
where the current of C02 is depicted, to the middle waveform of figure 3.16 . It is
verified that close to 4,8μs energy, of about 10A, is released by the discharging process of
CS2 and it is then flowing through snubber diode four towards the resistor and it concludes to
the negative arm of the C02 capacitor which causes the latter to a small overshoot as it was
mentioned previously.
82 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.16: Current increase in S 4 caused by a discharging process of C S2 during turn on of
the former
Figure 3.17: Representation of voltages across capacitors C 01 and C 02
83 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.18: Energy increase in C 02 during state “2”
During this state the upper IGBT module, switches one and two, is in blocking mode,
figure 3.19
where across both switches a voltage level of 400V is developed.
Figure 3.19: Blocking voltage of IGBT units S 1 and S 2 during state “2”
When the S3 and S4 are turned-on the current through the lower inductor increases as
it is shown in figure3.20 . Its peak value is equal to the peak value of the current through the
lower switch, 54A. Moreover, the current through the switch increases linearly with the
slope appointed by the following equation:
di /dt =
L ⋅I
U
⇒ t r= 2
L2
U
84 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 tr=
1,6 μH⋅54A
⇒t r =0,216 μs
400V
The latter result can be verified in figure 3.20 since the time taken for the current to
reach the peak value is about 0,2μs. Afterwards the current in the inductor decreases
linearly to the peak load current value.
Figure 3.20: Representation of the current through the lower snubber inductor in
conjunction with the current through IGBT unit S 4 during state “2”
Eventually, analyzing the behavior of D cl2 during this state it was deduced that the
component enters in blocking mode and thus the current decreases, when the two lower
IGBT units are turned-on. This fact can be seen in the figure below.
85 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.21: Voltage and current of Dcl2 during state “3”
3.2.4 ''Turn-on'' and ''Turn-off'' of units S 3 and S 2 (State “3”)
This state concludes the simulation cycle which was defined in P-Spice model in order
to analyze the operational behavior of the DCTLI. Thus, in this state the transition from the
two lower to the two middle IGBT units is implemented. This case was previously analyzed
but in that case the transition was made by the two upper IGBT units. In the present stage
the S4 unit turns-off and S3, S2, units are turned-on. The current runs through the lower
clamp diode and it concludes to the DC midpoint. Thus, the output voltage of the inverter is
now zero. The analysis of this state begins by introducing the snubber action of capacitor
CS2. This capacitor was used in order to provide a du/dt limitation across S4 during the
turn-off process of the latter. In order to show the importance of using this capacitor figure
3.22
is introduced. In this figure the conducting losses, apparent power, of the S4 unit are
depicted in conjunction with its voltage and current waveforms for the time interval dictated
by the time interval of the present inverter's state, 6,9 to 9,2μs. It should be noted that
this figure was derived by excluding the CS2 capacitor in order to emphasize on the impact of
this absence. Thereby, it was deduced that at 6,9μs, the time when S 4 transits to blocking
86 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 mode, the losses in the switch reaches very high value, close to 18kW. The same graph was
derived for the case where the capacitor is connected to the snubber circuit and it was then
obtained that losses had been reduced significantly, approximately 35W. This figure has
been placed in appendix A.3 .
Regarding the current and voltage of this unit, looking in the same figure, it is
observed that once the switch is turned-off the voltage reaches the maximum voltage of C 02
capacitor and the current decreases to 0A.
Figure 3.22: Voltage, current and power losses of S 4 unit when snubber capacitor C S2 is not
connected
The load current flows through the free-wheeling diode and switch parts of S 2 and S3
units respectively, figure 3.23 . Comparing the present current conditions of the units to the
corresponding conditions of the same switches during state “1” it can be deduced that in
the current state there is no additional energy coming from reverse currents caused by the
action of the anti-parallel diodes. This is true since during the previous state, state “2”, the
current was flew through the IGBT units of S3 and S4 and thus, no reverse currents were
produced. On the contrary, during state “1” reverse current caused by the conduction
mode of DFR_S1 and DFR_S2 during state “0” were increasing the current through S 2 and S3
87 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 units.
What is more, the voltage and current of Dcl2 can be seen in figure 3.24 . On the
contrary to the previous state, now the clamp-diode is forward biased and thus current flows
through its body. The current reaches a value of approximately 52A due to the overcharging
process of the snubber capacitors located in the negative arm of the inverter. Its voltage
decreases to zero.
Figure 3.23: Current through S 2 and S 3 units when transition of state “2” to state “3”
is implemented
88 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.24: Voltage and current of Dcl2 during state “3”
Conclusively, the measured voltage output of the inverter after the end of a full
switching sequence, table 3.1 , can be seen in figure 3.25 . The result shows a staircase
voltage waveform identical to the one introduced during the theoretical explanation of the
diode clamped three level inverter, §1.5: figure 1.8. It is seen that during state “0” the
voltage output is at +400V. Similarly, when the two middle switches are turned-on the
voltage output is clamped at the DC midpoint and therefore equals zero. Similarly, during
state “2” where the negative arm of the inverter is active, a -400V is produced. At last, a
voltage overshoot caused by the overcharging process of the capacitors C 01 and C02 can be
observed on both voltage output levels. The amplitude of this overshoot was about 5% of the
maximum voltage level.
89 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.25: Output voltage waveform of the DCTLI for a full switching sequence, when the
current has a positive direction
3.3 Negative Current Simulations
The P-Spice model of DCTLI which is depicted in figure 3.1, was analyzed throughout
the previous section for the case where the current flows towards the inverter, positive
current direction. In this section the model was analyzed for a negative current direction
which means that now the current flows outwards, with a direction to the load. From the
theoretical part it was known that the voltage output is independent of the current direction.
Additionally, the several components that are incorporated in both arms, positive and
negative, of the DCTLI were placed in a symmetrical way. Thus, operational behavior
identical to the one described in the case of positive current was derived. The results for
this current direction have been introduced in A ppendix A.4 . It should be reminded that
these results were obtained by simulating the P-Spice model depicted in figure 3.1 where
the current source was flipped to an outwards direction. The switching sequence was again
90 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 based on table 3.1 . The initial conditions of the capacitors and inductors were the same as
in the case of the positive current direction. Additionally, the clamped resistor was also
excluded in this case. Nevertheless, in order to verify that the model operates satisfactory
also for the case of the negative current direction, some results including the voltage output
of the inverter, snubber inductor and capacitor will be presented in the next sub-clauses.
3.3.1 ''Turn-on'' and ''Turn-off'' of the two upper IGBT units (State “0”)
The current throughout the inverter flows with an outwards direction, which means
towards the load of the system. On the contrary to the positive direction case, presently,
during state “0” the current initiates from the DC voltage source of the inverter, it flows
through the IGBT part of units S1 and S2 and it concludes to the output point. The latter
fact is described in the below figure.
Figure 3.26: Current through IGBT units S 1 and S 2 during state “0” for a negative current
direction
The upper waveform shows the current development through S 1 where the current
reaches a maximum value of approximately 76A. This current increase is a result of the
91 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 additional energy released by the CS1 capacitor when S1 has turned-on. The lower waveform
depicts the current through S2. The above results correspond to the state “2” of the
positive current direction analysis. As it can be seen in the above figure the S 2 unit is in
conducting mode from its initial state since its current value starts increasing from 20A to a
peak value of 80A. An identical situation is depicted in the waveform of IGBT unit S 3 during
the state “2” in the positive current analysis. Additionally, the current waveforms through
upper unit and snubber inductor L 1 have been plotted together in the next figure. The
intention of doing that was to observe the di/dt limitation provided by the inductor.
Figure 3.27: Current through S 1 and L 1 during state “0” for a negative direction of the
current
From the above figure the following were deduced, for a peak current of approximately 80A:
di /dt =
tr=
L ⋅I
U
⇒t r = 1
L1
U
1,6 μH⋅80A
⇒t r =0,32 μs
400V
The above obtained rise time can be verified in the above figure.
92 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 3.3.1 ''Turn-on'' and ''Turn-off'' of two middle IGBT units (State “1”)
In order to verify the du/dt limitation that C S1 provides to S1 when the latter is
turned-off, the power losses in the switch had to be determined. As in the case of the
positive current direction the voltage across the switch in conjunction with the current and
power losses were plotted in the same figure. The results can be found in figure 3.28 where
the simulation was performed excluding the CS1 snubber capacitor. As it is obtained the
power losses have gained a significant increase. Contrarily, the power losses in the switch
when the snubber capacitor was connected equals to a maximum value of 34W. Eventually,
the output voltage of the inverter when the current is negative can be seen in figure 3.29 .
All the above results revealed that the operation of the P-Spice model for both current
directions was identical. Additionally, full switching sequence results of each component for
the case of the negative current can be found in Appendix A.4 .
Figure 3.28: Voltage, Current and power losses in switch S 1 when C S1 is not connected a the
current has a negative direction
93 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.29: Output voltage of the inverter for a negative current direction
3.4 Estimation of Losses
In this section the losses of the inverter had to be calculated. It was known that two
forms of losses can be developed in the operation of an inverter system. These two forms are
the switching and conducting losses. The total losses can be determined by summarizing the
total conducting and total switching losses. The switching losses are associated with the
energy losses due to the turn-on and off process of a semiconductor device. In the case of
the DCTLI the switching losses were determined by estimation of energy losses in the four
snubber diodes. Additionally, the losses in the four IGBT units and the two clamp diodes
corresponded to the conducting losses of the inverter.
Using P-Spice the mean and RMS value of the current which would flow through the
snubber diodes were determined in Chapter 2 . Thus, in this section the total switching
losses were determined for a full switching period by summarizing the energy losses of each
snubber diode. Furthermore, a briefly overview of snubber diodes behavior during the
94 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 different states of the inverter was estimated using P-Spice and it has been also introduced.
A reference to the estimation of losses in the snubber resistors have also been presented.
3.4.1 Conduction Losses
In Chapter 2, the conducting losses of the upper IGBT module were calculated. This
was done in order to determine if a heat sink protection was needed. Presently, the total
conduction losses caused by the IGBT units had to be calculated with the main intention to
farther evaluate the total losses of the inverter.
Since the conduction losses for the upper IGBT module had been calculated same
values regarding the lower module were expected. However, the mean and RMS current
values as well as the conduction losses of the latter IGBT module were calculated and they
can be found in Appendix A.5 . In the same appendix section the current representation
through this module is also presented in f igure A5.1a) through A5.1c) .
The following table summarizes the conduction losses of the lower IGBT module.
UPPER IGBT MODULE (S 3 & S 4 )
Circuit
State
P I3
(Watts)
P I4
(Watts)
P D3
(Watts)
P D4
(Watts)
A.
0
0
7.97
7.97
B.
7,97
7.97
0
0
C. - S2
0
15.9
0
0
Total
7,97
23,87
7,97
7,97
Table 3.2: Conduction losses of the lower IGBT module
Thus, the total conducting losses of the two IGBT modules could be calculated using
the following equations:
 Upper Module
P upper (tot) =P( I1)+ P(I2 )+P (D1) +P( D2) ⇒ P upper(tot) =7.96W+23,86 W +7,96W +7,96W ⇒
P upper (tot) =47,74 W
(3.1)
95 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011  Lower Module
P lower (tot)=P (I3 )+P( I4 )+P (D3)+ P(D4 )=7.97W+23,87 W +7,97 W +7,97 W
P lower (tot)=47,73W
(3.2)
Similarly, in Chapter 2 , the conducting losses through D cl1 were calculated in terms of
the heat sink investigation. According to section §2.4.1 the conducting losses of the clamp
diode one were equal to 5,26W. This value was also considered as the conducting losses in
Dcl2. Thus, the total conducting losses produced by the clamp diodes were equal to:
P Cl(tot)=10,52 W
Eventually, the total conducting losses of the inverter could then be calculated:
P Con(tot) =P upper(tot) +P lower (tot )+P Cl(tot)=47,74 W +47,73W +10,52
P Con(tot) =106W
(3.3)
3.4.2 Switching Losses
Prior to calculation of the switching losses, the behavior of the snubber diodes during
a whole switching period, 10μs, will be introduced. The following results were obtained in
P-Spice for a positive current direction and without including Rcl.
96 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.30: Voltage across snubber diodes placed on the positive arm of the inverter
When state “0” of the inverter begins D 1 is in blocking mode, -400V. This was verified
by observing the voltage conditions of CS1. Prior to state “0” the latter capacitor is fully
charged, +400V, a situation which causes D 1 to be reverse biased. After turn-on of the two
upper IGBT units the reverse emf developed across the inductor causes the snubber diodes
to conduct current. The current waveforms of these two diodes are depicted in the below
figure.
97 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.31: Current waveforms of snubber diodes one and two when the current is
positive
Continuing looking into the voltage waveforms of the snubber diodes it can be seen
that D2 enters in blocking mode at 2,3μs since at that moment the inductor has been biased
again due to the reverse current caused from S 1 unit. When the reverse current stops, at
2,7μs, it can be seen that both diodes enter in conducting mode. Moreover, both the above
figures revealed that when the negative arm of the inverter was becoming active these
diodes were blocking a zero voltage. Similar operational conditions were observed for the
case of D3 and D4 and thus their waveforms can be found in Appendix A.6 .
As it was shown in Chapter 2 , Section §2.3.3 , using the current waveforms of the
four snubber diodes the mean and RMS values of the currents could be calculated.
Correspondingly, in section §2.4.2 the losses through D1 were calculated in order to
evaluate if a heat sink application was demanded. Thus, in a similar way the losses of all four
diodes were calculated in order to summarize their results and obtain the switching losses.
The calculation process can be found in Appendix A.7 .
P SW (tot)= P SW (D1)+ P SW (D2) +P SW ( D3)+P SW ( D4)=1,06 W +1,05W +0,53W +0,54 W
P SW (tot)=3,18W
(3.4)
98 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Conclusively, the total losses of the inverter could be determined by summarizing the
switching and conducting losses.
P total = P SW (tot )+P Con (tot)
(3.5)
P tot =3,18 W +106W
P tot =109,18W
3.4.3 Power Losses in Snubber Resistors
The power losses estimation constituted the aim of this section. Using P-Spice the
current waveforms of the snubber resistors were plotted and using the integral function S(x)
the energy losses were estimated. Figure 3.32 depicts the integral of the current through
the snubber resistors, RS1 and RS2. Primarily, the maximum values of the energy losses were
obtained as it follows:
10μs
∫ i2Rs1 dt⋅R S1=3,5158 mAs
0
10μs
∫ i2Rs2 dt⋅R S2=1,5524 mAs
0
99 of 149 P­SPICE Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 3.32: Current integral through the snubber resistors used for determining the
energy losses
The above values were then multiplied by the switching frequency as it follows:
Snubber Resistor, RS1
•
P RS1 =W RS1⋅ f SW =3,5158 mAs⋅10kHz
P RS1 =35,158 W
Snubber Resistor, RS1
•
P RS2 =W RS2⋅f SW =1,5524 mAs⋅10kHz
P RS1 =15,524 W
The chosen type of snubber resistor, a 10Ω TO-220 power resistor, could withstand a
maximum power dissipation of 50W. During the experimental process changes in switching
frequency were considered in order to observe the behavior of the inverter. By increasing
the frequency the power losses through the resistors would also increase and thus, for safety
reasons, two parallel resistors of 10Ω instead of one 5Ω would be installed in the pragmatic
model.
100 of 149 CHAPTER 4 MSc Thesis ­ Spring 2011 CHAPTER 4
Laboratory Investigation Of DCVSI
In this chapter the experimental investigation of the DCTLI was implemented. This was
done in order to verify the results derived from the simulation analysis which was performed
using P-Spice software and it was described in Chapter 3 .
This chapter begins by introducing a description of the construction process
throughout the “building” of the experimental model. A reference is made to the tools used
for this purpose and a detailed description of the inductor's constructional process is
presented. Prior to analysis of the laboratory results an overview of the experimental system
is introduced by using a general block diagram representation. A briefly overview for each of
the PCB hardwares is then follows, which aims to yield a more specific explanation regarding
their operation.
Thereinafter, this chapter concludes by introducing and analyzing the results.
4.1 Design Process Of Inverter's Hardware
Several PCB hardwares had to be constructed in this thesis such as the diode clamped
inverter depicted in figure I1 , a gate driver for controlling of the IGBT switches and a pulse
generator. Using Orcad P-Spice, Orcad Layout and Routepro 2000 softwares it was possible
to reliably construct the latter PCB hardwares. PCB designing of a theoretical model
constitutes a complex procedure including structural decisions, that in many cases require a
foreseeing by the designer, compromises, theoretical investigation and research in the power
electronics market. Several barriers regarding, power components selection and structural
design might occur such as, lack of components in the market industry and structural errors
during the preliminary design of the board. The hardware was designed under the guidance
of Tonny W. Rasmussen.
101 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 4.1.1 Inductor Design
In this section the physical, magnetic and thermal parameters of the two snubber
inductors, Ls1 and Ls2, had to be allocated since manually construction of them had to be
implemented. The value of the inductance for both inductors, calculated through Chapter 2
of this project, was known and thus some preliminary decisions were made. Each inductor
was equal to 1,6μH.
It was decided that the coil former ETD 29 provided by “EPCOS AG” could be the
base on which the inductor would be constructed. According to the data-sheet of this coil
former it was known that magnetic cores such the “N87” and “N27” types could be used.
These types included an air-gap. In order to find which type could be used the number of
winding turns of the inductor had to be estimated using the below equation:
N=
√
L
AL
(4.1)
Where,
N: Number of turns
AL: Inductance factor in nH
L: Value of the inductance, H
In the above equation, the only unknown parameter was the A L. Its value differed for
each magnetic core type and the values were provided by the data-sheet of ETD 29 core.
Thus the following were applied:
N27:
N=
√
1,6 μH
⇒ N ≃1,6turns
621 nH
√
1,6 μH
⇒ N ≃ 2 turns
383 nH
N87:
N=
Based on the above results it was decided that the magnetic core type would be the
N87 which for an inductance of 1,6μH yielded two winding turns. The air-gap distance, g,
102 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 was equal to 0,20mm.
As a next step the maximum magnetic field, B max, which would developed around its
copper conductors was calculated using equation 4.2 .
B max= μ⋅μ 0⋅I L⋅N
(4.2)
Where,
μ: Permeability of the core material
μ0: Magnetic constant, 4π*10-7 N/A2
ΙL: Peak current through the inductor
N: Total number of winding turns
The peak current which would flow through the inductor had been estimated in
Chapter 3
using P-Spice, IL = 52,419A.
Therefore,
( AN )⋅52,419 A⋅2 ⇒
B max=281⋅4π⋅10−7⋅
2
B max=37 mT
Since the maximum magnetic field was calculated, as a next step this value had to be
compared to the saturation point of the N87 core type. For that purpose the hysteresis or
B-H loop waveform of the core was used taken by its data-sheet. This waveform can be
found in Appendix A2 . The waveform which corresponded in an operation at T = 25ºC was
used. It was then deduced that for a magnetic field of 37mT the point of magnetic saturation
was not reached which meant that core will not saturate.
The power losses determination was the next step of the inductor analysis. The main
purpose was to determine the total losses of the core. This could be implemented using the
following equation:
P tot =P fe +P cu
(4.3)
Where,
Pfe: Core losses of the inductor
Pcu: Copper Losses through the windings
103 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Primarily, the core losses were determined using figure 4.1 . This figure was taken by
the material data-sheet of the core N87 and shows the core losses as a function of the
switching frequency.
Figure 4.1: Core losses as a function of switching frequency for an EPCOS N87 magnetic
core
The switching frequency which would be used in the model was known, f S = 10kHz and
thus, using the above figure the core losses could be found. As it can be seen for 10kHz no
values are provided and thus, a value which corresponded to 25kHz was selected in order to
ensure the operation of the inductor in higher switching frequencies if it would be needed.
Therefore for 25kHz the following value was obtained:
P V =5
kW
3
m
This value corresponds to 5 kW per cubic meter. The effective magnetic volume, V e, of
the N87, was provided by the data-sheet,
V e =5350 mm3
Therefore, the total core losses were calculated:
104 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 P fe=5
kW
⋅0,000005 m3 ⇒
3
m
P fe=25mW
As a last step, the copper winding losses of the inductor had to be found. This was
implemented using equation 4.4 .
P copper =
ρ⋅N⋅(MLT )⋅I 2RMS
AW
(4.4)
Where,
ρ: Effective resistivity of the copper wire
IRMS: RMS value of the current
MLT: Mean length per winding turn
N: Total number of winding turns
AW: Cross section of copper wire
The copper material used for constructing the inductor was a wide flat and thin piece
of copper. Its cross section was measured to be 0,1 mm. Regarding the value of resistivity, a
general estimation was used, ρ = 1,68*10 -8. Thus the copper loses were determined as it
can be seen below:
P copper =
1,68⋅10−8⋅2⋅52,8 mm⋅(30A )2
⇒
0,1 mm
P copper =15,96 mW
The total power losses were then calculated using equation 4.3 :
P tot =15,96 mW +25mW ⇒
P tot =40,96 mW
105 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 4.2 Overview Of Inverter's Hardware
Figure 4.2
depicts the block diagram of the power converter system used for
laboratory investigation. The system contains all the hardware which was necessary in order
to reliably represent the operation of the DCVSI.
Figure 4.2: Block diagram of the three level inverter's experimental model
In the above diagram, on the left the pulse generator is depicted. The latter was used
in order to generate the pulses needed for turning-on and turning-off the IGBT units of the
inverter. Prior to transmission of these signals to the gate-emitter pins of the switches,
amplification had to be implemented. This was done using the gate driver hardware. This
hardware consisted of four individual gate driver circuits. Moreover, at the end of the block
diagram an inductor can be found which was used as the consumption load of the system. By
making use of an inductive nature load reactive power could be consumed.
4.2.1 Pulse Generator
In order to perform the transition between turn-on and turn-off states of the IGBT
units, a voltage square pulse had to be applied across the gate-emitter terminals of each
106 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 switch. Provided by the data-sheet of the IGBT module, the threshold voltage was known,
UTH = 7,7V. Thus, an electronic PCB named as “Pulse Generator” was designed with the
main intention to fulfill this purpose.
The circuit of the pulse generator consisted of two parts, or more accurately by two
different PCB boards. The main idea of this hardware was the generation of an electrical
analogue signal which would then be converted into an optical signal for transmission
purposes and it would then converted again into an analogical electrical signal in order to
provide the necessary potential difference across the IGBT gate-emitter terminals. The
analogical signal was generated using the hardware which is depicted below in figure 4.3 .
Figure 4.3: Signal generator PCB designed to provide the current signal for the dual
peripheral drivers
The above schematic reveals that by making use of analogue electronic components
such as voltage comparators, analogical inverters and operational amplifiers an electrical
signal of variable frequency and angle, which would then be the input of pulse's generator
second hardware, could be generated. As it can be seen, in total four output signals are
generated. The next part of the pulse generator is depicted in figure 4.4 .
107 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 The operation of the pulse generator was based on the two “SN75452” dual peripheral
drivers. The supply voltage of these drivers was equal to +5V. In the above figure the power
supply circuit can be seen in the lower left corner and it is the same for both of the
peripheral drivers. According to the data-sheet of the component the principle of operation
of this driver was based on the NAND (Not AND) logic gate.
Thereafter, the output signals of the integrated circuits constituted the input signal of
the four, D1, D2, D3 and D4, LED photo transmitters, “SFH750”. The latter were used in
order to “convert” the electrical analog data, received by the peripheral driver, into an
optical signal coupled onto a fiber optic cable and transmitted to an optical receiver which
was placed on the PCB hardware of the gate driver. The latter is described in the next subclause.
Figure 4.4: P-Spice schematic overview of the pulse generator electronic circuit
108 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 The PCB hardware of the pulse generator was designed by the associate professor
Tonny W. Rasmussen and its pragmatic overview can be found in figure 4.5 .
Figure 4.5: PCB hardware of the pulse generator used in the experimental investigation of
the DCTLI
4.2.2 Gate Driver The equivalent circuit of the gate drive can be seen in the below figure. It consists of
three parts:
 The power supply, ±15V
 Its power driver, UC3707
 The optical receiver, SFH551V
The power supply of the power driver is at a DC voltage level of ±15V. This voltage level
was generated by using a diode bridge rectifier in parallel with four Zener-diodes. The
rectifier is represented by the four BYV27 diodes, D1 through D4, and in the laboratory, its
input current was provided by an AC current generator. The current was induced into the
diode rectifier using a single phase transformer where its secondary winding comprised of 30
turns. The AC form of this current was then converted in a DC current by the four ultrafast
109 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 diodes. The four Zener-diodes, Z1 through Z4, of particular voltage levels, acted as voltage
regulators in order to ensure that the output voltage will not exceed the desired ±15V.
Figure 4.6: P-Spice Schematic overview of Gate Driver's printed circuit board
Moreover, the optical receiver which lies on the left side in figure 4.6 , needed a supply
voltage of -10V which was also provided by the output of the diode rectifier. Its purpose
was to receive and amplify the optical signal generated by the pulse generator PCB.
Afterwards, the signal is transmitted to the power driver and it concludes through the gate
resistance to the terminals of the IGBT unit located on the inverter's PCB. The gate
resistance of the IGBT was known from the data-sheet of the component, 48Ω, and thus
two resistors of 24Ω were connected in parallel. It should be mentioned that four in total
gate drivers were constructed and each of them corresponded to one of the four IGBT units.
The constructed model of the four gate drivers can be seen in the below figure 4.7 .
110 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 4.7: Pragmatic model of the four IGBT gate drivers
4.2.3 Hardware of the Diode Clamped Three Level Inverter
The P-Spice equivalent of the DCTLI which was analyzed in Chapter 3 was used in order to
build its experimental model. However, in the actual case some modifications that were not
affecting its operation had to be implemented. These differences can be seen in figure 4.8
where the P-Spice schematic is depicted. Primarily, in order to ensure a safe power
dissipation across the snubber resistors, two 10Ω resistors were placed in parallel in order
to form the needed value. The energy losses in the resistor were calculated using P-Spice in
Chapter 3 .
Moreover, due to the non-availability of 68nF capacitors on the component
provider's product list, it was decided to use two capacitors, 47nF and 22nF, in parallel in
order to form the theoretical calculated value. The constructed model can be seen in figure
4.9 .
111 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 4.8: P-Spice schematic overview of the DCTLI used for its actual implementation
Figure 4.9: Experimental model of the single phase diode clamped three level inverter
112 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 4.3 Experimental Results
The goal of performing this experimental part was to verify the operation of the
theoretically analyzed inverter model in actual conditions. The PCB of the DCTLI as well as
the additional peripheral hardware had been constructed and a briefly description was given
in the beginning of this chapter. Prior to performing the experimental investigation each of
the peripheral hardware, pulse generator and gate driver, was tested separately in order to
check that its operation was the one expected. This was implemented by testing the output
signals of the latter. At this point it should be noted that due to the lack of laboratory
experience several mistakes, that occurred during the early design of the gate driver and
inverter PCB, slew down the whole process of the experimental part.
After implementing some constructional corrections on the gate driver PCB, then the
pulse generator was connected to the four gate drivers and by using an oscilloscope
verification of pulse signals was implemented. As a next step all the PCB hardware, including
the inverter, were interconnected in order to begin the experimental analysis of the latter.
The complete hardware used for this first stage analysis was comprised of the PCB
hardwares, two DC power supplies ±30V and ±15V, oscilloscopes, differential amplifiers
probes and a resistive load of 680Ω. Using such a configuration in this stage of the analysis
safety was ensured since the two power supplies were providing a current limitation and thus
in case of short circuits existence damages would be avoided.
4.3.1 Voltage Spike Occurrence
In this case a resistor of 680Ω was used as the consumption load. The applied DC
voltage at both, positive and negative, arms of the inverter was equal to the maximum
possible for this stage, 30V. In the figure below it can be seen that the voltage output signal
was of identical shape to the voltage output derived in the theoretical investigation, figure
3.25 §3.2.4 .
113 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 4.10: Measured voltage signal at the output terminals of the inverter
It should be noted that in this analysis stage the switching frequency and phase angle
of the inverter were not adjusted to match the theoretical design since verification of its
basic operation was the main goal. In the above figure each division corresponded to 25V
which means that a maximum, voltage of approximately 30V was measured at the output.
However, as it can be observed a high voltage spike was occurred. The amplitude of this
spike was almost double comparing to the applied voltage. That means that if a 400V would
be applied at the input of the inverter system, this spike would reach a peak value of 800V
which in turns would damage several components on the board. Therefore, in order to move
any further this spike had to be removed. This was done by enhancing several parts on the
inverter's board with extra solder in order to achieve better connections. Additionally, the
system was change, by placing an inductive load of 7mH at the output of the inverter.
Additionally, this new configuration of the system was also implemented in P-Spice in order
to be easier to determine the error which could generate this spike. By performing several
simulations it was found that snubber diode one was not placed correctly on the board and
this was generating the voltage spike, figure 4.11 . Therefore, the results of the output when
the spike had been removed can be found in figure 4.12 . It is seen that there is still an
overshoot but now the amplitude is much smaller and additionally, the latter fact was also
obtained in the P_spice simulation of the inverter.
114 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 4.11: Voltage spike generated by the absence of snubber diode one
Figure 4.12: Representation of the significant reduction of the voltage spike
4.3.2 Results Using an L = 4,66mH
Since the system seemed to be more efficient, three inductors were connected in
parallel in order to achieve a higher current amplitude. Each of the variable inductors were
equal to 14mH and thus, a total inductive load of 4,66mH was obtained. The applied voltage
115 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 at the DC side of the inverter was kept at maximum 30V. Moreover, the switching frequency
of the system was adjusted to 10kHz and the switching angle, α, was set to 30º degrees.
The latter value corresponded to a time of 8,333μs considering a whole period. That means
that the system was switching from the zero state at 8,333μs. Thus, the inverter's current
and output voltage were measured and their results can be found in figures 4.14 and 4.13
respectively.
Figure 4.13: Voltage output of the inverter for a maximum applied voltage of 30V
The above voltage waveform is identical to the one obtained during the theoretical
investigation. Each division corresponds to a value of 10V and thus a maximum voltage of
37V is obtained. This overshoot was a result of the overcharging process of snubber
capacitors C01 and C02.
Figure 4.14: Measured output current of the inverter
116 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 In the above figure each division corresponds to 100mA. As it can be seen its peak
value equals 100mA and some oscillations are present. The attenuation of these oscillations
could be well reduced using a damping resistor of 15Ω. But using such a resistor would
increase the system losses significantly. Instead a resistor of 1Ω was chosen to be
continuously connected between the output load and the inverter. The gate-emitter signals
of the four IGBT units are depicted in the below figures. The measurement was implemented
on the side of the inverter, across the terminals of each IGBT unit.
Figure 4.15: Voltage signals measured at the terminals of S 1 (blue) and S 2 (pink)
Figure 4.16: Voltage signals measured at the terminals of S 3 (blue) and S 4 (pink)
The above figures revealed that the hardware of the gate driver was functioning
satisfactory since it was providing the necessary output signal for switching on and off the
IGBT units.
117 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Further analyzing the inverter's board the voltage waveforms of the two clamped
diodes were measured and they can be found in the next figures. Comparing these figures to
the results obtained using P-Spice it can be seen that the results are identical, figure A6.14 .
More specifically, in this figure it can be seen that at the beginning of one period D cl1 (blue
colour) enters in blocking mode and then throughout the rest of the period it blocks a zero
voltage. Similarly, Dcl2 begins at a zero voltage level and at the moment where the negative
arm of the inverter becomes active it blocks the corresponding nominal voltage. In both
waveforms of the clamp diodes the overshoot can be observed. Additionally, the voltage
output of the inverter (right figure) has been also included beside the figure of the clamp
diodes (left) in order to make clear the moment of action of the the diodes within a switching
period. Therefore, the time axis for both figures is the same.
Figure 4.17: Voltage across the clamp diodes in conjunction with the voltage output
As a next step, the voltage across the C 01 capacitor was investigated. Two figures are
presented below. The one in the left shows the voltage across the aforementioned capacitor
and the right depicts the voltage of the capacitor in conjunction to the voltage output.
118 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 Figure 4.18: Voltage conditions across snubber capacitor C 01 (left) and comparison to
the output voltage (right)
The above figures verified the results obtained through the theoretical part, figure
A6.10 .
The capacitor was overcharging for every switching sequence in the positive arm of
the inverter. One point to mention is the fact that during the theoretical investigation, when
the positive arm of the inverter was active, +400V turn-on of S 1 and S2, first overshoot of
this capacitor was the one of the lowest amplitude. In the above figure the opposite case is
observed. Regarding the amplitude of this overshoot, it can be seen that for a 30V input
voltage an overshoot of 1,5V occurred, i.e, 5% of the input voltage. The latter can be
verified in figure A6.10 where for an input voltage of 400V a peak value of 520V is reached.
From the theoretical investigation, figure A6.11 , it was derived that the snubber
capacitor CS2 was fully charged during the time whereas the inverter's negative arm was
inactive. This can be experimentally verified in the below figure.
Figure 4.19: Voltage conditions across the CS2 snubber capacitor
119 of 149 Laboratory Investigation Of DCVSI MSc Thesis ­ Spring 2011 4.4 Discussions
The above figures revealed that a ''partly'' satisfactory operation of the experimental
model was achieved. The word ''partly'' is used since some irregularities were obtained.
Under normal conditions, as a next step the voltage supply had to be replaced and thereby a
gradual increase of the DC input voltage would then be implemented. However, this was not
possible to be done since the negative arm of the inverter was exhibiting some irregularities
regarding the voltage across the snubber capacitor C 02. The latter fact was a result of
constructional error and under such conditions the voltage could not be increased.
Furthermore, the period of occurrence of this error confined substantially a possible
correction which would allow the farther investigation of the experimental model. The error
was allocated. During the early design of the inverter's PCB, a mistake regarding the
dimensions of the isolated conductive area in which the IGBT terminals would be connected
required the use of an insulation tape in order to provide the necessary isolation. Indeed,
the use of the insulation tape was a risk, but at that specific moment of the Thesis time
schedule, it constituted the only possible solution. Eventually, the verification of the
theoretical model was decided to be based on the experimental analysis introduced through
the previous sections and focus was given on composing the documentation of this whole
procedure.
120 of 149 CONCLUSION MSc Thesis ­ Spring 2011 CONCLUSION
The main objective of this Master Thesis project was to analyze the switching behavior
of a diode clamped three level inverter theoretically and experimentally. The inverter was
equipped with a passive Undeland Snubber Circuit. The theoretical analysis was covered by
using as a main tool the computer aided simulation software P-Spice. Asymdim software was
also used during the theoretical analysis. An overview of the results and conclusions that
were estimated in each chapter are briefly discussed through the next lines of this section.
In Chapter 1 the technology of high power electronics was introduced through the
first sections of the former. Nevertheless, the main intention was to introduce the main
objective of this thesis, the clamp diode three level inverter. Its basic snubber circuit and
operation were elucidated and explained respectively. The theory behind the inverter was of
significant importance in concluding this project. At last the switching angle of the inverter
was used in order to eliminate one harmonic. In consultation with the associate professor
Tonny W. Rasmussen it was decided that this inverter should eliminate the third harmonic
and thus, α = 30º.
In Chapter 2 all the components that are incorporated in the inverter had to be
primarily identified based on theoretical terms and simulation softwares. The second
objective in this chapter was to investigate the need of thermal protection for the latter
components.
Therefore, primarily the characteristics of the snubber components but the snubber
diodes, were estimated using Asymdim software and they can be found in table 2.4.
Afterwards, the rest of the power components were estimated including the snubber diodes.
Prior to the selection of the components the current limitation for each device was
evaluated. Then using as selection criteria the
nominal voltage, nominal current and
switching speed the components were selected. An overview can be found in sections
§2.3.1 through §2.3.3. The thermal design of these components was covered in sections
§2.4.1 through §2.4.3. From the early design it was known that the IGBT module would
121 of 149 CONCLUSION MSc Thesis ­ Spring 2011 have to be equipped with a heat sink. The characteristics of the latter were determined and
they can be found in figure 2.11. Additionally, it was derived that thermal protection it
was not needed for the snubber diodes due to the development of a safe junction
temperature, ΘJ = 67,4ºC. Contrarily, the clamp diode had to be equipped with a heat sink
since a maximum temperature of ΘJ = 183ºC would be developed in its junction. Information
regarding the heat sink chosen can be seen in figure 2.14.
In Chapter 3 the main intention was to perform an investigation of the inverter's
switching behavior. This was entirely performed using P-Spice. Second objective was an
investigation regarding the usefulness of the clamp resistor.
The P-Spice model, which contained all the components that were derived in Chapter 2, was used throughout the simulations and it can be seen in figure 3.1. The model was
analyzed for each current direction separately. Throughout the switching behavior analysis
an overview of how the system works and additionally, the reason for using snubber
components were estimated. It could be seen that including a snubber capacitor, CS, for
du/dt limitation and a snubber inductor, L, for di/dt limitation constituted critical parts of
the circuit, figures 3.22 and 3.20 respectively. Moreover, the overcharging process of C0 snubber capacitor and the reverse currents caused by the free-wheeling diodes of the IGBT
units were also significantly affected the operational behavior of the system. The reverse
current caused by the diode parts of the units had to be considered since its absence could
yield completely different results. The clamped resistor investigation was supposed to be
performed using the pragmatic model of the inverter. However, due to constructional errors
this was not achieved. More information are given in Chapter 4.
Eventually, in Chapter 4 the experimental part of the thesis had to be performed. The
aim was to verify the experimental waveforms to the theoretical obtained using P-Spice.
Initially, general information about working in the laboratory were stated. Additionally, the
design process of the snubber inductor was introduced as a next step. Thereafter, a block
diagram representation of the system under investigation was presented and it can be seen
122 of 149 CONCLUSION MSc Thesis ­ Spring 2011 in figure 4.2. The chapter continued by introducing each PCB hardware whereas a briefly
explanation of their operation was also given. Conclusively, in the last section, §4.3 Experimental Results, all the obtained experimental waveforms where compared to the
results that were derived in Chapter 3. The system was achieved to be operated only at a
maximum DC voltage level of 30V. This was due to several constructional errors during the
early design of the PCB's which in turns created non ideal conditions for increasing the
voltage level. Additionally, lots of time was spent on trying to fix the aforementioned errors.
Nevertheless, most of the components yielded satisfactory results, eventhough at 30V, that
were identical to the theoretical analysis. Finally, the investigation of the clamp resistor
could not be achieved since the system was not operating satisfactorily. FUTURE WORK
As a future work, keeping the same theoretical design of the inverter, as it was
described in Chapter 2 , and rearranging of the ORCAD layout file of the inverter's PCB in
order to avoid many “manual corrections” could be a point to start with. When this is
achieved then performing the system in higher voltages could verify the results also for
400V. Additionally, since the system will exhibit a reliable operation then adding a resistor
would might show the meaning of using it.
123 of 149 REFERENCES MSc Thesis ­ Spring 2011 REFERENCES
Brendan F., Damian F., Leslie B., Jenkins N., Milborrow D., O'Malley M., Watson R.,
Anaya-Lara O., 2007, “Wind Power Integration, Connection and System Operational
Aspects”. Institution of Engineering and Technology, London.
Erickson R.W., Maksimovic D., 2001, “Fundamentals Of Power Electronics Second
Edition”, Colorado: University of Colorado Boulder.
Glover J., Sarma M., Overbye T., 2008, “ Power System Analysis and Design – Fourth
Edition”, Thomson.
In-Dong K., Eui-Cheol N., Bimal K.B., 1998, “ A new snubber circuit for Multilevel inverter
and converter”, IEEE.
Iskram M., 2010. “Electronic Circuits Design For Beginners - Chapter 5:Learn electronics
as a hobby, for industrial and home automation ” [Internet]. Version 137. Knol. Available
from:
http://knol.google.com/k/max-iskram/electronic-circuits-design-for/1f4zs8p9zgq0e/5.
Jaycar Electronics, 2000, “Understanding and Using DC – AC Inverters ”.
Mohan N., 2007, “First Course On Power Electronics”, Minneapolis: University Of
Minnesota, Department Of Electrical and Computer Engineering
Perreault D., 2007, “Power Electronic Notes”, Massachusetts Institute of Technology, MIT
open-course ware.
Rashid M. H., 2007. “Power electronics handbook: devices, circuits, and applications
Second Edition”, Elsevier, London.
Rasmussen T. W., Hansen A., Havemann H., Pedersen J. K., 2010, “ High Power
Electronics”, DTU: Department Of Electrical Engineering 2010.
Severns R., 2005. “Design of Snubbers for Power Circuits” , Cornell Dubilier Electronics.
Yang Chen, Smedley K.M., 2004, “ A Cost-Effective Single Stage Inverter With Maximum
Power Point Tracking”, IEEE Transactions on Power Electronics, Vol.19, NO.5.
Ying-Yu Tzou, 1996, “Power Electronics: An Introduction”, National Chiao Tung
University, Institute Of Control Engineering.
124 of 149 APPENDIXES MSc Thesis ­ Spring 2011 APPENDIXES
A.1 Estimation Of Junction to Ambient R TH
Figure A1.1: Thermal resistance junction to ambient versus copper surface under tab
for an epoxy PCB FR4 of 35μm copper thickness
125 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.2 N87 Inductor Core characteristics
Figure A2.1: Dynamic magnetization curves taken by material N87 data-sheet,
“EPCOS, “Ferrites & Accessories- Siferrit Material N87, 2006”
126 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.3 Observations For A Positive Current Direction
Figure A3.1: Voltage, current and power losses of IGBT unit S 4 during state “3” for a
positive current direction
127 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.4 Negative Current Direction – Waveforms
All the results presented here were obtained using the P-Spice model of the DCTLI.
The current direction was negative and they correspond to a full switching sequence as it is
dictated by table 3.1, §3.1 .
Figure A4.1: Current waveforms through IGBT units S 1 and S 2
128 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.2: Current waveforms through IGBT units S3 and S4
Figure A4.3: Voltage and current waveforms of snubber capacitor C 01
129 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.4: Voltage and current waveforms of snubber capacitor C 02
Figure A4.5: Voltage and current waveforms of snubber capacitor C S1
130 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.6: Voltage and current waveforms of snubber capacitor C S2
Figure A4.7: Voltage and current waveforms of snubber diode D 1
131 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.8: Voltage and current waveforms of snubber diode
Figure A4.9: Voltage and current waveforms of snu bber
132 of 149 D2
diode D 3
APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.10: Voltage and current waveforms of snubber
Figure A4.11: Voltage and current waveforms of cl amp
133 of 149 diode D 4
diode D cl1
APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.12: Voltage and current wavef orms
Figure A4.13: Voltage and curre nt
134 of 149 of clamp diode D cl2
of snubber inductor L 1
APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.14: Voltage and current of s nubber
inductor L 2
Figure A4.15: Voltage waveforms across IGBT units S 1 and S 2
135 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A4.16: Voltage waveforms across IGBT units S 3 and S 4
Figure A4.17: Voltage, current and power losses waveforms of IGBT unit S 1 when the
snubber capacitor C S2 is connected
136 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.5 Current Flow through lower IGBT module
a)
b)
c)
Figure A5.1: Current flowing indication through IGBT modules when a) S3 and S4 are
turned-on and current is negative b) S3 and S4 are turned-on and current is positive c) S2
and S3 are turned-on and current is positive
137 of 149 APPENDIXES MSc Thesis ­ Spring 2011 ➢ S3 and S4 are turned-on and the current is negative
2π
3π /2
1
1
I AV =
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos( x) dx
2⋅π 0
2⋅π π +α1
I AV =3,386 A
√
2π
√
3π /2
1
1
I RMS =
⋅∫ (i peak⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ ( 42,5⋅cosx)2 dx
2⋅π 0
2⋅π π +α1
I RMS =9,403 A
➢ S3 and S4 are turned-on and the current is positive
2π
2π−α1
1
1
I AV =
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos (x )dx
2⋅π 0
2⋅π 3π / 2
I AV =3,386 A
√
2π
√
2π−α1
1
1
I RMS =
⋅∫ (i peak⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ (42,5⋅cosx)2 dx
2⋅π 0
2⋅π 3π / 2
I RMS =9,403 A
➢ S2 and S3 are turned-on and the current is positive
2π
2π+α1
1
1
I AV =
⋅∫ î⋅cos( x) dx ⇒ I AV =
⋅ ∫ 42,5⋅cos (x )dx
2⋅π 0
2⋅π 2π−α1
I AV =6,757 A
√
2π
√
2π+α1
1
1
I RMS =
⋅∫ (i peak⋅cosx)2 dx ⇒ I RMS =
⋅ ∫ (42,5⋅cosx)2 dx
2⋅π 0
2⋅π 2π−α1
I RMS =16,575 A
138 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A. Conduction losses of free-wheeling diode part of units S3 and S4 when current is
negative
2
P Con=U T⋅I AV +R D⋅I RMS ⇒
P Con=(2,35 V⋅3,386 A)+(0.00139⋅9,403 A) ⇒
P ConS2=7,97 W
B. Conduction losses of IGBT parts of units S3 and S4 when current is positive
P Con=U T⋅I AV +R D⋅I 2RMS ⇒
P Con=(2,35 V⋅3,386 A)+(0.00139⋅9,403 A) ⇒
P ConS1 =7,97 W
C. Conduction losses of IGBT part of S3 unit when current is positive
2
P Con=U T⋅I AV +R D⋅I RMS ⇒
P Con=(2,35 V⋅6,757 A)+(0.00139⋅16,575 A)⇒
P ConS1=15,9W
139 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.6
Positive Current Direction – Waveforms
Figure A6.1: IC01 & IC02
Figure A6.2: ICS1 & ICS2
140 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.3: ID1 & ID2
Figure A6.4: ID3 & ID4
141 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.5: IDcl1 & Idcl2
Figure A6.6: IS1 & IS2
142 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.7: IS3 & IS4
Figure A6.8: Output voltage
143 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.9: S(IRs1) & S(IRs2)
Figure A6.10: VC01 & VC02
144 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.11: VCs1 & VCs2
Figure A6.12: VD1 & VD2
145 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.13: VD3 & VD4
Figure A6.14: VDcl1 & VDcl2
146 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.15: VL1 & IL2
Figure A6.16: VL2 & IL2
147 of 149 APPENDIXES MSc Thesis ­ Spring 2011 Figure A6.17: VS1 & VS2
Figure A6.18: VS3 & VS4
148 of 149 APPENDIXES MSc Thesis ­ Spring 2011 A.7 Evaluation of Snubber Diodes Switching Losses
➢
Snubber Diode, D2:
P SW ( D2)=1,5⋅0,40 A+0,033⋅13,84 A⇒
P SW ( D2)≃1,05W
➢
Snubber Diode, D3:
P SW ( D3)=1,5⋅0,22 A+0,033⋅6,08 A ⇒
P SW ( D3)≃0,53W
➢
Snubber Diode, D4:
P SW ( D4)=1,5⋅0,22 A+0,033⋅6,31 A⇒
P SW ( D4) ≃0,54 W
149 of 149