Datasheet SHF 423 Demux - SHF Communication Technologies AG

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SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23 • Aufgang D • 12277 Berlin – Marienfelde • Germany
Phone ++49 30 / 772 05 10 • Fax ++49 30 / 753 10 78
E-Mail: sales@shf.biz • Web: http://www.shf.biz
Datasheet
SHF 423 Demux
60 Gbps Demultiplexer Module
Description
The SHF 423 is a 1:4 demultiplexer operating at data rates up to 60 Gbps for use in SONET OC768 and SDH STM-256 applications, broadband test setups, and telecom transmission systems. A
60 Gbps single ended serial data stream is accepted by the demultiplexer and converted into four
single ended data signals at a nominal output data rate of 15 Gbps. A single ended clock signal
(nominally 30 GHz) with a frequency half of the input data rate drives the SHF 423, and a copy of
the divided input clock (with a nominal frequency of 15 GHz) is provided as an output signal to
drive succeeding circuits or an error analyzer. Data and clock outputs are DC-coupled ground
referenced CML signals with on-chip 50 Ω terminations. The data and clock inputs are AC-coupled
and also include 50 Ω terminations.
Features
SiGe HBT technology
Supports input data rates from 2 Gbps up to 60 Gbps
Low power consumption: 3.5 W typ.
Dual power supply with internal voltage regulator ±5 V
V-type connectors for the 60 Gbps data input
K-type connectors for the data outputs and clock in-/outputs
SMB-type connectors for the clock/data bias inputs
Applications
SONET OC-768 and SDH STM-256 applications
Broadband test setups
Telecom transmission systems and transponder prototyping
Option
Option BA: two potentiometers to allow data bias and clock bias to be adjusted without the
need for additional power supplies.
Functional block diagram
50
Data
Bias
A
1:2
C
50
Data
1:2
50
B
1:2
D
50
CL
50
:2
CL/2
Clock
Bias
SHF reserves the right to change specifications and design without notice - SHF 423 - Rev. 1.4 - 13/SEP/2004
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Specifications – SHF 423 DEMUX
Parameter
Unit
Min.
Gbps
2
Typ.
Max.
Conditions
Input parameters
Data bit rate
Data eye amplitude
mV
Sensitivity
mV
Return loss
dB
60
1000
50
150
<55 Gbps
<60 Gbps
-10
Output parameters
Data bit rate
Gbps
0.5
15
Voltage high level
mV
0
Voltage low level
mV
-300
Eye amplitude
mV
Rise time
ps
15
20
(20%...80%)
Fall time
ps
15
20
(20%...80%)
RMS jitter
ps
1
Return loss
dB
250
single ended
-250
300
single ended
single ended
-10
Clock parameters
Input level
mV
400
Clock phase margin
deg
200
160
Input return loss
dB
Clock/2 output level
mV
Clock/2 output return loss
dB
1000
<50 Gbps
<60 Gbps
-10
300
350
-10
Power requirements
Negative supply voltage
V
-6.5
-5.0
Negative supply current
mA
600
Positive supply voltage
V
+5.0
Positive supply current
mA
20
Total power dissipation
W
3.5
650
700
+6.5
Note: SHF also supplies adjustable delay lines for clock-data alignment purpose. See SHF
application note AN423-1 for 1:4 demultiplexing operation setup.
SHF reserves the right to change specifications and design without notice - SHF 423 - Rev. 1.4 - 13/SEP/2004
Page 3/6
Output waveforms
Eye Diagram at 10.75 Gbps
31
(43 Gbps input data rate), PRBS 2 -1
Clock/2 Output at 43 Gbps input data rate
Eye Diagram at 12.5 Gbps
31
(50 Gbps input data rate), PRBS 2 -1
Clock/2 Output at 50 Gbps input data rate
Eye Diagram at 15 Gbps
(60 Gbps input data rate), PRBS 231-1
Clock/2 Output at 60 Gbps input data rate
Measured using Agilent DCA 86100B, sampling module 83484A [50 GHz], precision timebase module
86107A, 0.5 m microwave cable assembly, 10 dB attenuator
SHF reserves the right to change specifications and design without notice - SHF 423 - Rev. 1.4 - 13/SEP/2004
Page 4/6
Sensitivity
150
Sensitivity [mV]
125
100
75
50
25
0
0
10
20
30
40
50
60
50
60
Input Bit Rate [Gbps]
Clock phase margin
350
Clock Phase Margin [degree]
300
250
200
150
100
50
0
0
10
20
30
40
Input Bit Rate [Gbps]
The results presented above represent the performance of a typical device
SHF reserves the right to change specifications and design without notice - SHF 423 - Rev. 1.4 - 13/SEP/2004
Page 5/6
Module outline
7,1
8,6
9,1
21
13
7,2
9,5
10,3
Clock
Bias
A
36
+ 5V
- 5V
C
9,5
B
Clk/2
19,3
9,3
19
26,5
Data
Bias
D
Clk
SHF 423
DEMUX
Data
10,6
18
28
38
48
26
Ø3(4x)
16,7
Please ensure that adequate cooling
of the multiplexer is guaranteed. We
recommend a heat sink with a thermal
resistance of approx. 3 K/W
Port
A
Connector
K
B
K
C
K
D
K
Clk
K
Clk/2
K
Data
V
Clock
Bias
SMB
Data
Bias
SMB
3
3
63
Bottom view
10,6
66
10,3
All dimensions in mm
SHF reserves the right to change specifications and design without notice - SHF 423 - Rev. 1.4 - 13/SEP/2004
Page 6/6
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