LECTURE SUPPLEMENT #5 . . . [LS #5]
CHAPTER #05
MOSFET Biasing Networks
Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
213–740–7581 [USC Fax]
818–384–1552 [Cell]
johnc@usc.edu
PRELUDE:
This chapter establishes the circuit concepts and circuit design strategies that underpin practical
biasing networks suitable for use in high performance, MOSFET technology analog integrated
circuits. We shall begin with an abridged review of the preceding chapter so that a strong technical foundation is forged to support the development of a family of practical biasing networks.
We shall see that these structures range from simple voltage references and current mirrors to
networks boasting biasing that is rendered nominally independent of supply voltages. Included
among the topical issues addressed in this chapter are conventional and low voltage reference
circuits, traditional and advanced high performance current sources and sinks, regulated current
sinks, and networks that feature constant or electronically tunable forward transconductances.
July 2013
Chapter 5
MOSFET Biasing
5.1.0. INTRODUCTION
As we have noted with BJT technology, biasing is a fundamental and often challenging
design task that pervades all analog circuit design initiatives. Biasing subcircuits establish the
necessary quiescent operating conditions that allow an active network comprised of interconnected and inherently nonlinear transistors and other active devices to deliver nominally linear
input/output (I/O) performance for given input signal environments and output load conditions.
Biasing networks are also designed to deliver the static transistor currents and voltages that are
deemed essential to support gain, bandwidth, linearity, I/O impedances, transient settling time,
standby power dissipation, and other targeted performance objectives.
In a reliable and reproducible analog network, the desired characteristics of the biasing
circuit must be sustained despite unavoidable changes in semiconductor operating temperatures
and the non-ideal nature of the utilized power supplies. For example, even relatively small drain
currents conducted by deep submicron MOSFETs can give rise to large device current densities
that foster significant internal device heating. The preceding chapter taught us to appreciate the
effects of the temperature sensitivities of carrier mobilities, threshold potentials, and other
transistor variables and parameters. As a result, it is only logical to expect the quiescent currents
and voltages established in our biasing networks to be vulnerable to temperature fluctuations unless we take care to implement creative and reliable thermal compensation schema. Moreover,
the portability culture in which we reside makes us mindful that batteries serving as the power
line voltage are not ideal sources of constant voltage. These battery voltages degrade quickly
with time, especially if the networks in which these batteries are deployed conduct relatively
large standby currents. Since it is an annoyance to be compelled to replace or recharge batteries
as soon as their voltages decrease by 10%, 20%, or even 50%, we must be prepared to design
biasing circuits whose static responses are not overly sensitive to voltage supply levels. Stated in
another way, our biasing designs must boast sufficiently high power supply rejection, or PSR.
Yet another issue that responsible circuit designers must address is that the quiescent currents and voltages forged by our biasing structures must be impervious to a plethora of engineering uncertainties. Such uncertainties include those that are associated with the physical and
geometric parameters implicit to the mathematical models of our active devices. To wit, a
reference output voltage that is directly proportional to carrier mobility is a less than laudable
accomplishment because mobilities are temperature dependent. Moreover, an accurate numerical delineation of carrier mobilities at any specific operating temperature or voltage is a challenge because of their functional dependence on numerous semiconductor variables that are obscure, nebulous, or simply difficult to monitor or measure. Additionally, manufacturing and
processing uncertainties plague passive circuit components, the matching accuracy among similar active devices produced by foundry processes, and the lossy parasitics associated with circuit
layout and packaging.
This chapter explores biasing cells that are commonly used in high performance analog
integrated circuits. Our discussion begins with an analysis of a simple voltage reference scheme
that is often adopted in conjunction with the realization of high impedance current sinks and
sources. We shall examine the viability of this and alternative schemes to function as a reliable
and predictable voltage and current references for arbitrary load terminations. The simple voltage reference configuration is subsequently extended to embrace the design requirements of minimal quiescent operating point sensitivity to temperature and variations in power line (battery)
voltages. Circuits that reliably bias transistors for constant and predictable forward transconduc- 405 -
Chapter 5
MOSFET Biasing
tance are addressed, as are topologies boasting improved current source and current sink impedance properties.
As a foundational prelude to our bias circuit discussions, the salient features of the
static volt-ampere characteristics of MOSFETs, which we addressed in the preceding chapter, are
reviewed. The analytical comfort level that hopefully derives from this review is indispensable
because mathematically tractable analyses serving to complement ultimate computer-aided circuit studies demand reasonable and insightfully understood device modeling approximations.
We shall also focus on the transient responses of biasing networks subjected to the sudden
application or removal of static power. This focus is important because the transients associated
with circuit startup or even shutdown can prove to be destructive to sensitive, deep submicron
transistors.
5.2.0. STATIC MODEL OF A MOSFET
Figure (5.1) gives the circuit schematic symbol of both n-channel and p-channel transistors. In this diagram, we explicitly show the bulk terminals appropriately connected so that bulksource and bulk-drain PN junctions intrinsic to the utilized transistors are reverse biased. In
other schematic representations, we may choose not to show these bulk terminal connections.
Regardless and unless stipulated otherwise, we presume that bulk connections are made to ensure
the reverse biasing of PN junctions internal to the transistor.

Vgd


Vgs

Id

Vsg


Vdg


Vds
To Min. 
B
(a).
To Max.
B 
Vsd
Id

(b).
Figure (5.1). (a). Schematic symbol of an NMOS transistor in which the positive
reference polarity convention for drain current and both gate-source
and drain-source voltages are delineated. (b). Schematic symbol of
a counterpart PMOS transistor. In both diagrams, the bulk substrate
terminals are presumed incident with signal ground.
Figure (5.1a) delineates the positive reference polarity conventions for the drain current, Id, the gate-source voltage, Vgs, the drain-source voltage, Vds, and the gate-drain voltage,
Vgd, are indicated. Unless otherwise specified, we assume that the substrate terminals of the ptype bulk of NMOS devices are connected to the smallest of available circuit potentials, which
we indicate in the figure as “Min. B−”. If these minimal and possibly negative circuit potentials
are constant, the bulk terminals lie at signal ground. For the p-channel device in Figure (5.1b), it
is more convenient to cast the static volt-ampere characteristics in terms of the source-gate voltage, Vsg, the source-drain voltage, Vsd, and the drain-gate voltage, Vdg. We assume that the substrate terminals of the n-type bulk of all PMOS devices are incident with the most positive of
available circuit potentials, which we delineate in the figure as “Max. B+”. To the extent that
these maximum potentials are constant, the bulk nodes of PMOS transistors, like those of NMOS
devices, are connected to signal ground. At this point in our electronic circuit travels, we should
easily remember that positive drain current flows into an NMOS device, while positive drain cur- 406 -
Chapter 5
MOSFET Biasing
rent flows out of a PMOS transistor.
In Figure (5.1a), let Vhn designate the threshold voltage of the NMOS transistor. If the
transistor is biased for operation in its saturation regime where Vds ≥ Vdsat ≈ Vgs − Vhn, the simple
square law, Schichman-Hodges model relating the drain current to the applied gate-source voltage is
2
2
 μ C W 
 K W 
I d   no ox    Vgs  Vhn
  n    Vgs  Vhn ,
(5-1)
 2  L 
 2  L 
where μno is the mobility of free electrons in the inverted channel immediately below the oxidesemiconductor interface. Specifically, μno is the carrier mobility when lateral electric field
intensities induced in the channel by applied drain-source voltages are much smaller than the
critical field intensity, which is in the neighborhood of 5 V/μm. Continuing, (W/L) is the gate
width to drawn channel length ratio, or simply, gate aspect ratio. Parameter Cox symbolizes the
density of the capacitance associated with the gate oxide layer, is
Cox  εox Tox .
(5-2)
In (5-2), εox is the dielectric constant of silicon dioxide (345 fF/cm), while Tox is the average
thickness of the insulating gate oxide.




The companion volt-ampere relationship for the saturated p-channel transistor in Figure
(5.1b) is
 μ poCox   W 
 K p W 
2
2
Id  
 
(5-3)
   Vsg  Vhp
   Vsg  Vhp ,
 2  L 
 2  L 
which requires Vsd ≥ Vsg − Vh. In this relationship, μpo is the low field value of the mobility of
free holes in the inverted channel. Note that the gate-source voltage, Vgs, in (5-1) is replaced by
the source-gate voltage, Vsg. The replacement of Vgs by Vsg allows threshold voltages Vhn in (5-1)
and Vhp in (5-3) to be couched as positive voltages. We recall that the threshold voltage in MOSFETs operated without the source terminal connected directly to the bulk terminal modulates
minimally for thin gate oxide layers.




It is expedient for us to write the volt-ampere equations in (5-1) and (5-3) in the forms,


2
β p Vsg  Vhp 
I d  βn Vgs  Vhn
Id 
2
for NMOS
,
(5-4)
for PMOS
where
μnoCox  W 
Kn  W 
  
  for NMOS
2 L
2 L
(5-5)
.
μ poCox  W 
Kp W 
βp 
  
  for PMOS
2 L
2 L
We observe that the introduced transconductance coefficient parameters, βn and βp, which have
dimensional units of mhos/volt, scale linearly with gate aspect ratio, W/L.
βn 
The compact static volt-ampere equations in (5-4) show that for given threshold voltage, gate aspect ratio, gate oxide capacitance density, and channel carrier mobility, the drain
current is determined exclusively by one voltage variable; namely, gate-source voltage Vgs in
NMOS and source-gate voltage Vsg in PMOS. The lack of drain current dependence on drain- 407 -
Chapter 5
MOSFET Biasing
source or source-drain voltage means that the electrical characteristics of the drain-source port of
a MOSFET are modeled as an ideal current source. In other words, (5-4) suggests that the drain
current can be represented as an ideal, albeit nonlinear, voltage controlled current source, with
either Vgs or Vsg serving as the controlling voltage. Since the gate terminal is incident with an
insulating oxide layer serving as an interface between the gate contact metallization (or polysilicon) and the semiconductor surface, the gate conducts zero static current. Accordingly, the
drain-source terminal pair emulates an ideal voltage controlled current source, as inferred by the
simple models offered in Figure (5.2). In short, the simple static model of (5-4) stipulates that
when MOSFETs operate in their saturation regions, their drain currents are functionally dependent, albeit to first order, on only gate-source voltages. Conversely, a current forced to flow in
the MOSFET drain establishes, by virtue of (5-4), a unique gate-source potential. We should
note further that if both the NMOS and PMOS devices are operated to conduct a fixed static
drain current, progressively larger gate aspect ratios result in a gate-source (or a source-gate) voltage that approaches threshold value.
Drain
Source


Id


V
V
gd
Vds

Vgs


Drain
Id = n (Vgs  Vhn )
2

Vgd

Gate

Vgs

Source
Vsd

Id
Source

Vsg

Gate

Vdg

Drain

Vds

(a).
2
Source

Gate

Vdg

Drain
Id = p (Vsg  Vhp )
Gate
sg


Vsd

(b).
Figure (5.2). (a). Simplified static model of an NMOS transistor biased for operation in saturation. The drain current, Id, is exclusively a function of the gate-source voltage,
Vgs. (b). Simplified static model of a PMOS transistor biased for operation in
saturation. To first order the drain current, Id, is exclusively a function of the
source-gate voltage, Vsg. The ground connection at the bulk terminals of both devices indicates signal ground only.
5.2.1. TEMPERATURE SENSITIVITY
In contrast to a BJT, whose static collector current exhibits positive temperature coefficient, the static volt-ampere characteristics of a MOSFET display negative temperature sensitivity. In other words, for constant gate-source or source-gate voltages, the observed drain current
decreases with increasing interfacial operating temperatures. Two principle phenomenological
reasons contribute to the negative temperature coefficient of a MOSFET. The first of these derives from the fact that the carrier mobility in the inverted channel of a transistor decreases nominally as a three-halves power law of absolute temperature. In particular,
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Chapter 5
MOSFET Biasing
32
T 
(5-6)
μ(T)  μ(To )  o 
,
T 
where μ(T) designates electron mobility μno in NMOS or hole mobility μpo in PMOS at any arbitrary absolute temperature, T. On the other hand To is the reference temperature at which the
reference mobility value, μ(To), is extracted. Since parameters βn and βp in (5-5), to which the
drain currents in (5-4) are proportional, are linear functions of carrier mobility, the immediate
effect of increased operating temperature is clearly a diminished drain current.
In addition to a temperature-induced degradation of mobility, the threshold voltage of a
MOS technology transistor increases with temperature. This threshold potential increase further
diminishes the drain current observed for a given gate-source voltage at increasing operating
temperatures. The positive temperature coefficient of threshold voltage derives from its intimate
dependence on the Fermi potential, which effectively defines the oxide-semiconductor interface
potential corresponding to the onset of channel inversion in a MOSFET. To first order,
 T T 

V (T )  V 
ho  V 
o,
(5-7)
V (T)  V (T )   2  h o
h
h o
F


2V
T



F
 o 
where Vh(T) is the threshold voltage value of either NMOS or PMOS at absolute temperature T,
and the Fermi potential, VF, is given by
N

(5-8)
VF  VT ln  sub  .
 ni 
In the last expression, Nsub denotes the impurity concentration in the substrate (acceptor
concentration for NMOS and donor concentration for PMOS), ni is the intrinsic carrier
concentration of silicon, and VT is the familiar Boltzmann voltage. But VF itself varies with
temperature owing to two well-known facts. In particular, VT is linearly dependent on absolute
temperature and ni nominally increases by as much as two to four fold for each 10 °C increase in
operating temperature. When due consideration is given to mobility and threshold effects, the
sensitivity of the drain current to absolute temperature is found to be
0.25 
3
I d I d
4VF  T 
Id

.
 

ST 
(5-9)
 
2

T T
T
Id β  o 


In (5-9), β = βn for NMOS, β = βp for PMOS, and it is understood that VF, Id, and β in the bracketed factor on the right hand side are each evaluated at the reference temperature, To. The first
term in the bracketed quantity derives from the temperature dependence of carrier mobility,
while the second term within the bracketed quantity reflects threshold voltage sensitivity to
temperature. Accordingly, the per-unit, or percentage, change in drain current induced by a
specified percentage change in operating temperature is negative and larger in magnitude than
1.50. We note, however, that for progressively larger drain currents, the temperature sensitivity
of drain current tends toward a constant of (−1.50).
EXAMPLE #5.1:
In an attempt to dramatize the foregoing temperature issues, consider an
NMOS MOSFET having a substrate impurity concentration of Nsub = 1015
atoms/cm3. At a reference temperature of To = 27 °C = 300.16 °K, the
MOSFET, which is biased for a drain current of Id = 1 mA, delivers βn =
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MOSFET Biasing
50 mmhos/volt, and a threshold voltage of Vhn = 400 mV. Assume a reference temperature intrinsic carrier concentration of 1010 atoms/cm3. Determine the requisite gate-source voltage, Vgs, such that the room temperature, 1 mA value of drain current is sustained at an elevated operating
temperature of 75 °C.
SOLUTION #5.1:
(1).
From (5-4), the gate-source voltage commensurate with 1 mA of drain current at 27 °C is,
with βn = 50 mmhos/volt and Vhn = 400 mV, Vgs = 541.4 mV. Also, at To = 27 °C = 300.16
°K, the Boltzmann voltage, VT, is
kTo
(E1-1)
VT 
 25.88 mV ,
q
where k = 1.38(10−23) joules/°K is Boltzmann’s constant, and q = 1.6(10−19) coulombs is the
magnitude of electron charge. For Nsub = 1015 atoms/cm3 and ni = 1010 atoms/cm3 at 27 °C,
the Fermi potential in (5-8) is VF = 297.9 mV at the reference temperature.
(2).
Using (5-7), the threshold voltage increases to Vhn = 495.3 mV at T = 75 °C = 348.16 °K,
which is an increase of almost 24%. Appealing to (5-6), the ratio of the carrier mobility at
348 °K to the carrier mobility at 300 °K is
3 2
3 2
μ(T)
T 
 300 
(E1-2)
  o
 
 1 1.249 .

μ(To )
 348 
T 
Since parameter βn is directly proportional to carrier mobility, βn decreases by a factor of
1.249 to a 75 °C value of βn = 40.02 mmhos/volt.
If a biasing circuit were to be implemented to deliver constant gate-source voltage to the
transistor of present interest, βn = 40.02 mmhos/volt, Vhn = 495.3 mV, and Vgs = 541.4 mV
(the gate-source voltage value computed at 27 °C), the drain current in (5-4) becomes Id =
85.03 μA. This revised current level is a decrease from the original drain current value by a
whopping factor of almost 12! On the other hand, sustaining a 1 mA drain current in the face
of the foregoing temperature-induced perturbations in parameter βn and threshold voltage Vhn
requires an updated gate-source voltage of Vgs = 653.4 volts. In other words, the gate-source
voltage must increase by 20.7% over the 48 °C increase in operating temperature.
ENGINEERING COMMENTARY:
This example teaches that the temperature-induced effects on the drain current conducted by
a MOSFET biased in saturation can be substantial. In the present case, the factor of 12 decrease in quiescent drain current is certainly large enough to motivate significant concern as
to the ability of the circuit in which the considered MOSFET is embedded to sustain performance specifications over the stipulated 48 °C rise in operating temperature. The design lesson learned is that if the desired signal performance of a circuit is critically dependent on
quiescent current level, constant gate-source voltage is not a prudent bias design strategy.
In the present case, the gate-source voltage that sets the drain current on the subject transistor
must increase by 20.7% over the 48 °C rise in temperature. While this requirement may appear foreboding, it reflects realistic biasing compensation. To place this contention into
engineering perspective, the requisite increase in gate-source voltage, say Vgs, is Vgs =
Vgs(75 °C) − Vgs(27 °C) = 112.0 mV, which amounts to an average temperature rate of voltage increase of 2.33 mV/°C. Thus, the incorporated biasing compensation must sense
temperature (perhaps by sensing current). In response to this sensing, it must then increase
the gate-source bias by about 2.33 mV for every degree centigrade increase in temperature.
This mandated average increase is indeed a reasonable design goal for properly designed
biasing compensation. As a general rule, the majority of MOSFETs achieve nominally
(3).
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MOSFET Biasing
temperature invariant drain current when the applied gate-source voltage is made to increase
at a rate in the range of 1.5 mV/°C to 2.5 mV/°C. Interestingly enough, the +2.33 mV/°C
requirement computed in this example differs only slightly from the average temperature rate
at which the base-emitter biasing voltage applied to a BJT must decrease to preserve constant
static collector current.
5.2.2. IMPROVED STATIC MODELS
We should remain mindful of the fact that the static volt-ampere characteristics given
by (5-4), which we shall invoke habitually in our first order, design-oriented circuit analyses, are
only first order approximations of the static characteristics we actually observe and monitor in
the laboratory. Unfortunately, the deviations between first order theoretic predilections and
engineering observations are aggravated as devices are scaled to deep submicron dimensions.
The primary shortfalls implicit to (5-4), insofar as static circuit responses of minimal geometry
transistors are concerned, are the neglect of channel length modulation (CLM), bulk-induced
threshold modulation (body effect or BITM), carrier mobility degradation induced by lateral
electric fields, and, to a somewhat lesser extent, drain induced barrier lowering (DIBL). The circuit level influence of these and other high order MOSFET phenomena are best studied via
computer-aided investigations that exploit device models more advanced than are those premised
on long channel simplifications. But it is important that we perform these computer-based studies only after we execute an insightfully understood manual analysis with our relatively simple,
first order transistor models so that we can understand and appreciate the quantitative impact of
high order phenomenology. Such understanding and appreciation are vital prerequisites for
enabling our creative abilities that implement circuit compensation or outright circuit architectural changes. In effect, the fundamental goal of such circuit enhancements and alterations is to
render high order, and generally poorly controlled, phenomenology inconsequential to the task of
meeting our design targets.
Although we have pondered the aforementioned modeling shortfalls in the preceding
chapter, it is prudent to itemize their respective circuit level effects before undertaking our design-oriented investigation of MOSFET biasing networks.
5.2.2.1. Channel Length Modulation
Three fundamental effects of CLM are observed in short channel MOS technology
transistors. The first of these is a slight positive slope to the saturated volt-ampere characteristics, which is rendered transparent by Figure (4.17). This slope is inversely proportional to the
channel length modulation voltage, Vλ, and thus, it is functionally related to the drawn channel
length, L. It manifests a drain current that is slightly larger than the drain current predicted by
the square law model in (5-4). The additional drain current is a nominally linear function of the
excess drain-source voltage, (Vds − Vdsat)1; in particular for NMOS,

2
V V
dsat  .
 1  ds
(5-10)
I   V V
d
n gs
hn 

V





1
The focus here is on NMOS transistors. But similar statements apply to PMOS transistors, where we could
minimize the impact of channel length modulation by setting the source-drain biasing voltage, Vsd, to a value that is
close to the source-drain saturation voltage. While we shall generally address modeling issues in the context of
NMOS transistors, we shall understand that, subject to minor notational differences, our assertions apply equally
well to PMOS transistors.
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MOSFET Biasing
We understand by (5-10) that biasing an NMOS transistor at a drain-source voltage
that is only slightly larger than its drain-saturation voltage minimizes the circuit-level impact of
CLM. Of course, setting the drain-source voltage close to the drain saturation voltage limits the
amount of signal swing that can be tolerated at the drain port while maintaining a specified
linearity target. Alternatively, CLM is inconsequential in transistors featuring long channel
lengths. To be sure, long channel lengths generally require correspondingly large gate widths,
which combine with these long channel lengths to produce increased device capacitances and
therefore, potentially reduced circuit bandwidths. But in biasing circuits, which operate in the
steady state at zero frequency, bandwidth is not an important metric. Indeed constrained bandwidths in biasing structures often prove advantageous from the viewpoint of avoiding excessively underdamped biasing responses to a bus line voltage that is applied suddenly.
The second effect of CLM is that the large signal model evidenced at the drain-source
port of a MOSFET is no longer an ideal current source controlled nonlinearly by applied gatesource voltage. Instead, the output port now appends a shunting resistive branch across the subject voltage controlled current source. Unfortunately, the appended resistance is nonlinearly related to both drain-source and gate-source voltages, which generally motivates our defaulting to
computer-aided analysis whenever CLM looms significant. However, the appended resistance is
large in devices that have large channel lengths and/or operate at low saturation currents.
Finally, CLM alters the small signal performance of a MOSFET by imposing a channel
resistance (ro) across the drain-source port of a MOS technology transistor. As is confirmed in
the preceding chapter, this resistance shunts the drain-source signal current source, which is controlled by applied gate-source signal voltage. The resistance shunting impinges on small signal
MOSFET performance in two ways. First, it reduces the achievable I/O gain because the appended resistance places an additional load between drain and source terminals in an amplifier.
Second, it establishes a finite resistance at the drain output port, as opposed to the infinitely large
driving point output resistance manifested at the drain port by the long channel approximation.
Thus, while the Schichman-Hodges model affords a common source amplifier that behaves as an
ideal transconductor, in the senses of infinitely large input and output impedances at low signal
frequencies, CLM brings such a transconductor into non-ideal state of engineering reality.
5.2.2.2. Bulk-Induced Threshold Modulation
Bulk-induced threshold modulation (BITM) incurs both large signal and small signal
effects. From the large signal perspective, the body effect increases the threshold voltage of a
MOSFET as a nonlinear function of the reverse bias imposed across the bulk-source PN junction. In extreme situations, this means that if the subject reverse bias includes a signal component, it is possible that sufficiently large signals can incur intermittent or aperiodic cutoff of the
transistor. Such an extreme can materialize, for example, if the gate aspect ratio is so large that a
desired drain current can be sustained when the gate-source voltage is ever so slightly above the
threshold potential. At a minimum, threshold voltage perturbations induced by large signal
swings can exacerbate nonlinearity problems, despite the care ostensibly taken to pin the quiescent operating point of the transistor in a reasonably linear region of its characteristics curves.
We remember that BITM is minimal for thin gate oxide layers.
From a small signal perspective, Figure (4.22), with the help of (4-172) and (4-173),
confirms that the body effect establishes a controlled current source in shunt with the drainsource terminals of a MOSFET. Depending on the nature of the bulk-source signal voltage, this
additional controlled source changes the I/O gain of an amplifier. And if the bulk-source signal
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MOSFET Biasing
voltage is nonzero, it can alter appreciably the driving point output impedance seen looking into
the transistor drain. We note again from (4-173) that a thin gate oxide reduces the net
transconductance associated with the additional voltage controlled current source in the drain circuit. But an even more important observation is that if this additional controlled source is
significant to the enumeration of gain and/or output impedance, there is cause for design
concern. In particular, a significant effect on the small signal characteristics implies that body
effect has a similarly significant influence on static MOSFET responses, which bodes poorly
from an I/O linearity perspective.
5.2.2.3. Carrier Mobility Degradation
The immediate impact of carrier mobility degradation induced by the lateral electric
fields caused by drain-source voltages is a reduction of the drain saturation voltage. This effect
is highlighted and analytically addressed by (4-130) through (4-133). These relationships show
that the reduction in drain saturation current is minimal for long channel lengths. A reduced
drain saturation voltage is actually good news in that it enables us to bias the transistor at
progressively smaller drain-source voltages while sustaining saturation regime operation. But
carrier mobility degradation reduces the drain current, which is to say that progressively larger
gate-source biases are required to offset this current reduction. Obviously, increased gate-source
voltage causes an increase in drain saturation voltage.
5.3.0. CURRENT SINKS AND SOURCES
Current sinks and sources are ubiquitous in analog networks. One reason that
underpins the popularity of these subcircuits is that the forward transconductance, drain-source
channel resistance, and several other low and high frequency parameters in the small signal
transistor model are dependent on quiescent transistor currents. In an attempt to minimize
network nonlinearities, it is incumbent on us to keep quiescent variables as constant as possible,
which is to say that it is desirable to derive critical static currents from nominally ideal sources or
sinks of constant current. Additionally, and as we witnessed in the preceding chapter, a constant
tail current in a balanced differential amplifier not only keeps pertinent small signal transistor
parameters constant, but its value also sets the allowable input signal amplitude that affords
acceptable linearity.
5.3.1. SIMPLE CURRENT MIRROR
We commence our present discussion by studying the current mirrors offered in Figure
(5.3). We shall analyze only the NMOS mirror in Figure (5.3a). The analysis of the PMOS mirror in Figure (5.3b) proceeds along the same lines as that of its NMOS counterpart and is left as
an exercise for the reader.
In both of the two circuit diagrams before us, input current Iref is often realized as an off
chip current source. In light of the design flexibilities afforded by discrete, off the shelf components, we can view this branch element as an ideal, constant current source having infinitely
large terminal impedance. While voltage Vdd is presumably larger than node voltage Vkk, we assume Vkk is large enough to ensure that transistor M2 operates in its saturation domain. In the
case of transistor M1, saturation is assured because of the indicated electrical connection of its
gate and drain terminals. From a cataloguing perspective, we usually think of the NMOS mirror
as a current sink in that the drain current, Ik, flows into ground from a general branch element
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Chapter 5
MOSFET Biasing
that is not delineated in the figure. On the other hand, the PMOS mirror is viewed as a current
source since drain current Ik flows into a general branch element, which is also not delineate din
the subject figure.
Vdd
Vkk
V 
Iref
x k21
x 1 Id1


Ik
ref
M1
M2
x 1 Id1
Rout
M2
x k21
Iref
Vref M1

Vdd
(a).
Ik
(b).
Rout
Vkk
Figure (5.3). (a). Schematic diagram of an NMOS current mirror. (b). The PMOS counterpart to the NMOS current mirror. In both diagrams, the gate aspect ratio of
transistor M2 is larger than that of transistor M1 by a factor of k21.
In Figure (5.3a), the drain-source voltage, Vds, of transistor M1 is identical to its gatesource bias, which we indicate as Vref. This means that the drain saturation voltage of this
transistor, Vdsat1, is Vdsat1 = (Vref − Vhn) = (Vds1 − Vhn). Note that as we inferred in the preceding
paragraph, this transistor operates in saturation in that the inequality, Vds1 > Vdsat1 = (Vgs1 − Vhn)
= (Vds1 − Vhn), is clearly satisfied. Because the gate of a MOSFET conducts no quiescent current, Iref is identical to the drain current, Id1 of M1. Accordingly, (5-10) yields
2
V 
 1  hn  ,
(5-11)
I  I
  V V
d1
ref
n1 ref
hn 
V 
 

where we have not bothered to differentiate between the two transistor threshold voltages and the
two channel length modulation voltages. We have adopted this tack because the two NMOS devices are monolithic transistors that are physically identical. We include identical channel
lengths in this physical restriction, but we do allow geometrical differences between their respective gate widths and thus, their corresponding gate aspect ratios. In case before us, the gate aspect ratio of transistor M2 is k21-times the gate aspect ratio of M1. Moreover, both transistors
return their source and bulk terminals to ground, thereby negating BITM. Thus, the two transistors function with the same threshold voltages. Since drain induced barrier lowering (DIBL) affects the threshold voltage, the latter statement presumes negligible or identical DIBL in both
transistors.


We note now that the circuit architecture forces the gate-source voltage, Vgs2, of transistor M2 to be identical to Vgs1, which is, of course, the previously introduced voltage, Vref. Thus,
V V V 
2
ref
hn
 1  kk
,
(5-12)
I
V V
 I  
d2
k
n2 ref
hn 

V



But from (5-5),

 n2
 n1
 k
21

.
(5-13)
It follows from (5-11) and (5-12) that
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Chapter 5
MOSFET Biasing
V V V 

ref
hn
 1  kk

V



I  k I 
.
k
21 ref
V


1  hn


V



(5-14)
In earlier chapters, we repeatedly asserted that the fundamental purpose of circuit
analysis is not necessarily to arrive at an accurate response result. Instead, we advanced the
pedagogy that the fundamental purpose of circuit analysis is to arrive at tractable results that provide insights as to how the considered circuit might be designed to deliver consistently reliable
and reproducible high quality responses. To these ends, the work we executed to generate (5-14)
comprises an excellent example of the engineering assessment task that will consistently confront us as we consider subsequent, and inevitably more complex, networks.
To the foregoing end, (5-14) is hardly a precise result for output current Ik, since we
have invoked a simple square law model for MOSFET volt-ampere characteristics, embellished
only for a first order account of channel length modulation. We do notice, however, that for
large Vλ, which is achieved for long drawn channel lengths, current Ik collapses approximately to
k21Iref. This means that since k21 is a reliably deterministic ratio of device gate aspect ratios, Ik
mirrors constant current Iref within a predictable scale factor of k21. In a word, as long as the off
chip reference current, Iref, remains constant, output current Ik stays constant, independent of
power line voltage Vdd, transistor threshold voltage, and all other transistor parameters and
operating temperature. In turn, the numerical value of current Ik is set by a reliable and predictable ratio of gate aspect ratios.
Unfortunately, there are potential issues concerning scale factor k21, which derives directly from (5-13). In particular, the transconductance coefficient, βn, is directly proportional to
carrier mobility. As we witnessed in the preceding chapter, the mobility of carriers in the inverted channel of an NMOS transistor is determined by the intensity of the drain to source electric field, which in turn is a monotonically increasing function of the applied drain-source voltage. In Figure (5.3a), the drain-source (as well as gate-source) voltage applied to transistor M1
is the voltage, Vref, while for M2, the drain-source bias is an invariably larger voltage, Vkk. If indeed Vkk > Vref, the electric field intensity in the drain-source channel of M2 exceeds the electric
field intensity in which the inverted channel of transistor M1 is immersed. This means that the
carrier mobilities in M1 and M2 are not identical, thereby rendering (5-13) an approximation. A
reasonable rectification of this dilemma does not necessarily require that Vkk be identical to voltage Vref, for carrier mobility is not overtly sensitive to voltage. But it is only sensible for us to
attempt to ensure that voltage Vkk is not excessively larger than Vref. In addition to reducing the
disparity between carrier mobilities in the two NMOS transistors, a secondary benefit of securing
Vkk in the neighborhood of Vref is that the parenthesized quantity on the right hand side of (5-14)
collapses nearly to one. In short, channel length modulation phenomena are rendered virtually
inconsequential.
Another valuable metric for assessing the quality of a current source or current sink is
the output resistance, Rout, which it presents to its output port. This output resistance is foundational to an assessment of the power supply rejection of a current sink. It tells us the amount, say
Ik, by which the presumably constant current, Ik, changes when applied voltage Vkk is perturbed
by the amount, Vkk. The voltage fluctuation may be the result of signal spurs, electrical noise,
poor regulation, or other offending conditions that contaminate the line supporting voltage Vkk.
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Chapter 5
MOSFET Biasing
Moreover, if Vkk and Ik are small, which we expect them to be in a well-designed biasing
environment, we can stipulate the linear constraint,
 Vkk
I k 
.
(5-15)
R
out
Equation (5-15) boasts two important engineering ramifications. The first of these is that if output resistance Rout is known, the perturbation, Ik in current caused by a given change (parasitic
or otherwise), Vkk, in voltage can be straightforwardly enumerated. The second ramification is
that if Vkk and Ik are small, output resistance Rout derives from a simple, low frequency, small
signal analysis that culminates in the computation of the voltage to current ratio, Vkk/Ik. Because of our presumed linearity between Vkk and Ik, we note that this ratio does not rely on an
explicit awareness of either Vkk or Ik. Clearly, Rout = ∞ is the ideal circumstance in that it ensures Ik = 0 for all Vkk. We therefore deem it productive to embark on the task of determining
output resistance Rout for the NMOS sink in Figure (5.3a).
We can conduct a circuit analysis that leads to an expression for the desired output
resistance, Rout, simply by straightforwardly examining the entire network in Figure (5.3a) with
each transistor supplanted by its small signal model. Although there is nothing philosophically
wrong with this solution tack, we shall adopt a slightly more creative analytical strategy. In
particular, we must begin to prepare ourselves for complicated analytical projects. In these advanced projects, replacing each active device by an equivalent circuit is likely to provoke inordinately cumbersome, tedious, and even annoying mathematics that accomplish little more than to
mask the design insights we are attempting to glean.
Vdd
Iref
0
Id1

Vref
To Gate
Of M2
To Gate
Of M2
gm1V1
M1
ro1
b1gm1V2
 V1 

 V2 
(a).
(b).
To Gate
Of M2
Vy
gm1V1
ro1
Iy
1/gm1
 V1 
(c).
ro1
rd
(d).
Figure (5.4). (a). Subcircuit comprised of diode-connected transistor M1 that drives the gate of transistor
M2 in Figure (5.3a). (b). Low frequency, small signal model of the subcircuit in (a). (c). Circuit used to evaluate the Thévenin output resistance, Vy /Iy = rd, of the subcircuit in (a). (d).
The Thévenin equivalent source circuit seen by the gate of transistor M2 in Figure (5.3a).
In order to initiate our design-oriented analysis, let us replace the diode-connected
subcircuit to the left of the M2 gate in Figure (5.3a) by its Thévenin equivalent circuit. Such a
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Chapter 5
MOSFET Biasing
replacement demands that the subject subcircuit be electrically represented by a small signal, and
therefore linear, equivalent circuit since Thévenin displayed neither interest in, nor compassion
for, nonlinear circuits. Figure (5.4a) displays the subcircuit partitioned from the remaining
components of the current mirror we are investigating. In Figure (5.4b), we exploit the low frequency, small signal transistor model we produced as Figure (4.22a) to delineate the pertinent
equivalent circuit of the reference subcircuit in Figure (5.4a). In this model, we have replaced
the power line voltage, Vdd, by a short circuit since the small signal voltage value of a source of
constant voltage is a null voltage. As it turns out, the present replacement of Vdd by a short circuit carries no engineering significance since the small signal model of the constant current
source, Iref, to which Vdd is applied as a series element, is an open circuit. To this end, we depict
current source Iref by its replacement small signal source. Given that current Iref is a constant, its
small signal current has zero value, which of course reflects an open circuit. If we had accounted
for a finite terminal resistance associated with Iref, the small signal model of the subject source
would have been its presumably large two-terminal shunting resistance, as opposed to the implied open circuit.
The short circuiting of voltage source Vdd and the open circuiting of current source Iref,
precludes any signal source from being applied to the biasing subcircuit. This situation immediately leads us to conclude that the Thévenin signal voltage activating the gate of transistor M2
is zero. If, however, we had observed a small fluctuation in Iref and/or a small fluctuation in Vdd
under the condition of a finite current source resistance, the subcircuit at hand would have responded by delivering a presumably small, but nonzero, Thévenin voltage at its open circuited
output port.
With zero Thévenin voltage observed at the output port of the M1 biasing subcircuit,
the Thévenin equivalent of this subcircuit collapses to a simple Thévenin resistance. We can
determine this resistance with the help of the model shown in Figure (5.4c). The latter model
derives directly from the network in Figure (5.4b), where we have dispensed with the short circuit replacement of line voltage Vdd because of the open circuit replacement of reference current
Iref. Additionally, we observe that since the bulk and source terminals of transistor M1 are
grounded, no bulk-source signal voltage, shown as voltage V2 in Figure (5.4b), is established.
Thus, the bulk transconductance current, λb1gm1V2, which quantifies the dependence of signal
drain current on signal bulk-source voltage, vanishes. We can then determine the Thévenin output resistance, say rd, in a conceptual manner that mirrors how an ohmmeter determines the
resistance between any two terminals of a linear network. In particular, an ohmmeter squirts a
small amount of current, say Iy in the present case, into the port of interest (the model output
port). In response to this applied current, the ohmmeter measures the voltage Vy, which is the
voltage across, and in disassociated polarity with, the injected small current, Iy2. The ohmmeter
then displays voltage Vy normalized to current Iy on the ohmmeter display; that is, it effectively
measures the resistance of interest by displaying the voltage to current ratio, Vy /Iy. We show the
mathematical form of this ohmmeter in the small signal model of Figure (5.4c).
In the aforementioned diagram, the ohmmeter voltage, Vy, happens to be identical to the
gate-source signal voltage, V1, which controls the current source, gm1V1. In other words, current
gmV1 is the same as gm1Vy. But voltage Vy appears directly across, and in associated polarity
with, the controlled source, gm1Vy. We therefore argue that the branch conducting current gm1Vy
2
A branch voltage is said to be in disassociated polarity with its branch current if said branch current flows toward
the “plus” end of the branch voltage. On the other hand, a branch voltage is in associated polarity with its branch
current if the branch current is directed toward the “minus” end of the voltage.
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Chapter 5
MOSFET Biasing
is equivalent to a branch resistance, Vy /gm1Vy = 1/gm1, as we depict in our final form subcircuit
model of Figure (5.4d). Without even writing an equilibrium Kirchhoff equation, we can then
conclude that the Thévenin resistance, rd, presented to the gate of transistor M2 by the M1 subcircuit is
r
1
1
o1
(5-16)
r  r


,
d
o1 g
1 g r
g
m1
m1 o1
m1
where the indicated approximation reflects the strong prospects that gm1ro1 >> 1. For large gate
aspect ratio and/or a relatively large reference current, Iref, gm1 is reasonably large (tens of
millimhos). In turn, the resistance seen at the output port of the diode-connected network is, as is
the resistance of a conventional PN junction diode, relatively small (high tens to a few hundreds
of ohms in the case of a diode-connected MOSFET).
The discovery that the small signal model of the diode-connected transistor, M1, is a
simple resistance is hardly revolutionary. In particular, transistor M1 functions effectively as a
two terminal branch element since its gate and drain terminals are connected together, as are its
bulk and source terminals. Accordingly, when we replace the subject transistor by its low frequency (and therefore memoryless), small signal equivalent circuit, we clearly end up with a linear, two terminal network that has no implicit energy storage elements. But a linear, two terminal, memoryless, network is, by definition, a two terminal linear resistance in that its terminal
voltage is necessarily linearly related to its terminal current in a fashion that is prescribed by the
adopted linear model.
Figure (5.5) is the small signal schematic diagram of the entire NMOS current mirror in
Figure (5.3a), wherein the gate circuit of transistor M2 is supplanted by our Thévenin equivalent
representation of this M1 subcircuit. Of course, we have determined that this Thévenin
representation consists only of a simple two-terminal resistance, rd, as stipulated by (5-16).
Moreover, our mathematical ohmmeter, comprised now of the independent current source, Ix,
and its companion terminal voltage Vx, is appended to the output port of the mirror. Since there
is no Thévenin voltage driving the gate of transistor M2, the gate-source signal voltage, Va, applied to M2 is zero. This zero signal voltage renders gm2Va = 03, whence, and again by inspection, we see that output resistance Rout is
Rout
Vdd
Vkk
Iref
Ik
M2
Id1

Vref M1

Vx
x k21
gm2Va
Rout
ro2
Ix
 Va 
rd
Figure (5.5). Low frequency, small signal model used to compute the output resistance, Rout, of the NMOS
current mirror. In terms of mathematical ohmmeter variables, this resistance is Rout = Vx /Ix.
3
A controlled current or a controlled voltage source must not be set to zero indiscriminately when evaluating a
circuit resisitance. As in the present case, such a controlled source may assume a null value, but only if network
conditions compel the source current (or voltage) to vanish.
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Chapter 5
MOSFET Biasing
R
out

V
x  r .
o2
I
x
(5-17)
As noted earlier, we should like to have Rout large. Since Rout in this case is merely the drainsource channel resistance of transistor M2, large Rout requires that M2 have a long channel length
and/or M2 should conduct a relatively small quiescent drain current.
We note, perhaps with some chagrin, that the effort we expended to determine the
Thévenin network driving the M2 gate turned out to be inconsequential in that Rout is independent of the electrical properties observed at the gate of transistor M2. Resistance Rout is
understandably independent of gate parameters, because the gate of a MOSFET conducts no
static current. Moreover, no excitation prevailed at the M2 gate site. However, our efforts have
not been expended in vain, for we shall commonly encounter diode-connected transistors to
which we can directly apply the fruits of the aforementioned analysis.
EXAMPLE #5.2:
In the NMOS current mirror of Figure (5.3a), spurious signals perturb the
voltages, Vdd and Vkk, in the respective amounts of Vdd and Vkk. The
reference current source, Iref, which can be presumed constant, has a terminal resistance of Rr. Determine the approximate resultant change, say
Ik in the quiescent current, Ik, established by the mirror. Explain all
approximations, and offer suggestions as to how the spurious signal-induced output current fluctuation can be minimized in view of the stipulated voltage changes.
SOLUTION #5.2:
Ik

Rt1
Rr
Vt1

rd
Vdd

gm2Va
Rt1
 Va 

ro2
Vkk

kd1Vdd

(a).
(b).
Figure (5.6). (a). Low frequency, small signal model of the M1 subcircuit for the NMOS current mirror of
Figure (5.3a). The model is used in Example #5.2. (b). Low frequency, small signal model of
the NMOS current mirror of Figure (5.3a). This model is also used in Example #5.2.
(1).
We begin by determining the Thévenin equivalent circuit driving the gate of transistor M2.
Unlike the discussion of the preceding section, this Thévenin representation embraces a
Thévenin voltage owing to the non-ideal nature of current source Iref and the stipulated
change, Vdd, in power line voltage. To this end, Figure (5.6a) depicts the small signal model
of the M1 subcircuit. Rather than representing transistor M1 by its small signal model, we
rely on our recent experience, which affirms that a diode-connected transistor (M1) can be replaced by a two-terminal resistance of value rd, as defined in (5-16). Resistance Rr accounts
for the finite terminal resistance associated with current source Iref, while the perturbation,
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Chapter 5
MOSFET Biasing
Vdd, in voltage Vdd can be viewed as a small signal voltage source. Recall that in the preceding section, Vdd is effectively expunged because Vdd is taken as an ideal, constant voltage
source. Moreover, Rr in the previous section of material is infinitely large owing to the presumed ideal nature of current source Iref. The subject model produces a Thévenin voltage,
Vt1, at the output port of the M1 subcircuit of
 rd 
Vt1  
(E2-1)
 ΔVdd  kd1 ΔVdd ,
 rd  Rr 
where kd1, the voltage divider in (E2-1), is
rd
r
1
kd1 
 d 
.
rd  Rr
Rr
g m1 Rr
(E2-2)
The indicated approximation exploits our awareness that the resistance, rd, of a diode-connected MOSFET is small and approximately equal to 1/gm1, while we expect a reasonably
well designed current source to exude a large current source terminal resistance, Rr.
The Thévenin scenario is finalized by determining the Thévenin output resistance at the drain
port of transistor M1. The simplicity of the network before us obviates the need to exploit
our mathematical ohmmeter here. In particular, we always set to zero all independent energy
sources in the process of evaluating a network resistance. In this case, there is only one such
independent source; namely, Vdd. With Vdd clamped to zero, inspection alone dictates a
Thévenin resistance, Rt1, of


 1 
ro1
1
Rt1  rd Rr  
,
(E2-3)
 Rr  
 Rr 
g m1
 1  g m1ro1 
 g m1 
where the approximations reflect large Rr and gm1ro1 >> 1. It follows that this Thévenin
resistance is essentially determined by the terminal resistance associated with the diode-connected first transistor.
(2).
Figure (5.6b) offers the small signal model of the entire NMOS mirror. In this model, we
have exploited the facts that the bulk-source signal voltage for M2 is zero, the gate of transistor M2 is driven by the Thévenin model deduced in the preceding part of this solution, and
the spurious change, Vkk, behaves as a small signal voltage source applied with respect to
ground at the drain terminal of transistor M2. Since the considered network is linear,
superposition theory can be invoked to determine the net change, Ik, in current, Ik. In
particular, with Vkk = 0, we see that the control voltage, Va, is Va = kd1Vdd; hence Ik =
gm2Va = gm2kd1Vdd. On the other hand, Vdd = 0 constrains voltage Va to zero. Resultantly,
Ik = Vkk /ro2. It follows that
ΔVkk
(E2-4)
ΔI k  g m2 kd1 ΔVdd 
.
ro2
Recalling (E2-2), we can write
g m2
(E2-5)
g m2 kd1 
.
g m1 Rr
But, transistor M2 has a gate aspect ratio that exceeds the gate aspect ratio of transistor M1 by
a factor of k21. Additionally, the drain current flowing in M2 is a factor of k21 larger than the
drain current of M1. Since the forward transconductance of a saturated MOSFET is proportional to the square root of the product of gate aspect ratio and quiescent drain current,
g m2
k
(E2-6)
g m2 kd 1 
 21 .
g m1 Rr
Rr
We conclude that the perturbation in drain current Ik is given by
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Chapter 5
MOSFET Biasing
ΔI k  g m2 kd 1 ΔVdd 
ΔVkk
k ΔV
ΔVkk
 21 dd 
.
ro2
Rr
ro2
(E2-7)
ENGINEERING COMMENTARY:
The result in (E2-7) tends to mirror expectations. In particular, the closer Iref is to an ideal
current source and the closer transistor M2 emulates an ideal controlled current source at its
drain port, the less sensitive current Ik is to perturbations in the voltages, Vdd and Vkk. Ideality
with respect to Iref means resistance Rr is infinity, in which case, the first term on the right
hand side of (E2-7) vanishes. If the drain port of M2 emulates an ideal (controlled) current
source, ro2 is infinitely large, and the second term on the right hand side of (E2-7) goes to
zero. We also note that too large of a current mirroring factor, k21, aggravates the sensitivity
of current Ik with respect to the power bus voltage, Vdd. The latter situation also reflects
engineering expectation for if Vdd fluctuates, Iref is perturbed (assuming Iref is a practical current source). Once Iref fluctuates, Ik necessarily changes for the current gain, Ik /Iref, is directly
proportional to k21. Indeed, Ik /Iref ≈ k21 if channel length modulation in transistor M2 is
minimal.
5.3.2. CURRENT MIRROR WITH SOURCE DEGENERATION[1]
The current mirrors in Figure (5.3) offer limited design flexibility with respect to the
output resistance, Rout. Recall from (5-15) that this output resistance establishes the sensitivity of
output current, Ik, with respect to small perturbations in the applied voltage, Vkk. In particular, a
targeted small sensitivity to applied voltage mandates a large output resistance. If we appeal to
(5-17), we see that Rout in Figure (5.3a) is determined exclusively by the channel resistance, ro2,
implicit to NMOS transistor M2. Thus, the only direct means afforded us to adjust, or to tune,
Rout is to change current Ik (smaller Ik for larger Rout). Unfortunately, this design degree of freedom may not be available, for current mirrors are often implemented to establish a required current, Ik, which is presumably optimal, or at least preferred, for a particular application. Yet
another problem arises when the application to which the design effort is focused requires that
deep submicron transistors be utilized in the mirror. We recall that very small drawn channel
lengths beget proportionately small channel length modulation voltages, which in turn result in
small drain-source channel resistances at given quiescent drain currents. We therefore expect
that low bias current sensitivity to applied voltage is a challenge for deep submicron technologies.
Vdd
Vkk
Iref
Ik
Rout
M1
M2
x k21
Rss
Rss /k21
Figure (5.7). Schematic diagram of a source-degenerated NMOS
current mirror. An analogous source-degenerated
PMOS mirror can also be forged.
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Chapter 5
MOSFET Biasing
A viable mitigation of the foregoing dilemma is offered by the so-called source-degenerated NMOS current mirror offered in Figure (5.7). The schematic diagram is similar to that of
the simple NMOS mirror in Figure (5.3a), save for the insertion of resistances, Rss and Rss/k21, in
the transistor source terminals. These resistances are called source degeneration elements for, as
we shall witness when we address MOSFET amplifiers, they reduce, or “degenerate,” the forward transconductances, and thus the overall I/O gain, of their respective transistors. We are
also about to see that if the source degeneration resistances are selected in accordance with the
elemental stipulations in the subject circuit schematic diagram, k21 must necessarily equate to the
ratio of the gate aspect ratio of transistor M2 to the transistor M1 gate aspect ratio. If Ik = k21Iref,
the gate-source voltage, Vgs2, of transistor M2 is forced to replicate the gate-source voltage, Vgs1,
of M1. This declaration follows from the Kirchhoff equilibrium relationship,
R 
V
I R  V
 I  ss  ,
(5-18)
gs1
ref ss
gs2
kk 
 21 
whence, with Ik = k21Iref,
 I

k
(5-19)
V
V
 I R 
 1  0 .
gs1
gs2
ref ss  k I

 21 ref

Of course, the Schichman-Hodges model affirms that if Vgs1 = Vgs2 produces Ik = k21Iref, parameter k21 is the ratio of the gate aspect ratio of transistor M2 to the gate aspect ratio of M1.
There is another important ramification to the source degeneration resistances deployed
in the mirror of Figure (5.7). In particular, if Vgs1 = Vgs2, (5-18) confirms that the drop, IrefRss,
across the source degeneration resistance, Rss, for transistor M1 is identical to the voltage drop,
IkRss/k21, across the source degeneration resistance, Rss/k21, used for transistor M2. The equal
resistive drops means that the quiescent voltages established with respect to ground at each
transistor source node are the same. In turn, equal source terminal voltages manifest equal bulksource biases since both transistors have their respective bulk terminals returned to circuit
ground. We can therefore conclude that the threshold voltages, Vhn1 and Vhn2, of M1 and M2,
respectively, while subject to bulk-induced threshold modulation, are, at least in theory, identically equal to a potential that is somewhat greater than the zero bias value of transistor threshold
voltage.
With Vgs1 = Vgs2  Vgs, Vhn1 = Vhn2  Vhn (inclusive of body effect) and Vλ1 = Vλ2  Vλ,
(5-10) yields
2
V 
 1  hn 
I
  V V
ref
n gs
hn 
V 
 

(5-20)
.
V  I R V

2
ref ss
dsat
 1  kk

I  k  V V
k
21 n gs
hn 

V



These two relationships lead to




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Chapter 5
MOSFET Biasing
V  I R V

ref ss
dsat 
 1  kk

V



I  k I 
(5-21)
,
k
21 ref
V


1  hn


V



which is similar in form to (5-14) for the simple (non-degenerated) NMOS current mirror. Since
Vdsat = (Vgs − Vhn), selecting Vkk in the neighborhood of (IrefRss + Vgs) mitigates channel length
modulation. Alternatively, large Vλ, which requires a suitably long drawn channel, likewise offsets channel length modulation. Thus, if we satisfy one or both of these design targets, we
achieve Ik ≈ k21Iref, which is indicative of an ideal current mirror.
If the shunt resistance associated with the reference current source, Iref, is infinitely
large, current Ik proudly boasts no sensitivity to power line voltage Vdd. In other words, an ideal
current source, Iref, implements infinitely large power supply rejection with respect to Vdd. On
the other hand, the sensitivity of Ik to voltage Vkk is determined by output resistance Rout in accordance with the generality set forth by (5-15). Deducing an analytical expression for Rout initiates
with our determining the Thévenin voltage and the Thévenin resistance associated with the gatedrain output port of the M1 subcircuit. In this case, we can claim immediately that the Thévenin
voltage driving the gate terminal of transistor M2 is zero owing to the fact that the constant and
ideal current source, Iref, presents zero signal value to the mirror. Equivalently, we may assert
that a small signal open circuit prevails in the network branch that interconnects voltage Vdd with
the gate-drain terminal of transistor M1. Moreover, the Thévenin output resistance of the M1
subcircuit bodes no significance in that the gate of transistor M2 conducts no static current and
therefore, no voltage is dropped across this resistance. Accordingly, we can presumably concentrate on the small signal analysis of only the M2 subcircuit of the mirror, with the understanding
that zero signal voltage is applied to its gate.
True enough! But nonetheless, we shall proceed with finding the Thévenin resistance
at the output port of the M1 subcircuit for two reasons. First, high frequency currents are conducted by MOSFET gates, whereupon it may be that the subject Thévenin resistance establishes
a critical time constant with an M1 device capacitance. Second, we shall encounter sourcedegenerated, diode-connected transistors as building block components in our future network
deliberations, so we are well advised to execute and file for future reference in our design notebooks the pertinent circuit analysis and its results.
Figure (5.8) is the small signal model for determining the M1 Thévenin resistance, Rt1,
which we shall calculate as the ratio, Vy /Iy, of mathematical ohmmeter variables. We recall our
modeling experience with the diode-connected transistor in the conventional NMOS mirror of
Figure (5.3a). This modeling experience suggests that the M1 diode-connected unit we are presently examining establishes a drain to source resistance of 1/gm1, if channel resistance ro1 is
large. In turn, our first blush estimate of the Thévenin output resistance is Rt1 = 1/gm1 + Rss. Indeed, this is a reasonably accurate first order estimate of Rt1, but it is not strictly correct in that
body effect prevails herewith. In support of this contention, we note that unlike the network in
Figure (5.3a), which grounds both the source and the bulk terminals of transistor M1, the diagram in Figure (5.7) portends only the grounding of the bulk terminal for transistor M1. It follows that the model shown in Figure (5.8) properly incorporates a bulk transconductance effect
of λb1gm1V2, where V2 symbolizes the signal component of the bulk-source voltage applied to
transistor M1. In general, we recall that a very thin gate oxide, Tox, begets very small λb. Of
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Chapter 5
MOSFET Biasing
course, λb =0 implies no bulk-induced transconductance.
Vdd
Rt1
Iref
Rt1
Vy
M1
gm1V1
b1gm1V2
 V1 
Iygm1V1b1 gm1V2
Rss
ro1
Iy
 V2 
Rss
Iy
Figure (5.8). Small signal model used to determine the Thévenin output resistance, Rt1, presented at the output
port of the M1 subcircuit in the source degenerated mirror of Figure (5.7).
In the small signal model of Figure (5.8), we have delineated key branch currents in order to facilitate the construction of the requisite Kirchhoff equations. In particular,
V  V I R
1
y
y ss
,
(5-22)
V  I R
2
and
V 
y
y ss
I
y
g
V  g
m1 1
V
r
b1 m1 2 o1
 I R
y ss
.
(5-23)
Upon substituting (5-22) into (5-23), followed by the obligatory rearrangement of terms, we find
that
1  1   g r 
V
1
y
b1 m1 o1 

R 
r  
R .
(5-24)
t1
o1

 ss
I
g
1 g r
y
m1
m1 o1


The first term on the right hand side of this expression represents our familiar small signal resistance of a diode-connected transistor. Our inspection of the last term, which accounts for the
resistance, Rss, placed in the source lead of transistor M1, suggests that the immediate effect of
BITM is to increase very slightly the witnessed value of this series resistance. Nevertheless, our
first order estimate of the value of Thévenin resistance Rt1 is apparently spot on. In particular, if
gm1ro1 >> 1 (which is almost always true) and λb1 << 1 (which is true for thin gate oxide layers),
1  1   g r 
1
1
b1 m1 o1 
R .
R 
r 
R 
(5-25)
t1
o1
ss
ss


g
1 g r
g
m1
m1 o1
m1






Our analytical task is completed by applying the low frequency, small signal MOSFET
model to the M2 subcircuit of the source degenerated current mirror. We display this model in
Figure (5.9), where we have once again identified relevant branch currents. The model, which
includes the inconsequential Thévenin resistance, Rt1, disclosed above, projects
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Chapter 5
MOSFET Biasing
Rout
Vx
gm2Va
 Va 
ro2
b2gm2Vb
Ixgm2Vab2gm2Vb
Ix
 Vb 
Rss /k21
Rt1
Ix
Figure (5.9). Small signal model used to determine the Thévenin output resistance, Rout,
presented at the output port of the source degenerated mirror in Figure (5.7).
R 
V  V   I  ss  ,
a
b
xk 
 21 
(5-26)
and
V 
x
R

 I x  gm2Va  b2 gm2Vb  ro2  I x  k ss  .
(5-27)
 21 
Subsequent to our inserting (5-26) into (5-27), we find that

 R 
V
R
x

(5-28)

 1  1 
R
g  ss   r  ss .
out
b2 m2  k   o2
I
k



x
21
21


For gm2ro2 >> 1 and λb2 << 1,


 R 
 R 
R
(5-29)
 1  1  
R
g  ss   r  ss  1  g  ss   r .
out
b2 m2  k   o2
m2  k   o2
k


21
 21  
 21  


Since transistor M2 has a gate aspect ratio that exceeds the gate aspect ratio of M1 by a factor of
k21, and since M2 conducts a static current that is larger than the static current of M1 by the same
factor (k21), gm2/gm1 = k21. It follows that (5-29) can be simplified to the form,


R
out



1  gm1Rss  ro2 .
(5-30)
It is now safe to say that the source degenerated current mirror of Figure (5.7) proactively addresses the output resistance shortfall we identified in the conventional mirror of Figure
(5.3a). In particular, the present output resistance embellishes the M2 channel resistance, ro2,
which we recall as the actual output resistance of the original current mirror, by an approximate
factor of (1 + gm1Rss). In a word, the degenerated mirror improves on the current sensitivity of
the original mirror by the factor, (1 + gm1Rss). But as is perennially the case whenever we succeed in enhancing or optimizing circuit performance, engineering prices are paid. In the present
case, two prices surface. The first is increased power dissipation. Whereas power needs to be
supplied to only the two transistors embedded in the conventional mirror, power in the degenerated version must be supplied to the same two transistors and additionally, two circuit resistances; namely, the resistances, Rss, and Rss/k21. If power dissipation is a critical issue, it clearly
behooves us to keep resistance Rss as small as practicable. The second price is the need for an
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Chapter 5
MOSFET Biasing
increased voltage, Vkk. In the present case, Vkk must bias the drain-source terminals of transistor
M2, and it must establish a suitable voltage across the circuit resistance, Rss/k21. We can alternatively state that for fixed Vkk, the second problem amounts to a constrained voltage swing at the
drain-source port of transistor M2. The latter contention impinges at least indirectly on the degree of achievable circuit linearity in the source degenerated current mirror.
5.3.3. CASCODE CURRENT MIRROR
When the source degeneration resistance, Rss/k21, in Figure (5.7) is supplanted by a
transistor that is biased at its gate with a diode-connected transistor, similar to the biasing of
transistor M2 in Figure (5.7), the source degenerated current mirror is transformed into what is
known as a cascode current mirror. The cascode mirror is depicted schematically in Figure
(5.10), where all transistor bulk terminals are grounded4. We note that since the source and bulk
terminals of transistors M3 and M4 are connected to circuit ground, no BITM occurs in these
devices. But threshold modulation in transistors M1 and M2 can be an issue since the source
terminals of these transistors are not grounded. We also note that transistors M1 and M3 have
the same gate aspect ratios, and transistors M2 and M4 also have equal gate aspect ratios But the
latter ratios are a factor of k-times larger than the gate aspect ratios of M1 and M2.
In Figure (5.10), we see that the output sinking current, Ik, is given approximately by
I  kI
.
(5-31)
k
ref
This result is promoted by four observations. First, current Iref flows through the drain of
transistor M3. Second, transistors M3 and M4 share the same gate-source voltages. Third, the
gate aspect ratio of M4 exceeds that of M3 by a factor of k. Fourth, we have tacitly ignored
CLM. Dare we now quip “Q.E.D” as regards the approximate validity of (5-31)?
Vdd
Vkk
Iref
Ik
Rout
M1
M2
x1
xk
M3
M4
x1
xk
Figure (5.10). Circuit schematic diagram of an NMOS cascode current mirror.
The bulk terminals of all four transistors are grounded.
As per our source degenerated mirror, let us assume that Iref derives from an ideal
source of constant current, which is to say that it boasts infinitely large terminal resistance.
Under this circumstance, the coupling of voltage Vdd into the gates of either transistor M2 or M4
is precluded. Resultantly, current Ik is rendered independent of Vdd. More importantly, the
4
In a twin well process, it may be possible to connect each transistor bulk terminal to its respective source terminal,
thereby negating any bulk-induced modulation of threshold voltages.
- 426 -
Chapter 5
MOSFET Biasing
inability of Vdd to couple into the gate of M4 means that no gate-source signal voltage can be
established for M4. In turn, this situation gives rise to a drain to source signal current, gm4Va, as
we depict in the equivalent circuit of Figure (5.11a), that is forced to zero. The same null stature
applies to the bulk transconductance source, λb4gm4Vb, since the grounding of both the bulk and
the source terminals remands the bulk-source signal voltage, Vb, to zero. Resistance Rt3 in this
equivalent circuit represents the Thévenin resistance presented to the gate of transistor M4 by the
diode-connected transistor, M3. This resistance is inconsequential since it conducts no current
and therefore, we can refrain from defining it analytically. Because Va = Vb = 0 in Figure
(5.11a), the only element left standing in the small signal model of transistor M4 is the M4
channel resistance, ro4. In effect, transistor M4 in the cascode mirror behaves as a two terminal
resistance and indeed, a rather large drain-source channel resistance.
gm4Va
Rt3
b4gm4Vb
ro4
 Va 
=0
ro4
 Vb 
=0
(a).
Rout
Vx
gm2V1
Rt1
b2gm2V2
 V1 
ro2
Ix
 V2 
ro4
(b).
Figure (5.11). (a). Low frequency, small signal model of transistor M4 in the cascode mirror of Figure
(5.10). (b). Low frequency, small signal model of the M2-M4 subcircuit in the cascode
current mirror of Figure (5.10).
The resultant low frequency model of the M2-M4 subcircuit is the topological structure
appearing in Figure (5.11b). In this model, we have replaced transistor M4 by its channel
resistance, ro4, which we now comprehend as an effective source degeneration resistance for
transistor M4. Analogous to the previously defined Thévenin resistance, Rt3, Rt1 is the presently
inconsequential Thévenin resistance presented to the M2 gate by the subcircuit formed of transistors M1 and M3 in Figure (5.10). But the most important undertone of this modeling exercise is
that the model in Figure (5.11b) is topologically identical to the equivalent circuit we forged in
Figure (5.9) for the conventional form of a source degenerated current mirror. The only
observable electrical difference between the two models is that the source degeneration
resistance, Rss/k21, in Figure (5.9) appears now as the resistance, ro4. This topological similarity
synergizes with our earlier pronouncement to the effect that the cascode mirror is little more than
a special case (indeed, an active form of a special case) of the source degenerated mirror. Its
immediate and practical implication is that we can determine output resistance Rout in Figure
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Chapter 5
MOSFET Biasing
(5.11b) merely by modifying the expression for Rout that we have already filed in our design
notebook for the source degeneration case. Specifically, if we replace Rss/k21 by ro4 in (5-28), we
see, without need for annoying additional analysis, that
V
R
g r r  r  1  g r r .
 x  1  1  
(5-32)
out
b2 m2 o4  o2
o4
m2 o4 o2

I

x



Because resistance ro4 is doubtlessly significantly larger than the former degeneration resistance,
Rss/k21, the output resistance, Rout of the cascode current mirror is laudably much larger than its
companion output resistance for the conventional mirror.
It is important to appreciate that the channel resistance, ro4, which functions as source
degeneration for transistor M2 in Figure (5.10), is large and assuredly much larger than the
passive degeneration resistance, Rss/k21, which we deployed in the previous current mirror.
Unlike the passive resistance, Rss/k21, which necessarily supports a static drop of IkRss/k21, the
active degeneration resistance, ro4, does not need to support a static voltage of Ikro4 across its
terminals. Instead, the static voltage required across the drain-source terminals of transistor M4,
where ro4 is realized, is a drain saturation voltage, which can be as small as only a few tenths of a
volt. This voltage drop is far smaller than the static drop necessarily established across a passive
resistance of value ro4. For example, if ro4 = 20 KΩ, a meager Ik = 1 mA develops 20 volts across
a passive form of resistance ro4. Good luck selling a cell telephone, a global positioning satellite
(GPS) unit for automotive use, or other portable electronic system that requires at least a 20-volt
battery for activation. In a word, voltage Vkk in the cascode mirror of Figure (5.10) need only be
large enough to ensure that transistors M2 and M4 operate in their saturation domains.
Let us examine more carefully the constraints to which voltage Vkk is necessarily
subjected. We begin by remembering that the gate-source voltages of transistors M3 and M4 are
the same; that is, Vgs3 = Vgs4  Vgs. In view of the facts that transistor M2 has the same gate
aspect ratio and conducts the same drain current that flows through transistor M4, Vgs2 ≈ Vgs4 =
Vgs. This gate-source voltage equality presumes that channel length and bulk-induced threshold
modulations in M4 are negligible. A similar statement applies to transistors M1 and M3; that is,
Vgs1 ≈ Vgs3  Vgs. We therefore deduce
(5-33)
V
 V
 V
 V
 V .
gs1
gs3
gs4
gs2
gs
Figure (5.10) additionally confirms that Vkk must supply drain-source bias to both M2 and M4:
V  V
V
.
(5-34)
kk
ds2
ds4
In order for transistor M2 to remain in saturation, we require Vds2 ≥ (Vgs2 − Vhn2), where Vhn2, is,
of course, the threshold voltage of transistor M2. Remember that the threshold voltages of
transistors M1 and M2 can be expected to differ from the threshold potential, Vhn4, of M4 owing
to body effects incurred by the grounding of the bulk terminals of transistors M1 and M2. Since
V
 V
V
V
 2V  V
,
(5-35)
gs2
gs1
M2 is saturated if
V
 V
ds2
gs2
gs3
V
hn2
ds4
 2V
gs
gs
V
ds4
Inserting this result into (5-34) establishes
V  V
V
 2V  V
kk
ds2
ds4
gs
hn2
ds4
V
hn2
.
Since
- 428 -
.
(5-36)
(5-37)
Chapter 5
MOSFET Biasing
V
 V
V
 V
dsat1
dsat3
we conclude that
V  2V
kk
gs1
gs3
gs
V
 V
V
 V
hn2
hn4
V
hn2
gs
gs
 V
dsat1
V
hn2
V
,
(5-38)
hn4
V
dsat3
V
hn4
(5-39)
;
that is, voltage Vkk must be at least as large as nominally one threshold potential above twice the
drain saturation voltage of a transistor. Depending on the channel length of the utilized
transistors, the drain saturation voltage can be in the range of 200 mV to 500 mV, while a gatesource threshold voltage can be of the order of 400 mV to 800 mV. Accordingly, we can expect
that voltage Vkk must lie in the range, 800 mV < Vkk < 1.8 V.
5.3.4. WILSON CURRENT MIRROR[1]-[2]
Figure (5.12) depicts the basic schematic diagram of the Wilson current sink. As in the
cascode network, we have not shown the bulk terminal connections of transistors, but we
nonetheless assume that these terminals are incident with circuit ground. Thus, bulk-induced
threshold modulation takes place in transistors M1 and M2. However, our analyses and
discussions of the Wilson mirror adopt the simplifying stance of gate oxide layers that are thin
enough to allow for the tacit neglect of threshold voltage modulation in all active devices.
Vdd
Vkk
Iref
Ik
Rout
M1
M2
x1
xk
M3
M4
x1
xk
Figure (5.12). Circuit schematic diagram of an NMOS Wilson current
mirror. The bulk terminals of all four transistors are
presumed returned to circuit ground.
If we compare the network before us with that of the cascode configuration in Figure
(5.10), we see that the Wilson circuit interchanges the roles of transistors M3 and M4. In other
words, transistor M3 functions as a diode in the cascode circuit, while in the Wilson network, it
serves effectively as a grounded source amplifier. More than simply a grounded source amplifier, M3 implements active feedback from the source of transistor M2 to the source terminal of
M1. This feedback serves to protect current Ik from spurious vulnerabilities. For example, suppose current Ik increases by an amount that is not so large as to threaten the removal of transistors M2 and M3 from their saturation domains. Since the diode-connected device, M4, acts as a
two terminal resistance, the increase in current Ik manifests a commensurate increase in the
drain-source voltage of M4 and hence, in the gate-source voltage of transistor M3. The rise in
M3 gate-source voltage produces a decrease in the drain-source voltage of M3 for, as we learned
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Chapter 5
MOSFET Biasing
in the preceding chapter, I/O (gate to drain) phase inversion is implicit to common source
amplifiers. The decrease in M3 drain-source voltage pulls down the voltage observed at the gate
of M2. With the gate voltage of M2 falling and the source voltage of the same device rising, as
we have already noted, the gate-source voltage of M2 diminishes. This decrease in the M2 gatesource voltage is met with a decrease in the indicated drain current, Ik. Accordingly, the original
spurious increase in Ik is met with a mitigating current decrease to incur an effective stabilization
of the sinking output current. In other words, the original current increase is ostensibly cancelled
by the feedback that is implicit to the Wilson circuit.
Transistors M1 and M3 have identical gate aspect ratios, as do transistors M2 and M4.
But we note that the gate aspect ratios of M2 and M4 are a factor of k larger than the respective
gate aspect ratios of M1 and M3. We shall demonstrate that the indicated output resistance, Rout,
is potentially very large, despite being somewhat compromised by the designable factor, k. This
laudable attribute does not stem principally from the source degeneration presented to M2 by the
diode-connected transistor M4. Instead, it arises largely from the series-shunt feedback we have
addressed in the preceding paragraph. We shall more definitively investigate the feedback implicit to the Wilson cell when we study the common source-Wilson cascode broadband amplifier
later in this text.
We see that the applied input current, Iref, flows through the drain of transistor M3.
Since the gate-source voltages, Vgs3 and Vgs4, of M3 and M4, respectively, are identical, M3 and
M4 comprise a traditional two-transistor current mirror. The drain current resultantly conducted
by transistor M4 is necessarily kIref, where we have made use of the fact that the gate aspect ratio
of M4 is larger than that of transistor M3 by factor k. In asserting this mirrored current value, we
have ignored the effects of CLM in M3 and M4. The mirrored current flows through M2,
whence we conclude that output current Ik approximates kIref.
Let us now support the foregoing intuitive disclosures with a more focused analysis.
We begin by monitoring the drain-source voltage, Vds3, of transistor M3 as Vds3 = (Vgs2 − Vgs1 +
Vgs4). Then, by the square law model, modified to account for CLM,


V
V
V
 V
V
2
gs2
gs1
gs4
gs3
hn 
(5-40)
I
1
  V
V
.
ref
n gs3
hn 
V





Since Vgs3 ≡ Vgs4,
V
V
V 
2
gs1
hn
 1  gs2
.
(5-41)
  V
V
I
ref
n gs3
hn 

V



For transistor M4,
2
V 
 1  hn  ,
(5-42)
V
I  k V
k
n gs3
hn 
V 
 

where we have exploited identical threshold voltages of M3 and M4 resulting from the absence
of body effect in these two devices. Moreover, the CLM voltage, Vλ, should be nominally the
same in M3 and M4, as long as no wide disparity prevails between the drain-source voltages of
these two devices. We can combine (5-41) and (5-42) to obtain







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
Chapter 5
MOSFET Biasing


V


1  hn
V



I  kI 
(5-43)
.
k
ref
V
V
V



gs2
gs1
hn 
 1 

V



In addition to confirming our mirroring intuition, the last expression renders clear the fundamental purpose of diode-connected transistor M1. To wit, if M1 were supplanted by a short circuit,
so that the input current, Iref, is applied directly to the drain of M3, Vgs1 in (5-43) is effectively
zero. This means that the parenthesized correction factor on the right hand side of (5-43) becomes
V
1  hn
V

,
V
V
gs2
hn
1
V

thereby making it likely that Ik is noticeably smaller than the mirrored value, kIref, of this current.
But with M1 included in the circuit, it is plausible that Vgs2 equals, or at least closely approximates, Vgs1, wherein we conclude that Ik ≈ kIref. Thus, the mirroring factor we have noted is rendered virtually insensitive to channel length effects5. We should point out that achieving Vgs1 ≈
Vgs2 is not a challenge. In particular, since M1 and M2 are physically identical transistors whose
gate aspect ratios are scaled in accord with the quiescent currents they respectively conduct, their
gate-source voltages should be nominally equal, assuming reasonably robust CLM voltages.
Moreover, while it is necessary for the relative gate aspect ratio of transistor M4 to be k, there is
nothing sacred about setting the gate aspect ratio of transistor M2 to k. In a word, it may be both
prudent and desirable in the course of simulating the network to adjust the relative gate aspect
ratio of M2 to effect voltage Vgs2 closely matched to voltage Vgs1.
In order to determine the output resistance, Rout, of the Wilson mirror, we turn to the
low frequency, small signal equivalent circuit we display in Figure (5.13). This model reflects
two simplifying and reasonable assumptions. The first of these assumptions is that BITM, which
is nonexistent in transistors M3 and M4, is negligible in transistors M1 and M2. This stipulation
is entirely reasonable for the thin gate oxide MOSFETs that are routinely available from state of
the art integrated process foundries. Our second assumption is the tacit neglect of CLM, which
is equivalent to asserting infinitely large drain-source channel resistances, in transistors M1 and
M4. The latter assumption is justifiable in that M1 and M4 are diode-connected transistors that
exhibit terminal resistances that are no larger than the small resistance values implied by their
respective inverse forward transconductances. We recall from our previous experiences that the
resistances of these diode-connected devices equate to the parallel combination of channel resistance (ro) and inverse forward transconductance (gm). In turn, this shunt interconnection produces a resistance that closely approximates 1/gm since gmro is invariably much larger than one.
Finally, we have delineated various branch currents to facilitate writing the Kirchhoff equilibrium relationships for the Wilson small signal model.
A conventional circuit analysis of the model reveals
5
It is worthwhile noting that transistor M1 was not included in Wilson’s initial seminal disclosure[2].
- 431 -
Chapter 5
MOSFET Biasing
gm3Vb
ro3
Rout
1/gm1
gm3Vb
Vx
Ixgm2Va

Va

ro2
gm2Va
gm2Va

Vb

Ix
Ix
1/gm4
Figure (5.13). Approximate, low frequency, small signal model used to determine the driving
point output resistance, Rout, of the Wilson current mirror in Figure (5.12).
I
I g V  x
o2  x
m2 a
g
V  r
x
,
(5-44)
m4
where
V 
b
I
g
x
m4
.
(5-45)
 I 
V  g r V V   1 g r  x 
a
m3 o3 b
b
m3 o3  g

 m4 
It follows that

 g 
V
1
(5-46)
R
 x 
 1  1  g r  m2   r .
out
m3 o3  g
  o2
I
g

x
m4
 m4  

We can argue that the transconductances, gm2 and gm4, are identical because transistors M2 and
M4 have identical gate aspect ratios and conduct the same quiescent current. Because the drainsource channel resistances of transistors M2 and M3 are large, as is the product, gm3ro3, (5-46)
collapses to
R
out





 2  gm3ro3  ro2 .
(5-47)
Since the current conducted by M2 is k-times larger than the current flowing in transistor M3, ro2
≈ ro3/2, whence
r 
R
 2  g r  o3  .
(5-48)
out
m3 o3  k 


We conclude that the output resistance of the Wilson mirror is large and comparable to that of
the cascode current mirror. We should note, however, that the Wilson output resistance is
compromised by a large ratio, k, of transistor gate aspect ratios


EXAMPLE #5.3:
Design the Wilson current mirror of Figure (5.12) for an output current, Ik,
of 1 mA when the reference current, Iref, is 100 μA. For the purposes of
- 432 -
Chapter 5
MOSFET Biasing
this exercise, assume that Iref derives from an ideal source of constant current. Although the value of voltage Vdd is inconsequential because of the
presumed ideality of current source Iref, use a power line voltage, Vdd, of
3.8 volts. Assume that Vkk is set to a steady state value of 2.7 volts. For
the NMOS transistor, whose parameters appear in Table (4.1) and whose
drawn channel length is 1.5 μm, use HSPICE or its equivalent to simulate,
and provide engineering commentary of, the following performance
characteristics:
(a). the static transfer characteristic, Ik versus Vkk, for 0 ≤ Vkk ≤ 4 volts;
(b). the real part of the driving point output impedance, Zout, as a function
of signal frequency;
(c). the shunt output port capacitance as a function of signal frequency;
(d). the transient response to voltage Vkk, where Vkk is taken as a 2.7 volt
pulse train having 2 μSEC pulse widths and a 4 μSEC period.
SOLUTION #5.3:
(1). Very little work is required to design the Wilson configuration. We begin by selecting the
gate width of transistors M1 and M3 in Figure (5.12). There is no with problem setting W1 =
W3 = L = 1.5 μm. But in this case, we shall make W1 = W3 = 5L = 7.5 μm in order to incur
larger transistor capacitances, which serve to subdue voltage response overshoots to suddenly
applied line voltages. Since we need Ik = 1 mA, W2 = W4 = 10W1 = 75 μm. Making W1 and
W3 too large begets very large W2 and W4, which may incur layout challenges that we shall
address in due time. As already noted, larger capacitances in bias networks are generally
desirable in that they tend to mitigate, albeit perhaps incompletely, the overshoots associated
with an abrupt application of voltage Vkk. We shall observe somewhat dramatic response
overshoots when we address the issue of the transient response to voltage Vkk.
(2).
The area and peripheral dimensions associated with device capacitances compute in accord
with (4-155). We have
As1  As3  Ad 1  Ad 3  2W1 L  2.2 x 10 11 m 2
Ps1  Ps3  Pd 1  Pd 3  W1  4L  13.5 μm
In addition,
.
(E3-1)
As2  As4  Ad 2  Ad 4  2W2 L  2.25 x 10 10 m 2
(E3-2)
.
Ps2  Ps4  Pd 2  Pd 4  W2  4L  81 μm
In most simulators, these geometrical parameters are inputted in conventional MKS units
(meters, meters2, etc.)
(3).
Figure (5.14) displays the simulated static transfer characteristic, Ik versus Vkk. We can confirm that the current, Ik, ultimately reaches its constant value of 1.008 mA at Vkk ≈ 1.6 volts.
The current goes on to increase minutely to 1.0081 mA at Vkk = 4 volts. The 1.008 mA output
current is within 0.8% of the 1 mA design target. This minute increase in current suggests
excellent power supply rejection, which we understand requires a high output resistance, Rout.
Undoubtedly, we can lower this error to nearly zero by slightly reducing the gate aspect ratios
of transistors M2 and M4. No attempt is made herewith to reduce this error since it lies well
within routine processing and manufacturing tolerances typically embodied by integrated circuit design.
As already noted, the 1.008 mA current level is attained at about Vkk = 1.6 volts. An inspection of the network in Figure (5.12) affirms that Vkk must be large enough to supply at least a
- 433 -
Chapter 5
MOSFET Biasing
drain saturation voltage, Vdsat2, across the drain-source terminals of transistor M2, plus a gatesource bias, Vgs4, for transistor M4. Table (5.1) shows the operating point data for all Wilson
transistors in Figure (5.12), where at this operating point, Vdd = 3.8 volts, Vkk = 2.7 volts, and
Iref = 100 μA. We see from the static operating point data that Vdsat2 = 0.5060 volts, while Vgs4
= 1.1027 volts. Thus, Vkk ≥ Vdsat2 + Vgs4 = 1.609 volts, which is only 0.54% larger than the
extracted minimum required voltage value (≈ 1.6 volts) of Vkk.
1.2
Output Current Ik (mA)
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
Input Voltage, Vkk (volts)
Figure (5.14). Simulated static transfer characteristic, Ik -versus- Vkk, of the Wilson current
mirror shown in Figure (5.12) and studied in Example #5.3.
MODEL
ID
IBD
IBS
VGS
VDS
VBS
VTH
VDSAT
GM
GDS=1/ro
GMB
CBD
CBS
CGSOVL
CGDOVL
CGBOVL
CGS
CGD
CGB
M2
USCN
M4
USCN
M3
USCN
1.0073E-03
-2.7080E-12
-1.1152E-12
1.2371
1.5973
-1.1027
0.7160
0.5060
3.2979E-03
1.6219E-05
3.5151E-04
9.9478E-14
1.1978E-13
2.4000E-14
2.3250E-14
7.7000E-16
2.5444E-13
0.0000E+00
0.0000E+00
1.0081E-03
-1.1107E-12
-2.7662E-15
1.1027
1.1027
0.0000
0.5739
0.4985
3.2431E-03
1.5948E-05
5.4415E-04
1.1987E-13
1.5182E-13
2.4000E-14
2.3250E-14
7.7000E-16
2.5444E-13
0.0000E+00
0.0000E+00
1.0001E-04
-1.1071E-12
-2.7707E-16
1.1027
1.0973
0.0000
0.5770
0.4954
3.2253E-04
1.5781E-06
5.5825E-05
1.3350E-14
1.6919E-14
2.4000E-15
2.3250E-15
7.7000E-16
2.5444E-14
0.0000E+00
0.0000E+00
M1
USCN
9.9961E-05
-2.3499E-12
-1.1079E-12
1.2425
1.2425
-1.0973
0.7244
0.5029
3.2798E-04
1.6053E-06
3.6683E-05
1.1450E-14
1.3348E-14
2.4000E-15
2.3250E-15
7.7000E-16
2.5444E-14
0.0000E+00
0.0000E+00
Table (5.1). Simulated operating point data for the Wilson mirror in Figure (5.12). The operating point is
fixed by Vdd = 3.8 volts, Vkk = 2.7 volts, and Iref = 100 μA.
(4).
Figure (5.15) is the simulated frequency response for the shunt output resistance, Rout, of the
Wilson mirror operated at Vdd = 3.8 volts, Vkk = 2.7 volts, and Iref = 100 μA. Because of the
- 434 -
Chapter 5
MOSFET Biasing
transistor capacitances itemized in Table (5.1), this resistance monotonically degrades with
increasing frequency. At low frequencies, HSPICE yields Rout = 14.3 MEGΩ, which is
assuredly indicative of a high quality current sink. Let us see how this simulated value compares with the output resistance predicted by (5-48). To this end, we know that k = 10, while
Table (5.1) gives gm3 = 322.53 μmho and ro3 = 633.67 KΩ. Accordingly, (5-48) predicts a
shunt output resistance of Rout = 13.08 MEGΩ, which is 8.55% lower than the simulated
value. This error lies within the expected accuracy limits of our manual analysis.
Shunt Output Resistance (Meg)
15
12
9
6
3
0
0.001
0.01
0.1
1
10
Signal Frequency (MHz)
Figure (5.15). Simulated frequency response of the shunt output resistance for the Wilson current mirror shown in Figure (5.12) and studied in Example #5.3.
We have already noted that transistor capacitances incur a frequency rolloff in the output
capacitance response. It is therefore germane for us to study Figure (5.16), which shows the
frequency response of the shunt output capacitance, Cout, of the Wilson circuit operated at the
stipulated quiescent level. The simulated response shows essentially constant shunt output
capacitance of an amount slightly larger than 373 fF over a passband spanning a KHz to 10
MHz. When we study high frequency electronic amplifiers, we shall learn how to estimate
analytically the capacitances effectively manifested at network input and output ports.
Figure (5.17) displays the simulated transient response to the specified pulse train of voltage
Vkk. We witness dramatic current peaking whenever Vkk rises suddenly to 2.7 volts; indeed,
overshoots corresponding to currents larger than 10.6 mA are recorded. A negative current
peak of about 1.8 mA is also transparent whenever Vkk “turns off” to its zero value. In addition to this excessive positive and significant negative current peaking, we can see that the
circuit requires about 209 nSEC of settling time. In other words, it takes about 209 nSEC after voltage Vkk rises suddenly to its standby level of 2.7 volts for the Wilson mirror to achieve
its steady state output current of 1.008 mA.
ENGINEERING COMMENTARY:
We have a lot to talk about, although some parts of our discussion must remain parochial until we address more complex electronic circuits and systems. Let us begin by returning to Table (5.1). In that table, we note, as expected, that the gate-source voltages, Vgs, of transistors
M3 and M4 are identical. Moreover, and as we predicted earlier in view of including transistor M1 into the Wilson network, the gate-source voltages of M1 and M2 are nearly the same.
In fact, the gate-source voltages of M1 and M2 are so close that adjustment of the M2 gate aspect ratio, which would be aimed toward equalizing gate-source biases, is arguably unnecessary.
(5).
- 435 -
Chapter 5
MOSFET Biasing
Shunt Output Capacitance (fF)
374.0
373.5
373.0
372.5
372.0
371.5
371.0
370.5
370.0
0.001
0.01
0.1
1
10
Current, Ik (mA)
Voltage, Vkk (volts)
Signal Frequency (MHz)
Figure (5.16). Simulated frequency response of the shunt output capacitance for the Wilson
current mirror shown in Figure (5.12) and studied in Example #5.3.
3.0
2.5
2.0
1.5
1.0
0.5
0
12
9
6
3
0
-3
0
2
4
6
8
10
12
Time (SEC)
Figure (5.17). Simulated transient output current response to a pulse train excitation of the
Wilson current mirror shown in Figure (5.12) and studied in Example #5.3.
We observe in Table (5.1) that the active gate-drain capacitances, Cgd, of all transistors are
zero. This observation synergizes with our understanding of the manner in which the drain
depletion zones affect gate-drain capacitances of saturated transistors. In contrast, however,
overlap components to gate-drain (as well as to gate-source) capacitances prevail.
The bulk transconductance, gmb (= λbgm) bears no significance for transistors M3 and M4,
since both the source and bulk terminals of these two transistors are grounded. Our inspection of Table (5.1) indicates that the bulk transconductances for the remaining two transistors
remain respectively only moderately significant since both are smaller than 11.2% of the forward transconductance, gm of these devices. This is to say that λb1 = 0.112, while λb2 = 0.107.
Apparently, our decision to ignore body effect in M1 and M2 warrants applause.
The low frequency output resistance of more than 14 MEGΩ is laudable and is indeed indicative of the nearly constant current observed in Figure (5.14) for Vkk ≥ 1.6 volts. But we note
in Figure (5.15) that this driving point output resistance attenuates dramatically with increas- 436 -
Chapter 5
MOSFET Biasing
ing signal frequency. The non-constant nature to the output resistance is a perennial problem
with active current sources. It is caused, of course, by unavoidable transistor capacitances
and, at least in this case, the feedback nature of the Wilson topology. The problem is often
sufficiently severe in broadband networks to motivate circuit designers away from active current sinks and sources and towards conventional linear resistances. An acceptable, two-terminal, monolithic resistor doubtlessly does not have the resistance value indigenous to an
active circuit operated at low frequencies, but at very high signal frequencies, its resistance
value may, in fact, exceed that of a current source or sink.
The output capacitance of better than 370 fF is typical of active current sinks and sources and
contributes to the rather sharp decrease of output resistance over signal frequency. In the
present case, capacitances implicit to all transistors manifest the aforementioned settling time
of roughly 209 nSEC. This settling time corresponds to a frequency of only 4.8 MHz, which
explains why circuit designers are concerned with current sinks and sources that appear in the
forward signal flow paths of networks destined to operate at gigahertz frequencies.
Most importantly, the transient response displayed in Figure (5.17) causes great concern.
The overshoots, which derive from transistor capacitances whose voltages are incapable of
responding quickly to sudden changes in excitation, can damage transistors. It is therefore
understandable that in an attempt to reduce the kind of current spiking shown in Figure
(5.17), the power supplies applied to many high performance and particularly sensitive circuits are designed so that bus line voltages are brought to their steady state values gradually,
not abruptly. These regulated power supplies, which proactively address undesirable network
startup transients, are one of several reasons that explain why we have to wait for our laptop
computers, cellular telephones, GPS receivers, and such to “wake up.”
5.4.0. VOLTAGE REFERENCES
A voltage reference is active subcircuit whose output port sustains a voltage that is
suitable for biasing one or more other active subcircuits in a considered network. In the simplest
of routinely encountered designs, the reference voltage is used to energize the gate-source port of
a transistor whose drain current functions as a constant current source or sink. In these cases, the
Thévenin resistance we see looking into the reference output port need not be especially small
since the gate of the gate-source port the reference is intended to drive conducts no static current.
In high performance applications, stringent operating requirements are invariably imposed on the
open circuit output voltages and Thévenin output impedances of the voltage reference module.
For example, we may require a reference output port to drive biasing control ports of broadband
amplifiers, broadband operational transconductors, high bit-rate data converters, precision
instrumentation networks, high frequency voltage controlled oscillators, and other sophisticated
electronics. These control voltages may be used to establish predictable and reliable,
temperature invariant, and stable transconductances, I/O impedances or other performance
metrics that must be rendered substantively insensitive to spurious perturbations in the applied
power supply voltage. Moreover, the reference voltages must be relatively oblivious to a variety
of parasitic phenomena incurred by the layout or the general environment into which our
network is embedded.
5.4.1. ACTIVE VOLTAGE DIVIDER
We commence our present discussion by studying the active voltage divider offered in
Figure (5.18a). As usual, bulk connections are not delineated, but both transistor bulk terminals
are indeed returned to circuit ground. In the subject circuit, transistors M1 and M2 are identical
- 437 -
Chapter 5
MOSFET Biasing
except for the fact that the gate aspect ratio, W1/L1, of transistor M1 differs from the gate aspect
ratio, W2/L2, of M2 in accordance with the design stipulation,
Ip
Ip
Vdd
Vdd

M2
Vhn

x1
k12 Rx
Vref
M1
Vref
Rx
2
12
xk

Vhn

(b).
(a).
Figure (5.18). (a). Active voltage divider for a series interconnection of two NMOS diodeconnected transistors. (b). Passive model of the circuit in (a). Resistance Rx
is given by (5-57).
W1 L1
2
 k12
.
(5-49)
W2 L2
Both transistors function MOSFET diodes since their respective gate and drain terminals are
connected together. These connections ensure that the transistors operate in saturation. In the
absence of significant CLM, (5-4) and (5-5) are therefore applicable. Since fast responses are
not an issue in a static divider and indeed, in most biasing networks, the device channel lengths,
L1 and L2, can be large to placate the effects of CLM. Large channel lengths and commensurately large gate widths incur the additional advantage of increased device capacitances that
effectively ground any high frequency signals coupled parasitically to the output port of the divider. Additionally, the approximation of nominally equal threshold voltages, Vhn, between the
two transistors is valid if the gate oxide thicknesses of the transistors are matched and small.
The upshot of the foregoing discourse allows us to write

I p  βn2 Vdd  Vref  Vhn

2

 βn1 Vref  Vhn

2
.
(5-50)
Parameter n1 is directly proportional to W1/L1, and n2 is analogously proportional to W2/L2.
Thus, (5-50) combines with (5-49) to deliver
 k  1
Vdd
(5-51)
Vref 
  12
 Vhn .
k12  1  k12  1 
We observe that for k12 = 1, Vref is simply one-half of the supply line voltage. This result is
comforting in that k12 = 1 is tantamount to a series connection of two identical transistors (inclusive of identical gate aspect ratios) that are configured to operate as two-terminal elements. In
other words, the static characteristics of the circuit for k12 = 1 emulate those of a simple voltage
divider comprised of two identical resistances. Strictly speaking, however, we need to be mind- 438 -
Chapter 5
MOSFET Biasing
ful of the fact that (5-51) and the voltage result corresponding to the special case of unity k12 are
approximations because the body effect in M2 renders its threshold potential larger than that of
M1, which experiences no BITM.
The foregoing resistive divider interpretation can be expanded by modeling the circuit
in Figure (5.18a) by the behavioral representation in Figure (5.18b). In the latter diagram, the
current, Ip, is given by
V  2Vhn
I p  dd
,
(5-52)
 k12  1 Rx
whereupon voltage Vref follows as
V  2Vhn
 Vhn ,
(5-53)
Vref  Rx I p  Vhn  dd
 k12  1
which is identical to (5-51). The model electrically reflects the static performance of the twotransistor biasing cell if we choose the value of resistance Rx, such that the static power, Pdiss,
dissipated by the active divider equates to the power dissipated in the behavioral network.
Specifically,
V V  2Vhn 
2
(5-56)
,
Pdiss  Vdd I p  Vdd βn1 Vref  Vhn
 dd dd
 k12  1 Rx
where we have invoked (5-50) and (5-52). The last expression produces the requisite resistance,
Vdd  2Vh
Rx 
.
(5-57)
2
βn1  k12  1 Vref  Vh




EXAMPLE #5.4:
The circuit in Figure (5.18a) is to be designed to deliver a reference output
voltage, Vref, of 1.25 V when the supply line, which supports a static voltage, Vdd, of 3 V, delivers 5 mW of power to the active divider. The nchannel transistor utilized in the network is parameterized in Table (4.1).
Determine suitable gate aspect ratios for the two devices and confirm the
propriety of the design through simulations executed with HSPICE or
similar computer-aided design software.
SOLUTION #5.4:
(1).
With a supply voltage of Vdd = 3 V and a desired circuit power dissipation of Pdiss = 5 mW,
the drain current conducted by both transistors, which is also the power supply current, Ip, in
the circuit of Figure (5.18a) is Ip = Pdiss /Vdd = 1.667 mA. We are free to make this current
smaller than the indicated computed value since no one is going to ostracize a circuit designer
who delivers targeted circuit performance at reduced power dissipation levels.
(2).
Since the threshold voltage and transconductance parameter of the transistor are not known
explicitly, we initiate the design exercise by investigating the volt-ampere characteristics of
the transistor operated as a diode for the case of unity gate aspect ratio. The pertinent baseline circuit for this simulation is given in Figure (5.19), where the null voltage source in series with the drain terminal facilitates the extraction of the simulated drain current. The
transistor whose parameters appear in Table (4.1) features a channel length, L of 0.5 m. But
the static nature of the circuit of interest, together with a desire to mitigate the dominant im-
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Chapter 5
MOSFET Biasing
pact of channel length modulation, encourage adopting a channel length that is longer than
0.5 m. To this end, choose L =2 m and, of course, W = 2 m for the initial simulation.
Id

0


Vds

M1
W1 /L1
Figure (5.19). Circuit used to simulate the diode volt-ampere
characteristics of the transistors used in the voltage
divider design considered in Example #5.4.
(3).
An HSPICE simulation of the circuit in Figure (5.19) reveals Id = 23.537 A if Vds is set to
the desired reference output voltage of 1.25 V and W1/L1 = 2 m/2m = 1. This result implies the need to increase the gate aspect ratio of the device by a factor of 1.667 mA/23.537
A = 70.81, which means that W1 = (70.81)(2 m) = 141.6 m. At Vds = 1.25 V, the simulation for this increased gate aspect ratio delivers Id = 1.706 mA, which is higher than the maximum allowable current of 1.667 mA by about a factor of 1.023 (2.3%). If we decrease W1 by
this factor, we get W1  138 m. A simulation for this gate width update results in Id = 1.663
mA, which is close enough to the target current of 1.667 mA. For Vds = 1.25 volt and Id =
1.663 mA, HSPICE predicts a threshold voltage of Vhn = 699 mV. In the interest of completeness, Vds = Vref = 1.25 volt, Vhn = 699 mV, and Id = 1.663 mA predicts an effective value of
the transconductance parameter, n1, in (5-50) of n1 = 5.478 mmho/volt.
(4).
From (5-52), parameter k12 necessarily abides by
Vdd  Vref  Vh
k12 
.
Vref  Vh
(E4-1)
With Vdd = 3V, Vref = 1.25 V, and Vhn = 699 mV, k12 = 1.907. The square of this number,
which is 3.638, is, by (5-49), the factor by which the gate aspect ratio of transistor M2 in the
circuit of Figure (5.18a) must be smaller than the gate aspect ratio of the companion device,
transistor M1. Hence, for W1/L1 = 138 M/2 M, W2/L2  38 m/2 M. We find in accordance with the foregoing calculations, that HSPICE predicts an output voltage of Vref = 1.124
V, which is about 10% smaller than the design target of 1.25 V. By (5-51), we reason that a
decrease in parameter k12 is in order. To this end, we determine through iterative simulations
that k12 = 1.423 is appropriate, with the proviso that it increases the circuit power dissipation
to about 3.5 mW. In this particular case, we shall not be concerned by this power dissipation
increase. But in other designs, this increased dissipation may be a significant factor warranting further engineering attention. The revised k12 metric corresponds to W1/L1 = 77 m/2 m,
which delivers Vref = 1.253 V. Figure (5.20) depicts the final schematic diagram.
ENGINEERING COMMENTARY:
The biasing cell addressed herewith is an elementary example of a potentially viable biasing
cell. The design procedure and strategy offer a valuable engineering lesson in that they confirm that MOSFET circuit design adjustments are likely, if not inevitable, when the first order
design result is premised on simplified device models. In the present case, the significant
limitation to our first order analysis is our tacit neglect of bulk-induced modulation of the
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Chapter 5
MOSFET Biasing
threshold voltage for transistor M2. In particular, it turns out that in the final design solution,
the threshold potential of M2 is about 28% larger than the simulated 579 mV threshold voltage of transistor M1.
Id
3 V
M2
38 m/2 m
Vref
M1
77 m/2 m
Figure (5.20). Final schematic diagram of the active voltage
divider circuit designed in Example #5.4. The
HSPICE parameters of the transistors appear
in Table (4.1). The reference output voltage,
Vref, is 1.253 volts at 27 C.
While the output voltage result satisfies output voltage design requirements postured in the
problem statement, the circuit is nonetheless flawed in at least two respects. In particular, (551) confirms that the output response, Vref, is linearly dependent on the supply voltage, Vdd,
which is to say that Vref is vulnerable to any signal spurs that couple to the power line to cause
a change in the value of the supply line voltage. A second shortfall (unless k12 = 1) is the
dependence of Vref on the threshold potential, Vh, which renders Vref sensitive both to chip
temperature variations and vulnerable to body effect, which unfortunately is functionally
dependent on vagarious device model parameters. However, two positive notes do
reverberate. First, Vref is nominally independent of the transconductance parameter βn, and
hence, it is ostensibly insensitive to the mobility variable to which parameter βn is proportional. A second positive note is sounded by the functional reliance of voltage Vref on the
geometrical parameter, k12. In particular, since k12 is related to a ratio of transistor gate aspect
ratios, we can set this metric accurately.
5.4.1.1. Current Sink Application of the Active Divider
A common application of the active divider cell we have just investigated is the current
sink offered in Figure (5.21). In this diagram, the M1-M2 subcircuit is identical to the network in
Figure (5.18a). The output of the divider energizes the gate of M3 so that voltage Vref serves as
the gate-source biasing voltage, Vgs3, applied to M3. We also include a capacitor, Cp, in shunt
with the gate-source port of M3. This capacitor serves two fundamental purposes. First, if we
choose Cp large enough (more about this design requirement shortly), it serves as a high frequency short circuit that harmlessly routes to ground spurious signals that might invade the gatesource port of M3. For example, such invasion can materialize as a divided voltage response to
interference that couples to the power supply line. In turn, this interference can derive from
proximate radio frequency (RF) signals or, perhaps, from relatively poor regulation of the supply
line. Second, since a capacitor cannot change its voltage instantaneously (or even very quickly,
for that matter), Cp reduces any excessive transient overshoot evidenced at the divider output
port in response to the sudden application of power line voltage Vdd. From a circuit modeling
perspective, Cp superimposes with the gate-source capacitance, Cgs3, of M3. To be sure, this
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Chapter 5
MOSFET Biasing
effective increase in gate-source capacitance degrades the unity gain frequency of M3, and
potentially the overall bandwidth of the network. But the unity gain frequency of a transistor and
the bandwidth of the circuit into which the transistor is connected, are rarely crucial design issues
in networks earmarked for biasing purposes.
Ip
Vdd Vkk
M2
Ik
Rp
W2 /L2
Rout
Vref
M1
M3
Cp
W1 /L1
W3 /L3
Figure (5.21). Active divider used to bias a grounded source current
sink network to realize a nominally constant current, Ik.
If (5-49) remains applicable and negligible body effect prevails, voltage Vref in Figure
(5.21) remains given by (5-51). This contention follows from the fact that the gate of transistor
M3 and the compensation capacitance, Cp, conduct no static current. Additionally, we choose
the gate aspect ratio, W3/L3, of transistor M3 as
W3 L3
β
 k31  n3 ,
(5-58)
W1 L1
βn1
Vdd
Rl
Rl
Output #2
Output #1
Ik
Id4
Id5
M5
M4
Input #1
Input #2
Vkk
M2
W2 /L2
Ik = Id4+Id5
Rp
Rout
Vref
M1
W1 /L1
Cp
M3
W3 /L3
Figure (5.22). An illustration of the use of the current sink in Figure (5.21) to bias a balanced differential amplifier. The differential amplifier consists of identical transistors M4 and M5 and the identical resistive loads, Rl, imposed
on the drains of the matched transistor pair.
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Chapter 5
MOSFET Biasing
where k31 is viewed as a greater than one scaling factor. We observe that the gate of M3 is connected directly to the gate of transistor M1, while the drain of M3 is incident with a node that
supports a voltage of Vkk. In most embodiments of the subject mirror, voltage Vkk is smaller than
the power line voltage Vdd. For example, Vkk might represent the source terminal voltage of a
source-coupled differential pair whose resistively loaded drain terminals are biased by Vdd, as we
suggest in Figure (5.22). In the differential configuration, transistor M3 is called upon to establish a current path to ground that sinks the sum of the net drain currents, Id4 and Id5, flowing in
the matched transistors, M4 and M5, respectively. This is to say that current Ik necessarily flows
through the drain of M3, which we have previously referred to as the tail of the balanced
differential pair. Regardless of the specific nature of voltage Vkk, the fundamental design objective of the mirror is the establishment of a predictable M3 static drain current, Ik, which is virtually constant and assuredly predictable. Moreover, current Ik must be relatively impervious to
signal-induced perturbations in voltage Vkk, which is to say that the indicated output resistance,
Rout, must be sufficiently large.
Before plunging into the mathematical analysis of the network in Figure (5.21), let us
extol our engineering comprehension of the circuit, for it is insightful understanding that sows
the seeds of design propriety, creativity, and innovation. The first point to be made is that the
drawn channel lengths of all transistors in the subject biasing network can be relatively long (at
least as long as 1.5 μM), for fast response speeds in biasing circuits are rarely important. Indeed
slow response speeds in biasing circuits are usually preferred so that the potentially destructive
effects of significant transient overshoots are mitigated. Moreover, long channel lengths mediate
the effects of CLM and DIBL, which is to say that drain currents are rendered minimally dependent on drain-source voltages. This relative insensitivity to drain-source voltages is further fostered if design care is exercised to preclude a significant difference between the three observable
drain-source voltages; namely, (Vdd − Vref), Vref, and Vkk. To be sure, we certainly need not make
these three voltages identical, but in concert with relatively long channel lengths, the closer the
voltages are to one another, the less critical they are to the predictable determination of the static
drain currents. Yet another biasing advantage of long channels is the reduced carrier mobility
degradation incurred by lateral, drain-source electric fields. Negating significant mobility
degradation, not to mention the tacit neglect of DIBL, simplifies transistor modeling and postures transistor performance that is essentially independent of drain-source voltage and many
nebulously defined and difficult to control physical parameters. Finally, body effect is
manifested in transistor M2 since its bulk terminal is grounded while its source terminal is incident with the output port of the voltage divider. Significant body effect fosters observable differences in threshold voltages (of the order of 25% or so, as we have witnessed by way of simulation example). In turn, threshold differences promote a dependence of voltage Vref on the
threshold potentials of both transistors M1 and M2, even if the relative gate aspect ratio of the
transistors is one. Body effect phenomena are minimized if the transistors boast very thin oxides
(less than 80 Ǻ). Of course, one downside to thin gate oxides is that they exacerbate the charge
trapping that may accompany large vertical electric fields in the channel. These effects are held
to a minimum if the applied gate-source voltages are not excessive in comparison to their relevant threshold potentials. We recall from our long standing association with Schichman and
Hodges that for a desired or given drain current, gate-source voltages can be held small through
increases in gate aspect ratios.
In view of the foregoing discussion and since transistor M1, like transistor M2, is obviously saturated, current, Ip, which flows through the drains of transistors M1 and M2, is
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Chapter 5
MOSFET Biasing
Vref  Vdsat1 
2
Vhn 
1 
  βn1 Vref  Vhn  1 
 , (5-59)
V
V
λ
λ 



where Vref is the gate-source voltage, Vgs1, applied to M1, as well as the gate-source voltage, Vgs3,
which activates transistor M3. Moreover, (5-59) exploits the fact that the drain saturation voltage, Vdsat1, for M1 is
Vdsat1  Vgs1  Vh  Vref  Vh .
(5-60)

I p  βn1 Vref  Vhn

2


The drain current, Ik, conducted by M3 is, assuming the satisfaction of the M3 saturation requirement, Vk  (Vref − Vhn), follows as
Vkk  Vref  Vhn 
2
 ,
I k  βn3 Vref  Vhn 1 
(5-61)
Vλ




where the channel length, L3, of transistor M3 is presumed identical to L1, which is the drawn
channel length of M1. This channel length identity ensures that both transistors have nominally
the same CLM voltage, V, despite likely differences between their gate aspect ratios, W3/L3 and
W1/L1. Recalling (5-58), (5-59) and (5-61) combine to produce

Vkk  Vref  Vhn 
1 

Vλ


(5-62)
I k  k31 I p 
.
Vhn
1


Vλ










In (5-62), we note with more than casual interest that if voltage Vkk is of the order of the
gate-source voltage, Vref, developed across the gate-source terminals of both transistors M1 and
M3 and/or if
(5-63)
Vλ  Vkk  Vref  Vhn ,


the foregoing drain current is nicely approximated by
I k  k31 I p ,
(5-64)
As we have already surmised qualitatively, (5-64) posits an M3 drain current that matches the
current, Ip, conducted by transistor M1 to within a constant scale factor of k31. The result at hand
is similar to the fruits of analogous work we documented in Section (5.3.1).
An arguably more reliable realization of the current sink in Figure (5.21) is the structure in Figure (5.23), wherein transistor M2 in the former diagram is supplanted by an off chip,
constant current source, Ip. An analysis of this particular structure appears in Section (4.7.3) of
the preceding chapter. Current Ip flows through transistor M1 to produce a gate-source voltage,
Vref. Once this gate-source voltage is established, regardless of its precise value, current Ik tracks
with current Ip in accordance with (5-62) or its approximation in (5-64).
As we have already learned, the output resistance, Rout, seen looking into the drain terminal of transistor M3 in Figure (5.23) must be large if the sensitivity of current Ik with respect to
perturbations in voltage Vkk is to be minimized. We can deduce this output resistance through
mere engineering inspection. First, no signal appears across the gate-source port of M3 since
voltage Vdd in this network is a constant. Even if signal spurs superimpose with the static
component of Vdd, the presumably large capacitance, Cp, grounds the time domain response to
these spurs. With the signal component, Vgs3s, of gate-source voltage Vgs3 equal to zero, the
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Chapter 5
MOSFET Biasing
resultant drain-source signal current, gm3Vgs3s, in the low frequency, small signal model of M3 is
forced to zero. Then, we note the absence of body effect in M3. This means that the drainsource signal current, λb3gm3Vbs3s, is null because the bulk-source voltage, Vbs3, and therefore its
signal component, Vbs3s, applied to transistor M3 is clamped to zero. Accordingly, the only element in the low frequency equivalent circuit of M3 is the drain-source channel resistance, ro3. It
therefore follows that Rout = ro3, which is reasonably large for long drawn channel length and/or
a relatively small quiescent drain current (Ik) conducted by M3.
Vkk
Vdd
Ip
Ik
Rp
Rout
Vref
M1
M3
Cp
W1 /L1
W3 /L3
Figure (5.23). An alternative realization of the current sink in Figure (5.21).
Assuming transistor M3 is held in saturation and channel
length modulation is insignificant, current Ik is directly proportional to constant current Ip, which is typically realized accurately and controllably off chip.
We suggested in the preceding paragraph that large Cp in Figure (5.21) serves to short
circuit any parasitic signal voltage that may surface across the gate-source terminals of transistor
M3. Since the gate of M3 behaves as an open circuit to low and even to moderately high
frequencies, the net resistance seen by capacitance Cp is solely the resistance, Rp, which is manifested by the series interconnection of the two diode-connected transistors. We can evaluate this
resistance by replacing both M1 and M2 by their respective low frequency, small signal models.
For this resistance computation, we must replace Vdd and any spurious voltage component thereof by short circuits. Such replacement does not derive from habit. Instead, it follows from
Thévenin’s theorem, wherein all independent sources of energy must be set to zero while
evaluating a resistance between any pair of circuit nodes. We can then argue that Rp is a parallel
interconnection of two resistances that are indigenous to the models used to represent transistors
M1 and M2. One of these shunt resistances, say Rp1, is established by diode-connected transistor
M1; the other, say Rp2, by diode-connected transistor M2. Because the present M1 subcircuit is
identical to the M1 network studied in Figure (5.4a) we defer to Figure (5.4d) to write by inspection,
r
1
o1
R 
r 
.
(5-65)
p1
o1
g
1 g r
m1
m1 o1
The analytical form of resistance Rp2 differs slightly from that of Rp1 because while M1
experiences no body effect, M2 is subjected to BITM. Accordingly, we turn to Figure (5.24a),
which displays the low frequency, small signal model pertinent to computing the resistance, Rp2,
as the voltage to current ratio, Vx /Ix. Of course, resistance Rp2 is a portion of the net resistance
presented to the output port of the active voltage divider by diode-connected transistor M2. The
model at hand renders very clear that the controlling voltages, Va and Vb, satisfy the constraint,
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Chapter 5
MOSFET Biasing
Va = Vb = −Vx. This fact is incorporated into our small signal modeling exercise to produce the
equivalent structure in Figure (5.24b). Observe that the immediate impact of the foregoing voltage equivalence is to reverse the direction of the voltage controlled current sources in the model
of Figure (5.24a). We note, interestingly enough, that the controlling voltages for the reversed
current sources are the ohmmeter voltage, Vx. But this voltage appears directly across, and in
associated polarity convention with, each of the two controlled current sources, gm2Vx and
λb2gm2Vx. It follows that the gm2Vx source is equivalent to a branch resistance of 1/gm2, while
λb2gm2Vx produces the same branch current as does the branch resistance, 1/λb2gm2. We adopt
these observations in Figure (5.24c), which transparently delivers
Vdd
M2
gm2Va
W2 /L2
b2gm2Vb
ro2
 Va 
 Vb 
Rp2

Vx
Rp2

Vx
Ix
Ix


(a).

gm2Vx
b2gm2Vx
 Va 
ro2 Vx


1/(1b2)gm2
 Vb 
Rp2

Vx
Rp2

Vx
Ix
ro2 Vx

Ix


(c).
(b).
Figure (5.24). (a). Low frequency, small signal model for determining Rp2 = Vx /Ix, the resistance presented by the
M2 subcircuit to the reference voltage output port in Figure (5.22). (b). The model in (a), modified
to account for the fact that control voltages Va and Vb in the small signal model are identical to the
mathematical ohmmeter voltage, Vx. (c). Reduced version of the equivalent circuit in (b).
R
p2


1
1 
b2

g
r
m2
o2

r

o2
1  1 
b2

g
r
.
(5-66)
m2 o2
As we might have expected, the form of this expression is identical to that of Rp1 in (5-65) if we
ignore BITM, which forces the bulk transconductance to forward transconductance ratio, λb2, to
zero. Our intermediate conclusion is that the resistance, Rp, seen by capacitance Cp, is, by (5-65)
and (5-66)


 
r
r
1


o1
o2

R  R
R  
. (5-66)
p
p1 p2

1  g r   1  1  
g g
g
r
m1 o1  
m1
m2
b2 m2 o2 


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
Chapter 5
MOSFET Biasing
where we have invoked the reasonable presumptions, λb2 << 1, gm1ro1 >> 1, and gm2ro2 >> 1.
Recall that MOSFET transconductances are proportional to the square root of the product of gate
aspect ratio and static drain current. Noting in Figure (5.21) that the series interconnection of
transistors M1 and M2 forces these two devices to conduct the same static current, (5-49) implicitly gives rise to
g
m1  k .
(5-67)
12
g
m2
Thus, we can express resistance Rp as
1
R  R
R 
p
p1 p2
g g
m1
k
12

 12 
1 g
k
m2
(5-68)
.
m1
In view of the foregoing resistance disclosures, we now surmise that the net impedance,
say Zp(jω), established between the gate terminal of transistor M3 and ground is the parallel
combination of resistance Rp and capacitance Cp; that is,
R
1
p
(5-69)
Z  jω  
R 
.
p
p
j C
1  j R C
p
p p
The magnitude of this resistance-capacitance (RC) impedance is
R
p
Z  jω  
.
p

1  R C
p p

(5-70)
2
Since we wish Cp to emulate a short circuit for all signal frequencies above a prescribed minimum frequency, fmin6, we choose Cp to satisfy the design requirement,

min R pC p
 
2

2 f
R C
min p p

2
 1 ,
(5-71)
for which
1
ω
C
min p

1
2 f
C
min p

R
p
10

k
12
 12  1 gm1
10 k
.
(5-72)
generally suffices. In plain engineering language, (5-72) directs us to select capacitance Cp, such
that the magnitude of its impedance at a frequency of ωmin = 2πfmin is at least a factor of root ten
smaller than the resistance (in this case Rp) faced by capacitance Cp in the circuit. Since resistance Rp is usually small, Cp is likely to be large, especially if frequency fmin is small. Unfortunately, large capacitors cannot be synthesized monolithically. This limitation forces us to implement capacitance Cp as a discrete, off chip component. And while progressively larger
capacitances approximate progressively better short circuits, engineering reason must prevail, for
large capacitances can be bulky and are generally less reliable than are smaller valued capacitances.
6
Frequency fmin must be identified from the performance requirements of the system into which the current sink and
active voltage divider are embedded.
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Chapter 5
MOSFET Biasing
5.4.1.2. Multistage Current Mirror
We shall commonly encounter the need for several current sinks or sources in a variety
of analog circuit applications. For example, the signal flow path in an analog circuit may embody a cascade of balanced differential amplifiers, each of which requires a tail current to sink
the drain currents of each respective pair. In this case, each current sink need not be biased by a
distinct reference circuit. Instead, one reference circuit can be exploited to bias the gates of all
sinks, as we depict in Figure (5.25) for a general N-stage current mirror. In this diagram, the
reference circuit, which is comprised of transistor MO, current source Iref, and supply line voltage, Vdd, establishes the reference voltage, Vref, which is applied to the gates of all the remaining
N transistors. Unlike a multistage mirror realized in bipolar technology, which is plagued by
modest, but nonetheless nonzero, base currents, the input gate ports of the N transistors in the
MOSFET mirror do not load the reference circuit since the gates of MOSFETs do not conduct
static current. Then, with the understanding that
Vdd Vkk1
Vkk2
Vkk3
VkkN
Iref
Ik1
Vref
Cp
MO
Rout1
M1
x k1
Wo /Lo
Ik2
Ik3
Rout2
M2
Rout3
M3
x k2
IkN
x k3
RoutN
MN
x kN
Figure (5.25). Schematic diagram of a multistage current mirror. In the diagram, ki represents the gate aspect
ratio, Wi /Li of the ith transistor, normalized to the gate aspect ratio, Wo /Lo, of reference transistor
MO, where i = 1, 2, 3,···N.
k 
i
W L
i
W
o
i ,
o
(5-73)
L
we see that the current, Iki, conducted by the drain of the ith transistor in the N-stage cascade is
I  kI
.
(5-74)
ki
i ref
Of course, (5-74) requires that the ith transistor be biased in its saturation regime, where Vkki 
(Vref − Vhn), with Vhn naturally representing the threshold potential of all transistors (all devices
are presumed matched). Equation (5-74) also requires negligible CLM, which in turn requires
long channels and/or voltage Vkki reasonably close to the value of the reference potential, Vref.
A mere inspection of the schematic diagram in Figure (5.25) suggests immediately that
the output resistance, Routi, of the ith stage is simply the drain-source channel resistance, roi, of the
ith MOSFET in the cascade. This observation points out a potential shortfall of the cascade. In
particular, we recall that the channel resistance is inversely proportional to static drain current.
Thus, for progressively larger ki in (5-74), Routi = roi becomes progressively smaller.
5.4.2. LOW VOLTAGE REFERENCE
The low-voltage, low power integrated circuit culture that comports with present day
portable electronic systems demands current sinks, current sources, and other types of biasing
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Chapter 5
MOSFET Biasing
networks that operate gainfully with low static input voltages. To this end, the network shown in
Figure (5.26) is commonly used for several reasons. First, its open circuit output voltage, Vref,
need be only modestly larger than the threshold voltages of transistors M1 and M2. We should
interject here that the presence of BITM in M1 increases the M1 threshold voltage above that of
M2. Despite this inescapable fact, we shall adopt the simplifying stance of identical threshold
potentials in both transistors. Second, and to the extent that current source Iref approximates an
ideal current generator, output voltage Vref is independent of the supply line voltage, Vdd. Third,
the driving point output resistance, Rout, is relatively small and as we shall demonstrate, it is of
the order of the terminal resistance associated with our previously examined diode-connected
transistor. In contrast to a current output port, a small output resistance is a desired design target
for a voltage output port that establishes a predictable voltage capable of driving a variety of
other network ports within the considered integrated circuit.
Vdd
Iref
Vbias
Rout
Vref
M1
x1
M2
2
x k21
Figure (5.26). Schematic diagram of a voltage reference circuit capable of supplying a low voltage output,
Vref, and a reasonably low output resistance,
Rout. Observe that the gate aspect ratio of
transistor M2 is normalized to the gate aspect
ratio of transistor M1.
In the circuit of Figure (5.26), voltage Vbias, which can be either generated on chip or
supplied from a source that is extrinsic to the considered integrated circuit, is adjusted so that
transistor M2 operates on the ideal cusp between ohmic and saturated operating regimes. In
other words, Vbias is used to set the drain-source voltage, Vds2, of M2 to a value of (Vref − Vhn),
where Vhn identifies the threshold potentials of both NMOS devices. Aside from constraining
M2 to operate in its saturation domain, biasing the drain-source terminals of M2 at its drain
saturation level negates CLM in this transistor. Interestingly, setting Vds2 = (Vref − Vhn) imposes
a drain-source voltage, Vds1, on transistor M1 that is only one threshold drop (if we indeed ignore
body effect). This contention follows from the fact that Vds1 = Vref − Vds2 = Vref − (Vref − Vhn) ≡
Vhn. In view of this small drain-source bias, it is not immediately plausible that transistor M1 can
operate in saturation. But it indeed can. All we need to ensure saturation of M1 is Vhn ≥ (Vgs1 −
Vhn) = Vbias − Vds2 − Vhn = Vbias − Vref + Vhn − Vhn = Vbias − Vref. In brief, we require
V
 V V .
(5-75)
bias
ref
hn
This saturation constraint makes retrospective sense, for it implies an M1 gate to drain voltage,
Vgd1 = (Vbias − Vref), that is smaller than one threshold potential. But because of body effect and
carrier mobility degradation caused be lateral electric fields in the channel, the resultant drain- 449 -
Chapter 5
MOSFET Biasing
source saturation voltage of transistor M1 is likely to lie slightly below the idealized drain saturation level.
The flow of current, Iref, through the drains of both M1 and M2 in Figure (5.26) establishes a distinct relationship between the gate-source voltages of these two devices. We see that
the gate-source voltage, Vgs2, of M2 is reference voltage Vref and that the gate aspect ratio of M2
is a factor of k212 larger than that of transistor M1. With Vbias tuned to force Vds2 = (Vref − Vhn),
which ideally forces Vds1 = Vhn, we also witness no CLM in M1 and invariably negligible CLM
in M2. Thus, we assert,
I
ref
 
n1

V
gs1
V
hn

2
 
n1

V
bias
V
ref

2
 k2 
21 n1

V
ref
V
hn
which straightforwardly delivers
V
k V
21 hn .
V
 bias
ref
k 1

2
, (5-76)
(5-77)
21
By virtue of the constraint imposed by (5-75) on voltage Vbias,
 k  1
V
k V
21 hn   21
V .
 bias
(5-78)
V
ref
 k
 hn
k 1
 21 
21
The only electrical variable on which Vref is dependent is the transistor threshold voltage. Thus,
the output voltage, Vref, is comparatively small and independent of reference current Iref and
power line voltage Vdd. Of course, Vref can be no smaller 2Vhn, which is as expected since Vref
must supply the Vhn bias across the drain-source terminals of transistor M1 and the (Vref − Vhn)
bias imposed across the drain-source terminals of M2.
A downside of the foregoing result is that the reference voltage increases with temperature. We deduce this reality from (5-7), which, when combined with (5-78), gives us
 T  T 
 k  1
o  .
21



(5-79)

V
V (T )  2V 
ref
h
o
F
 k

 T 
 21  
 o 
Equation (5-79) portrays Vref as nominally PTAT7 with a voltage versus temperature slope that is
designable through the gate aspect ratio parameter, k21. As we learned when we studied BJT
biasing networks and as we shall continue to witness, the utility of PTAT voltage generators is a
appreciated in a multitude of analog networks.
The Thévenin output resistance, Rout, of the low voltage cell can be evaluated from an
investigation of its small signal equivalent circuit. To this end, the pertinent low frequency small
signal model is submitted in Figure (5.27), where gm1 and ro1 respectively denote the
transconductance and drain-source channel resistance of transistor M1, gm2 and ro2 correspondingly represent the transconductance and channel resistance of M2, and the current and voltage
sources, Iref and Vbias, are presumed ideal, constant sources of energy. Moreover, bulk-induced
modulation of the threshold voltage of transistor M1 is tacitly ignored. A straightforward analysis of the subject model reveals
R
out
7

V
r

 1 g
r
r

o1
m1 o1 o2
x 
,
I
1 g
1 g r r
x
m2
m1 o1 o2

Recall that “PTAT” is the astonishingly clever acronym for “proportional to absolute temperature.”
- 450 -
(5-80)
Chapter 5
MOSFET Biasing
Rout
Vdd
Iref
ro1
gm1V1
Rout
Vref
M1
Vbias
Ixgm1V1
 V1 

Ix
Vx
Ix

x1
Ixgm2VX
M2
ro2
gm2Vx
x k212
Figure (5.27). Low frequency, small signal model of the low voltage reference of Figure (5.26). The output
resistance, Rout, is determined as the ratio, Vx /Ix, of mathematical ohmmeter variables Vx and Ix.
which reduces to
R
out

r 
1  g 1  g r  r
m2
m1 o1 o2
r
o1

 1 g
r
1
m1 o1 o2
g
(5-81)
m2
for large gm1ro1 and large gm2ro2. The obvious implication of (5-81) is that insofar as the output
resistance is concerned, the configuration in Figure (5.26) behaves as a single diode-connected
transistor. We accentuate this disclosure with the macromodel in Figure (5.28), where we have
inserted (5-77) into (5-76) to stipulate quantify the reference current, Iref.
Since current Iref in Figure (5.27) is
2
2
V
 k

V 
2
hn    
21  V
   bias
V
I
,
(5-82)
ref
n2  k  1 
n1  k  1 
bias
hn
21


 21

we are gifted a clue as to how the voltage, Vbias, which is applied to the low voltage reference
network, might be implemented electronically. This clue is exploited in Figure (5.29) where the
gate aspect ratios of transistors M1, M2, and M3, satisfy
Vdd
Vdd
Vbias
Low Voltage
Reference
(
n2
Rout
Vref


Iref =
Vbias  Vhn
k21  1
R
)2
out
M2
Vref
[Figure (5.26)]
x k212
Figure (5.28). Approximately electrically equivalent macromodel of the low voltage reference provided in
Figure (5.26).
- 451 -
Chapter 5
MOSFET Biasing
Vdd
Rout
Iref
Iin
Vbias
M3
Vref
M1
M2
Figure (5.29). Alternative version of the low voltage reference in Figure
(5.26), wherein voltage Vbias is implemented electronically
by diode-connected transistor M3 and an adjustable, off
chip current source, Iin. Equation (5-83) defines the requisite relative gate aspect ratios for all three transistors.
W
W
2  k2 1
21 L
L
2
1
.
(5-83)
2
2
 k
 W
 1  W
3  
21 
1  
2





L
k 1 L
k 1 L
 21
 1
 21
 2
3
Ideally, the current identified in Figure (5.29) as Iin is identical to the originally stipulated reference current, Iref. But in recognition of the vagarious nature of a monolithic fabrication process,
we implement this current in the form of an adjustable, likely off chip, current source, Iin. In this
way, we can adjust current Iin to fine tune voltage Vbias so that the drain-source voltage established on transistor M2 is its drain saturation voltage, as stipulated earlier. If current Iin is implemented as an off chip branch element, reference current Iref need not be an off chip current
source. It should also be clear that since the gate terminals of transistors M1 and M2 conduct no
low frequency currents and are therefore electrically isolated from the appended M3 subcircuit,
the output resistance indicated in Figure (5.29) is unchanged from the value predicted by (5-81).
W
A popular application of the low voltage reference in Figure (5.29) is the high output
resistance, cascode current mirror depicted in Figure (5.30). In this diagram, current Iin, which is
usually an off chip current source, is adjusted to set the drain-source voltage of transistor M2 to
(Vref − Vhn), which is, of course, the idealized drain saturation voltage of M2. Voltage Vkk must
be sufficiently large to guarantee that transistors M4 and M5 in the cascode current sink operate
in saturation. We note that transistor M4 mirrors the current, Iref, which is conducted by transistor M2, with a scale factor of kok212/k212 = ko. In order to equalize the current densities of transistors M4 and M5, as well as minimize the drain saturation voltage of M5, it is a good idea to set
the gate aspect ratio of M5 equal to that of M4. Thus, with body effect in M5 ignored and CLM
effects minimized, the output current, Ik, of the cascode sink reflects the approximation,
I  k I
.
(5-84)
k
o ref
This result confirms of our intuitive suspicion that a stable and accurately predictable output current mandates an equivalently stable and predictable reference current, Iref. Additionally, a suitably large, and likely off chip, capacitance, while not shown in the subject schematic diagram,
- 452 -
Chapter 5
MOSFET Biasing
might be required from the gate of transistor M2 to ground if the shunt resistance associated with
reference current source Iref is not big enough to ensure adequate rejection of the supply line voltage spurs. Recalling (5-81), this capacitance must establish an impedance magnitude at the lowest system frequency of interest that is much smaller than the approximate output resistance,
1/gm2, of the reference voltage circuit.
Vdd
Vkk
Iref
Iin
Vbias
Ik
M1
M5
x1
M3
x kok21
M2
 k

x  21 
 k  1
 21

2
Rok
2
M4
2
x k21
Vref
x kok21
2
Figure (5.30). The low voltage reference used to bias a high output resistance,
cascode current source. Observe that all gate aspect ratios are
referred to the gate aspect ratio of transistor M1.
The output resistance, Rok, of the cascode current sink is laudably very large owing to
the deployment of transistor M4 as a source degeneration element for transistor M5. In order to
quantify this assertion, we turn to the low frequency, small signal equivalent circuit in Figure
(5.31). The model reflects the absence of bulk-induced threshold modulation in transistor M4
and the presumption of negligible body effect in transistor M5. The current sources, Iin and Iref in
Figure (5.30) are set to zero because we interpret these applied energy elements as ideal, constant
current sources. Moreover, we have replaced diode-connected transistor M3 by a resistance,
1/gm3, which is an action that presumes the M3 drain-source channel resistance, ro3, is such that
gm3ro3 >> 1. In accordance with (5-81), we have also represented the Thévenin output resistance
of the voltage reference circuit driving the gate of M4 as the approximation, 1/gm2.
An inspection of the subject circuit model shows that since no current can enter the gate
of transistor M4, the voltage drop across the resistance, 1/gm2, is zero, which forces control voltage Vb to zero. This means that transistor M4 behaves as a simple two terminal resistance that
equals the M4 channel resistance, ro4. In other words, ro4 functions as a large source degeneration resistance for transistor M5. With Vb = 0, gm4Vb = 0, which suggests that the current conducted by ro4 is simply the mathematical ohmmeter current, Ix. Since the gate of transistor M5,
like the gate of M4, conducts no low frequency current, the control voltage, Va, follows as Va =
−ro4Ix. In turn, the current flowing through resistance ro5 is (Ix − gm5Va) = Ix(1 + gm5ro4). These
discoveries and the venerable KVL readily produce the output resistance result,
V
R  x  r  1 g r r ,
(5-85)
ok
o4
m5 o4 o5
I
x


which is substantively larger than either of the relatively large channel resistances, ro4 and ro5.
- 453 -
Chapter 5
MOSFET Biasing
Rok
Vx
Ixgm5Va
ro5
gm5Va
1/gm3
 Va 
Ix
Ix
Ixgm4Vb
ro4
gm4Vb
1/gm2
 Vb 
Ix
Figure (5.31). The approximate, low frequency, small signal equivalent circuit
of the cascode current sink appearing in Figure (5.30). The
model is used to find the output resistance, Rok, which is determined analytically as the ratio, Vx/Ix, of the mathematical
ohmmeter variables, Vx and Ix.
EXAMPLE #5.5:
In the low voltage, cascode current sink of Figure (5.30), set the nominal
values of current Iin, current Iref and voltage Vkk to Iin = 100 μA, Iref = 100
μA, and Vkk = 3.5 volts. Since the circuit is fundamentally a static network, all transistors, whose SPICE parameters appear in Table (4.1) can
have relatively large drawn channel lengths of, say L = 1.5 μm. Let
transistor M1 have a gate aspect ratio of 4.5 μm/1.5 μm. Use HSPICE or
equivalent computer-aided design software to design the circuit for a target output current, Ik, of 500 μA. Investigate the specific value of current
Iin that sets the drain-source voltage of transistor M2 to its drain saturation
value. Adjust the relevant gate aspect ratios so that at the nominal settings
of Iin, Iref, and Vkk, all transistors operate in accordance with the results of
the analyses in this subsection of material. Determine the individual
ranges of Iin and Vkk over which current Ik is held reasonably constant near
its 500 μA target. Finally, simulate the real part, gok = 1/Rok, of the small
signal admittance seen looking into the drain of transistor M5. Examine
carefully this frequency response plot of the network output conductance.
SOLUTION #5.5:
(1).
Since transistors M1 and M3 are driven by ideal sources of constant current, we shall simulate
the network in Figure (5.30) with voltage Vdd set to zero. Realistically, however, current
sources Iin and/or Iref are implemented either on chip or off chip with active devices.
Pragmatically, therefore, voltage Vdd must be sufficiently large to bias the active current
source devices, as well as transistors M1, M2, and M3 in the circuit schematic.
(2).
Parameter k21 must be large enough to minimize the indicated reference voltage and the
corresponding drain saturation voltage of transistor M2. Since we have not been given a tar- 454 -
Chapter 5
MOSFET Biasing
get voltage for Vref, we somewhat arbitrarily choose k21 = 4. Accordingly, our first iterated
gate width for transistor M2 is W2 = k212W1 = 16(4.5 μM) = 72 μM, whence a gate aspect ratio for transistor M2 of 72 μM/1.5μM = 48. It follows that for M3,
2
2
 k

4
(E5-1)
W3   21  W1     4.5 μM   2.88 μM ,
5
 k21  1 
which gives an M3 gate aspect ratio of 2.88 μM/1.5 μM = 1.92. Since we wish to have Ik =
500 μA with Iref = 100 μA, and transistors M2 and M4 obviously form a current mirror, we use
ko = Ik/Iref = 500 μA/100 μA = 5, which means that the gate width of transistor M4 is W4 =
kok212W1 = (5)(16)(4.5 μM) = 360 μM. In order to equalize the current densities between M4
and M5, we set the gate aspect ratio of both of these transistors to 360 μM/1.5 μM = 240.
There is no need to calculate the periphery and area parameters for all devices until finalized
gate aspect ratios are determined.
(3).
Our first simulation chore is to examine the quiescent operating points of all transistors to ensure that they operate in saturation. Moreover, we recall that we require Vds2 = Vdsat2. For the
quoted input currents and the calculated gate aspect ratios, HSPICE predicts Ik = 501.84 μA,
Vds2 = 176.3 mV, and Vdsat2 = 154.0 mV. Changing the gate aspect ratio of M1 to secure
proper circuit operation is messy in that it requires changes to the gate aspect ratios of transistors M2 and M3. Thus, we elect to perturb current Iin appropriately.
After a few playful iterations, we find that Iin = 94.4 μA delivers Vds2 = 154.3 mV, Vdsat2 =
154.0 mV, and Ik = 501.79 μA. Voltages Vds2 and Vdsat2 are close enough for government
work, while current Ik can be tweaked by changing the gate aspect ratio of transistor M4.
Such a change does not require changes in the gate aspect ratios of transistors M1, M2, and
M3, since the current mirroring scale factor between M2 and M4 is determined by parameter
ko, and not by k21. But to equalize current densities in transistors M4 and M5, we should
match the gate aspect ratio of M5 to the new gate aspect ratio of M4. We find that with Iin=
94.4 μA, an M4 (and M5) gate aspect ratio of W4/L4 = 358.7 μM/1.5 μM = 239.1 results in Ik
= 500.0 μA, which is the design target. Under these conditions, HSPICE delivers Vbias = 1.48
volts and Vref = 706.9 mV. The latter voltage is less than 133 mV above the threshold voltage
of transistor M4.
We should mention that with W1/L1 = 4.5 μM/1.5 μM, W2/L2 = 72 μM/1.5 μM, W3/L3 = 2.88
μM/1.5 μM, W4/L4 = W5/L5 = 358.7 μM/1.5 μM, Iin = 94.4 μA, Iref = 100 μA, Vkk = 3.5 V, and
Vdd = 0 V, transistor M1 is close to operating in its saturation domain. Strictly speaking,
however, it functions in its ohmic regime since our HSPICE simulations confirm Vds1 = 552.7
mV, while Vdsat1 = 661.2 mV. In other words, the M1 drain-source voltage is 108.5 mV below
its drain saturation value. A fundamental reason for this disparity is that M1 is subjected to
body effect, which renders its threshold voltage larger than the threshold potential of transistor M2. Indeed, the threshold potential for M1 is Vhn1 = 606.8 mV, while for M2, Vhn2 = 575.3
mV. Of course, the threshold voltage influences both the M1 gate-source voltage commensurate with the observed 100 μA drain current in this device, as well as the corresponding drain
saturation voltage.
The ostensibly meager M1 intrusion into its ohmic regime engenders a non-zero active
component to the net gate-drain capacitance. That is, the net gate-drain capacitance of M1 is
not simply precipitated from an oxide overlap with the drain volume. The enhanced gatedrain capacitance can prove problematic in high-speed networks, which our current sink
surely is not. As long as the static performance of our network remains true to our design targets, we shall therefore ignore this ohmic regime issue. For the record, we do find that all
other transistors operate solidly within their saturation domains.
(4).
We can now compute the periphery and area dimensions for all transistor capacitances.
Borrowing from (E3-1) and (E3-2),
- 455 -
Chapter 5
MOSFET Biasing


As1  Ad1  1.35 10 11 m 2
Ps1  Pd1  10.5 μM


,
(E5-3)

,
(E5-5)
As2  Ad2  2.16 10 10 m 2
Ps2  Pd2  78.0 μM

As3  Ad3  8.64 10 12 m 2
Ps3  Pd3  8.88 μM
and finally,
(E5-2)
,


As4  Ad4  As5  Ad5  1.08 10 9 m2
Ps4  Pd4  Ps5  Pd5  365 μM
(E5-6)
.
7
Output Current, Ik (mA)
6
5
4
3
2
1
0
0
40
80
120
160
200
Input Current, Iin (A)
Figure (5.32). The simulated dependence on input current Iin of the current sink output current,
Ik, for the network studied in Example #5.5.
(5). Figure (5.32) displays the static transfer characteristic between input current Iin and output
current Ik, The input current region below roughly 80 μA is impertinent owing to our adopting ideal, as opposed to realistic, current sources for currents Iin and Iref. Fundamentally, an
output current of nominally 500 μA is achieved for 90 μA ≤ Iin ≤ 200 μA. More precisely, the
simulations show that Ik varies from 507.82 μA at Iin = 90 μA to 502.19 μA at Iin = 200 μA. In
other words, we observe a delightfully small 1.1% change in output current Ik over the 110
μA change in applied input current, Iin.
(6).
In Figure (5.33), we show the simulated dependence of output current Ik on applied voltage
Vkk. The curve confirms that current Ik remains essentially constant at near its 500 μA target
value over an impressively wide range of voltage Vkk values. Specifically, Ik varies from
496.85 μA at Vkk = 390 mV to 500 μA at Vkk = 4 volts.
(7).
Figure (5.34) projects the simulated frequency response of the shunt output conductance, gok,
where we understand that gok is merely the inverse of the resistance, Rok, in the schematic diagram of Figure (5.30). Both good news and bad news surface from the fruits of this simulation. The good news is that at very low signal frequencies, HSPICE predicts gok = 21.66
nmho, which corresponds to Rok = 46.17 MEGΩ. Obviously, this shunt output resistance is
- 456 -
Chapter 5
MOSFET Biasing
very large, and it therefore conflates with our engineering expectations of a high quality current sink. The result also agrees reasonably well with our theoretic result in (5-85). Specifically, at the operating point defined earlier, HSPICE yields ro4 = 84.40 KΩ, ro5 = 83.33 KΩ,
and gm5 = 5.758 mmhos, whence, by (5-85), Rok = 40.66 KΩ. This approximately 13.5% error is reasonable in light of the simplified nature of our small signal model.
500
Output Current, Ik (A)
400
300
200
100
0
0
1
2
3
4
Input Voltage, Vkk (V)
Shunt Output Conductance, gok (mho)
Figure (5.33). The simulated dependence on input voltage Vkk of the current sink output
current, Ik, for the network studied in Example #5.5.
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
0.001
0.01
0.1
1
10
Signal Frequency (MHz)
Figure (5.34). The simulated frequency response of the shunt output conductance of the
current sink shown in Figure (5.30) and addressed in Example #5.5.
The bad news is that the plot in Figure (5.34) infers that our high performance current sink is
a potentially unstable network. In particular, we should be alarmed by the fact that above a
signal frequency in the neighborhood of 1 MHz, gok is negative. From a simplistic point of
view, we surmise that since positive conductance dissipates power, negative conductance
must generate power. But we expect our network to dissipate the power it receives from an
applied signal source, as opposed to surprising the signal source with signal power reflected
from its own output port and back to the applied source of signal. In other words, and despite
- 457 -
Chapter 5
MOSFET Biasing
the fact that our current sink is designed expressly to establish a quiescent operating point,
any high frequency component in voltage Vkk produces signal power reflected back to Vkk.
Because of this signal reflection, we must view our network as potentially unstable electronics. We say “potentially unstable” because the net effective resistance seen at the output port
depends on the electrical nature of the external load imposed on this port. For example, if the
conductance of a passive load appended to the output port of the current sink exceeds the
magnitude of the negative conductance manifested by the sink at its output port at all signal
frequencies of interest, the net conductance established at the output port is positive, and the
loaded network remains operationally stable. Otherwise, our network is indeed unstable.
Ik
Vkk (3.5 V)
Iin
Iref
1.5 pF
(94.4 A)
(100 A)
Rok
10 pF
M1
M5
V
bias

Vdd
(0
V) 
M3
2.88
1.5
4.5
1.5
358.7
1.5
M2
72
1.5
Vref
M4
358.7
1.5
Figure (5.35). The current sink of Figure (5.30), compensated to ensure unconditional stability at all signal frequencies. The dimensions of the numerators and denominators of all gate aspect
ratio are in microns. Voltage Vdd is set to zero because of the use of the ideal current
sources for currents Iin and Iref.
We shall have much more to offer later as regards stability issues and the mitigation of potential instabilities. For now, potential instability can be neutralized by incorporating a 10 pF
capacitor from the gate of transistor M5 to ground and a 1.5 pF capacitor between the gate
and drain terminals of M5. Our compensated structure is submitted as Figure (5.35). The
first of these two compensation capacitors effectively ground the gate of transistor M5 at high
frequencies, while the second (1.5 pF) capacitor slows down the response speed, thereby
increasing the signal delay time, of M5. As we have noted, these compensation measures receive definitive attention later. For now, we relish the fact that the two capacitors render our
compensated current sink unconditionally stable, as is projected by the frequency response of
the current sink output conductance in Figure (5.36). We note therein that the subject
conductance remains positive for all frequencies. The introduced capacitances do not alter
the low frequency output conductance since capacitances act as open circuits at low signal
frequencies. But we note, with more than mere passing concern, that the output conductance
rises dramatically, and therefore the output shunt resistance falls precipitously, at progressively higher frequencies. In other words, our active current sink, while assuredly stable, becomes progressively less indicative of an ideal current sink as the frequency of the signal
component implicit to Vkk increases.
ENGINEERING COMMENTARY:
Numerous circuit design and analysis lessons derive from this example. The first, and perhaps most important, of these lessons is that the satisfaction of quiescent operating specifications does not tell the complete story in which we, as presumably skilled and competent circuit designers, must be well-versed. To wit, after we jiggled a couple of gate aspect ratios
and systematically adjusted the value of the applied input current, Iin, we satisfied all of the
quiescent operating specifications articulated in the problem statement. Had we not examined the frequency response of the driving point output admittance (or impedance) of our
- 458 -
Chapter 5
MOSFET Biasing
Shunt Output Conductance, gok (mho)
current sink, we would have courted possible processing disaster by prematurely (and
inappropriately) claiming design success. In particular, the simulated real part of the driving
point output admittance infers potential high frequency instability, which indeed is not
uncommon in current sinks and sources that utilize feedback and boast huge Thévenin output
resistances. A simulated transient analysis to a step form of voltage Vkk would have corroborated our potential instability revelations by displaying significant and/or prolonged time
periods of response overshoots and undershoots, if not actual self-sustaining sinusoidal
oscillations.
1.0
0.8
0.6
0.4
0.2
0
0.001
0.01
0.1
1
10
Signal Frequency (MHz)
Figure (5.36). The simulated frequency response of the shunt output conductance of the compensated
current sink shown in Figure (5.35) and addressed in Example #5.5.
The second lesson to be learned is that the manual analyses we executed to ascertain the static
and low frequency performance of our current sink are gratifyingly accurate. For example,
we needed to reduce current Iin by only 5.6% from its nominal 100 μA value to achieve proper
biasing of transistor M2. Moreover, our computed low frequency output resistance was low
by 13.5%. While the latter error does not pass the taste and smell tests for blatant insignificance, it, along with the aforementioned 5.6% current adjustment, lies well within the tolerances that are typical to a monolithic circuit realization. Yet another laudable example of
analytical propriety is embraced by the gate aspect ratios of transistors M4 and M5, which
needed to be reduced from their respective nominal values of 360 by only 0.36% to 358.7.
The third lesson learned is that simulations nicely and insightfully complement necessarily
simplified manual work. In this case, HSPICE clearly reveals that body effect in transistor
M1 makes it difficult to operate M1 in saturation when transistor M2 operates on the cusp between ohmic and saturation domains.
We should also have derived two other items of interest from the HSPICE simulations. The
first of these deals with Figure (5.32). In particular, setting Iin to 94.4 μA places the input
operating point of our current sink fairly close to the lower limit of Iin that is commensurate
with the targeted 500 μA output current goal. Depending on the accuracy, reliability and
reproducibility of Iin, this proximity of the quiescent value of Iin to the lowest allowable value
of Iin may require additional design modifications, which we did not pursue here. The second
issue offers news that is more positive. In the static transfer curve of Figure (5.33), the fact
that the output current is virtually independent of applied voltage Vkk purports very high output impedance for, as we have come to understand, infinitely large output impedance begets
zero sensitivity to applied voltage. Of course, this prognosis is germane only to static, zero
- 459 -
Chapter 5
MOSFET Biasing
frequency conditions and does not illuminate the potential instability problem we uncovered
at high signal frequencies.
5.5.0. SUPPLY-INDEPENDENT BIASING
We have applauded biasing networks delivering static responses that are independent of
power supply voltages. Supply voltage independence circumvents the effects of poor supply line
regulation, noise and spurious other signal coupling to the supply line, battery degradation, and
other miscellaneous phenomena. At this point of our electronic system travels, such independence has been accomplished by inserting a current source, which is ideally characterized by
infinitely large terminal impedance, between the supply voltage and the electronic system that
the supply line is intended to activate. The downside to this design tack is that ideal current
sources and sinks live and prosper only within the hallowed halls of academe. Fortunately, however, reasonable approximations of ideal current sources can be designed and implemented as a
means of securing adequate power supply rejection in high performance electronic systems.
5.5.1. SUPPLY-INDEPENDENT CURRENT SOURCE
An example of a practical alternative to the current source approach for mitigating
power line uncertainties is the five-transistor network shown in Figure (5.37). The circuit uses
three PMOS transistors and two NMOS devices to establish an output current, Io, which can be
supplied to any conductive, two terminal load. In this case, the load is taken to be a simple linear
resistance, Rl. As long as the power supply voltage, Vdd, is large enough to sustain saturation of
transistors M2, M4, and M5, and CLM in these three transistors is insignificant, current Io is
demonstrably independent of voltage Vdd. We note in passing that the diode-connected transistors, M1 and M3, are guaranteed to operate in saturation by virtue of their diode-type
interconnections.
Vdd
x1
x1
x kp
M4
M3
M5
IQ
M1
x1
IQ
Io
M2
2
x k21
R
Rl
Figure (5.37). Schematic diagram of a biasing network that delivers an
output current, Io, which is nominally independent of the
power supply voltage, Vdd. Although substrate terminals are
not shown, the bulk substrate terminals of the three PMOS
transistors are returned to the positive bus line, while the
bulk terminals of the two NMOS devices are grounded.
Because transistors M3 and M5 comprise a classic current mirror and since the gate as- 460 -
Chapter 5
MOSFET Biasing
pect ratio of transistor M5 exceeds that of M3 by a factor of kp, the output current is given simply
by Io = kpIQ. Of course, this claim ignores CLM, body effect, and all other second order transistor modeling phenomena. Consequently, we conclude immediately that if IQ can be made
independent of Vdd, output current Io must similarly be invariant with Vdd.
We see that current IQ flows through both transistors M1 and M4. Because of the identical gate aspect ratios in the M3-M4 mirror, current IQ is also conducted by transistors M3 and
M1. But the gate aspect ratio of transistor M2 is larger than the gate aspect ratio of M1 by a factor of k212. Accordingly, the gate source-voltage, Vgs2, of M2 is necessarily smaller than Vgs1, the
gate-source voltage developed on M1. The resultant difference, (Vgs1 − Vgs2), of these two gatesource potentials necessarily appears across the resistance, R, which degenerates the source of
M2. Our stalwart buddy, George Ohm, insists that IQ derive as this difference voltage divided by
R. But remember that IQ flows through M1 and therefore Vgs1 is almost entirely determined by
IQ. Moreover, IQ flows through M2, which means that Vgs2 is similarly a function of quiescent
current IQ. These current-voltage dependencies allow hint as to how supply independence of IQ,
whence output current Io, can be achieved. In particular, since current IQ satisfies
V
V
gs1
gs2
I 
,
(5-86)
Q
R
and both Vgs1 and Vgs2 are functionally dependent on current IQ, it follows, that IQ is independent
of Vdd and other circuit variables. Let us now examine the details that analytically underpin this
intuitive glimpse.
From the circuit diagram in Figure (5.37), we see that to the extent that CLM is negligible,
I
Q
 
n
V
gs1
V
hn

2
 k2 
21 n
V
gs2
V
hn

2
,
which gives rise to the voltage interrelationship,
V
V
gs1
hn
V 
V
.
gs2
hn
k
(5-87)
(5-88)
21
We should note that (5-87), in addition to being oblivious to CLM effects, tacitly ignores body
effect in transistor M2. This body effect is negligible for thin oxide transistors and is minimized
by ensuring that degeneration resistance R is small. We see that (5-87) postures an unambiguous
functional dependence of both voltages Vgs1 and Vgs2 on static current, IQ. Using (5-86),
I
Q

V
gs1
V
gs2

V
gs1
V
hn
  V
gs2
V
R
R
Upon inserting (5-88) into (5-89), we determine that

1 

 V 1 
V
gs1
hn 
k 
 k  1

21 

  21
I 
Q
 k R 
R
 21 
where we have once again profited from (5-87). If we
determine that


- 461 -
hn
I
Q
n
.
(5-89)
,
(5-90)
square both sides of this expression, we
Chapter 5
MOSFET Biasing
2
1  k 21  1 

 ,
I 
(5-91)
Q
 n  k 21 R 
which is indeed independent of the power line voltage, Vdd. Of course, this voltage independence
is observed if and only if voltage Vdd is larger than the minimum line voltage commensurate with
ensuring the saturation of all transistors embedded in the considered biasing network. Although
current IQ and thus, the output current,
k
p  k 21  1 


I  k I 
o
p Q
 n  k 21 R 
2
,
(5-92)
are independent of the applied static voltage, Vdd, currents IQ and Io are temperature variant. In
particular, transconductance coefficient βn decreases with increasing temperature because of its
direct dependence on the mobility of channel charge carriers. If we assume that resistance R is
independent of temperature, which is less than an entirely rational declarative, we see from (5-6)
that current Io in (5-91) rises as a three-half power law of temperature.
An interesting aspect of (5-91) is that it produces a constant device transconductance.
A confirmation of this contention compels a return to (5-87) to obtain the forward transconductance, gm1, of transistor M1. We have, recalling our small signal modeling ventures in the
preceding chapter,
I
Q
(5-93)
g

 2 V
V
 2  I .
m1
n gs1
hn
n Q
V
gs1


If we insert (5-90) into (5-92), we get
 k  1
,
(5-94)
g
 2  I  2  21
m1
n Q
 k R 
 21 
which clearly infers a predictable transconductance that is determined exclusively by the normalized gate aspect ratio parameter, k21, and circuit resistance R. We note in passing that for k21 =
2, gm1 = 1/R; that is, the inverse of the source degeneration resistance, R, defines the forward
transconductance. Analogous current independent results can be obtained for the transconductances of transistors M2 and M5.
We should highlight the significance of a transconductance that is invariant with bias
currents and voltages. This importance stems from the fundamental fact that the forward
transconductance of any transistor is a measure of the I/O gain that can be supplied by that
transistor when operated with its source terminal grounded. To the extent that the I/O gain is
directly proportional to forward transconductance, constant transconductance means that the
observable gain is rendered constant, independent of bias settings and signal levels. In other
words, perturbations in quiescent operating points caused by signal swings do not incur changes
(or at least incur only minimal changes) in forward transconductance. In a word, I/O nonlinearities are at least partially mitigated. Recall that BITM in transistor M2 is held to a minimum if
resistance R is kept small. We now have a second reason that compels small R. In particular, the
fact that gm1 (and other transistor transconductances) is inversely proportional to resistance R affirms the need to keep R small if large forward gain is to be realized.
Before addressing an engineering shortfall that is endemic to virtually all supplyindependent biasing networks, it is important that we understand the three design requirements
- 462 -
Chapter 5
MOSFET Biasing
that underlie the nominal invariance of currents IQ and Io with respect to perturbations in power
line voltage Vdd. The first of these conditions is that PMOS transistor M4 must function to emulate an ideal current source. The output current, IQ, of this current source establishes the gatesource potential for diode-connected transistor M1. To the extent that this current source boasts
very large terminal resistance, the M1 gate-source potential is essentially independent of the line
voltage, Vdd. Figure (5.38) depicts the pertinent M4-M1 subcircuit we have extracted from the
schematic in Figure (5.37). The subject subcircuit is seen to generate current IQ as a foundation
for establishing the gate-source voltage, Vgs1, observed for transistor M1 and given by (5-87).
Note that the resultant circuit model in Figure (5.38) is similar to the biasing cell we studied in
Section (4.7.3). It also mirrors a subcircuit deployed in the schematic diagram of Figure (5.23).
Because the current source formed of transistor M4 must approximate an ideal branch element if
supply voltage independence is to be nurtured, the channel resistance, ro4, needs to be as large as
possible. Recall that a large channel resistance is associated with a relatively long drawn channel
length and/or small IQ. In turn, small IQ requires small gate aspect ratios for transistors M1 and
M4. Alternatively, the resistance associated with the M4 current source cell can be enhanced
through either passive or active source degeneration in M4. Of course, a topological modification to the M4 subcircuit mandates that appropriate changes be made in the M3 and M5 subcircuits implicit to Figure (5.37).
Vdd
Vdd
x1
Bias
From M3
M4
IQ
IQ
IQ
M1
x1


M1
To Gate
of M2
x1
Vgs1


To Gate
of M2
Vgs1
Figure (5.38). The M1-M4 subcircuit extracted from the self-biasing network in Figure (5.37). Transistor M4 functions as a simple current source.
The second requirement in the design of the self-biasing network is that the current, IQ,
be mirrored as accurately as possible by PMOS transistor M3. High current mirroring accuracy
implies the relative unimportance of CLM, which in turn commands suitably long channel
lengths in both M4 and M3. We show this mirroring as the extracted subcircuit in Figure (5.39).
This figure purports that current IQ is forced to flow through both the M1-M4 and M2-M3
branches of the bias circuit. At this point of our discussion, it is important to remember that by
virtue of (5-87), current IQ and gate-source voltage Vgs1 are inextricably intertwined; that is, the
value of current IQ uniquely fixes the M1 gate-source voltage, Vgs1.
The third design requirement is that the current, IQ, which flows through transistor M3
because of M4-M3 mirroring, be made to flow through the drain of transistor M2. Transistor M2
must have a gate aspect ratio that differs from the gate aspect ratio of transistor M1. The difference between these gate aspect geometries is critical because if M1 and M2 conduct the same
current, IQ, as we underscore in Figure (5.39), the larger transistor, which is M2 in this case,
generates a gate-source voltage, Vgs2, which is smaller than Vgs1. The differential voltage, (Vgs2 −
- 463 -
Chapter 5
MOSFET Biasing
Current
Mirror
Vgs1), consequently appears across the terminals of source degeneration resistance R, which ultimately engenders (5-89). If M1 and M2 were assigned the same gate aspect ratios (meaning k21
= 1), Vgs1 and Vgs2 are necessarily identical to first order, and IQ is remanded to zero. But for k21
> 1, Vgs2 < Vgs2, and current IQ, which is proportional to (Vgs1 − Vgs2), ensures nonzero IQ. In the
first component on the right hand side of (5-89), it is notable that, by the Schichman-Hodges
model, current IQ fixes both of the gate-source voltages, Vgs1 and Vgs2. This circumstance enables
us to conclude that IQ is effectively a function of itself and is therefore independent of line voltage Vdd.
x1
x1
M4
M3
IQ
Vdd
IQ
x k212
M1


x1 V
gs1

M2
Vgs1

R
Figure (5.39). TheM4-M3 current mirror subcircuit extracted from the
self-biasing network in Figure (5.37).
The fact that current IQ in Figure (5.37) can be ominously couched as a function of itself proffers a clue that a problem surrounds the constant current disclosure of (5-91) and hence,
the accompanying response in (5-92). In particular, (5-91) is not the only solution to (5-90),
which can indeed be satisfied trivially for IQ = 0. In other words, it is possible for the network in
Figure (5.37) to register the quiescent current given by (5-91) when supply voltage Vdd is applied
suddenly. But it is also and unfortunately possible that upon boot up, the subject network latches
to its useless null solution nest of IQ = 0. To be sure, such a null solution is programmatically
unlikely because of processing uncertainties that incur at least small parametric differences, and
thus current imbalances, in transistors M3, M4, and M5. But because of the insidious nature of
Murphy’s Law, we must take care to preclude the null startup state.
Viable startup modules, which are topologically similar to those deployed in the BJT
form of this supply-independent biasing network, are available to preclude the foregoing null
current state. Fundamentally, these startup modules force an imbalance among transistors M3,
M4, and M5. Ideally, these startup cells, which generally require at least two additional transistors, consume no power in the steady state.
We should interject that the null current state is not unique to the circuit presently before us. To be sure, most biasing networks that boast supply voltage independence suffer from a
small, but nonzero, probability of a null current latching upon startup.
Figure (5.40) depicts a simple startup module that has been appended to the supplyindependent circuit of Figure (5.37) [3]. The startup cell in question is comprised of capacitor C
and the grounded source transistors, M6 and M7. Note that the gate terminal of M6 is incident
- 464 -
Chapter 5
MOSFET Biasing
with the junction of the drain terminals of M1 and M4, while the drain of M7 is connected to the
junction of the drain and gate terminals of M3. In the steady state, where capacitance C behaves
as an open circuit, no static voltage is delivered to the gate of M7, thereby forcing M7 into cutoff.
In addition, the open circuited nature of C in the steady state precludes any drain current in M6.
Thus, we can appreciate that the highlighted startup cell is effectively disconnected from the
supply-independent configuration when steady state biasing levels are achieved. Although the
startup cell is transparent to strict “DC,” it does load the M4 and M3 drain nodes with parasitic
device capacitances. Fortunately, this loading is rarely an issue because the nodes in question
exhibit low driving point impedances under small signal conditions owing to the diode-connected nature of M1 and M3. Accordingly, these parasitic capacitances forge small time constants that rarely impact circuit response speeds.
Vdd
x1
x1
x kp
M4
M3
M5
M6
M7
IQ
Startup
Module
C
IQ
Io
M2
M1
2
x1
x k21
R
Rl
Figure (5.40). The supply-independent biasing network of Figure (5.32) with a startup
module incorporated to preclude a null current state when the voltage,
Vdd, is applied suddenly to activate the network.
As we did in the BJT version of the circuit before us, we choose to investigate the
functionality of the startup module in a largely qualitative manner. To this end, we assume that
the power supply voltage, Vdd, is applied as a voltage step at time t = 0. If capacitance C is initially uncharged and is much larger than the net device capacitance witnessed at the gate of
transistor M7, almost all of Vdd appears instantly between said gate and circuit ground, thereby
turning on M7. We see then that the drain current of M7 establishes the aforementioned current
imbalance that ostensibly precludes the null current setup.
Let us look at the startup scenario of the circuit at hand. The current flowing in M7 is
necessarily sourced by the drain of transistor M3. This device turns on prior to M4, which awaits
the time required for voltage Vdd to charge the M4 source-gate capacitance to the transistor threshold potential. It follows that because of capacitance C and its inherent inability to change its
terminal voltage instantaneously, transistor M7 forces M3 to begin conducting some of its current
into the drain of M2. Immediately after time t = 0, M4 and M1 remain nominally cutoff. When
current flows through M2, the sum of the gate-source voltage of M2 and the voltage drop across
- 465 -
Chapter 5
MOSFET Biasing
resistance R begins to rise to the threshold potential of M1, thereby supporting the initiation of
current in the drains of M1 and M4. As the gate-source voltage of diode-connected transistor M1
continues to increase, so does the gate-source voltage of M6, which throughout this interlude remains cutoff. But as the gate-source voltage of M6 rises beyond threshold level, M6 conducts
current, which charges capacitance C toward Vdd, thereby lowering the voltage at the gate of M7.
When C charges to a level larger than (Vdd − Vh7), where Vh7 is the M7 threshold voltage, M7
switches off, which is tantamount to the initiation of steady state circuit operation. Since zero
current response has been precluded by the current imbalance induced by the startup cell at the
instant of voltage application, this steady state condition supports the establishment of (5-91) as
the only observable solution for current IQ.
5.5.2. BANDGAP REFERENCE NETWORK
In addition to affording low voltage, low power, and supply-independent operation,
voltage references for high performance analog integrated circuits, and especially circuits earmarked for high-speed data acquisition and information processing, must project superior
temperature insensitivity. The temperature sensitivity problem can be especially pronounced in
deep submicron technologies for which even modest current levels correspond to high current
densities that routinely produce intrinsic temperatures rising to as much as 75 °C or higher.
The arguably finest engineering solution to the temperature dilemma problem is the
bandgap reference circuit. This circuit, which also boasts static performance that is nominally
insensitive to power line voltage variations produces an almost temperature invariant reference
voltage. This temperature insensitivity is achieved by exploiting the inherently negative
temperature coefficient we witnessed in Chapter #2 for the junction potential developed across a
forward biased PN junction diode. Specifically, the bandgap reference produces an output response that is proportional to the sum of the aforementioned junction forward bias and the output
voltage of a PTAT generator, whose voltage output is directly proportional to absolute temperature. Accordingly, a theoretic cancellation of temperature effects is made possible
The bandgap reference cell is explored thoroughly in Section (3.5.2) and therefore, its
analysis is not repeated here.
5.6.0. HIGH PERFORMANCE BIASING
Before concluding our expository on MOSFET biasing networks, we should address a
few special purpose, but nonetheless commonly exploited, biasing cells that offer exceptionally
high performance. “High performance” is a generic descriptive whose meaningful definition is
often tied to the application of interest. In the present case of biasing, we associate performance
quality with two fundamental engineering requirements. First, we demand that the output currents or voltages of a biasing network be predictable and reproducible. Foremost among the
engineering implications of predictable and reproducible static responses is biasing invulnerability to supply voltage variations incurred by temperature changes, poor line regulation, spurious
signals, or other environmental phenomena. Yet another implication is a biasing response that is
not overtly sensitive to vagarious transistor model parameters and poorly controlled values of
circuit branch elements. Second, we wish to have a biasing network emulate the performance of
an idealized circuit structure. In the case of voltage sources, this means that Thévenin output
resistances must be very small. In contrast, current sources naturally exude very high Thévenin
output resistances.
- 466 -
Chapter 5
MOSFET Biasing
5.6.1. REGULATED CASCODE CURRENT SINK
The network depicted in Figure (5.41) is referred to as a regulated cascode current sink.
It exploits active feedback to achieve a very large output impedance, Rout. The active feedback
to which we refer derives from the indicated connection of a voltage amplifier8 whose gain, Av, is
taken as the ratio of the amplifier output voltage, Va, to the applied differential input voltage, Vd.
In particular,
Vkk
+Vdd
Ik
Iin
Rout
M1
Vbias
Va
 Vd  Av


xk
23
M3
M2
x1
x k23
V2
Figure (5.41). Schematic diagram of a regulated cascode current sink. The amplifier, voltage gain is Vo /Vd = Av. It also delivers infinitely large
input impedance at both its non-inverting and inverting input ports.
A 
v
V
a ,
V
d
for which
V  V
d
bias
(5-95)
V .
(5-96)
2
In (5-96), V2 symbolizes the drain-source voltage imposed on transistor M2. On the assumption
that the feedback amplifier offers very high impedances seen looking into both its non-inverting
and inverting input ports, the output current, Ik, is determined largely by the applied input current, Iin. Specifically, the current mirror nature of transistors M3 and M2 deliver
I  k I ,
(5-97)
k
23 in
where k23 is the ratio of the gate aspect ratio of transistor M2 to the gate aspect ratio of transistor
M3. Equation (5-97) assumes that the effects of CLM in M2 and M3 are mitigated by maintaining comparably equal drain-source voltages between these two transistors and/or by using
transistors that feature reasonably long channel lengths. Thus, the utilized amplifier has little
impact on the particular value of output current Ik. But, as we are about to demonstrate, it does
boost the output resistance, and unselfishly offers other performance advantages. The most notable of these additional advantages is that it effectively “regulates” drain-source voltage V2 by
keeping it nearly constant, independent of perturbations in the applied voltage Vkk.
Figure (5.42) displays the small signal equivalent circuit pertinent to determining the
output resistance, Rout, of the regulated cascode. In this structure, we have tacitly ignored bulk8
As we shall see in the subsequent chapter, an especially simple form of this feedback amplifier requires but a
single MOSFET and a single resistance.
- 467 -
Chapter 5
MOSFET Biasing
induced threshold modulation in transistor M1. Moreover, we assume that Vbias is a constant voltage that is divorced of any signal component. Accordingly, the signal voltage, say Vas, developed with respect to ground at the gate of transistor M1 is −AvV2s, where we have invoked (5-95)
and (5-96). Moreover, we have represented the signal component of the M2 drain-source voltage
as V2s. The small signal equivalent circuit of M2 embodies only the drain-source channel resistance, ro2, across which signal voltage V2s is developed. This situation reflects the presumption
that input current Iin is constant and derives from an ideal current source possessed of infinitely
large terminal resistance. It follows that no signal voltage can be developed across the gatesource terminals of either M3 or M2, whence no signal current proportional to the M3 gatesource voltage can evolve in the model for transistor M2. The model at hand makes clear the
fact that the gate-source signal voltage applied to transistor M1 is
Rout
Ixgm1V1
ro1
gm1V1
Vas
 V1 

Vx

AvV2s

Ix

ro2
V2s


Ix
Figure (5.42). Low frequency, small signal equivalent circuit of the regulated
cascode current sink shown in Figure (5.44). The circuit is
used to evaluate the output resistance, Rout, as the ratio, Vx/Ix, of
mathematical ohmmeter variables.
V  V
V
V  r
 I x  gm1V1   ro2 I x .
1
as
while
x
o1
2s
 AV
v 2s

V

  1 A r I ,
2s
(5-98)
v o2 x
(5-99)
After we substitute (5-98) into (5-99), we arrive at the output resistance result,
V
 x  1  1  A g
R
r r  r r
.
out
v
m1
o1 o2  o1 o2


I

x




(5-100)
The last result encourages two observations. First, the output resistance of the regulated cascode
is a markedly enhanced version of the series combination of the channel resistances offered by
transistors M1 and M2. We note that this resistance enhancement is embellished by the feedback
amplifier, whose positive voltage gain is Av. Second, in the likely case that gm1(1+Av)(ro1||ro2)
>> 1,
R
 1  g
r r
1 A  r  r
 1 A g r r ,
(5-101)
out
m1 o1 o2
v  o1
o2
v m1 o1 o2

which projects the fact that Rout is large because the reasonably large gain metric, gm1ro1, multiplies a large channel resistance (ro2), which is itself multiplied by (1 + Av).



 

An illuminating sidebar of the regulated cascode network is the nature of the signal vol- 468 -
Chapter 5
MOSFET Biasing
tage, V2s, developed across the drain-source terminals of transistor M2 in Figure (5.41). From
Figure (5.45), (5-100), and (5-101), we have
V
V
x 
x
(5-102)
V  r I  r
,
2s
o2 x
o2 R
g
r
1

A
out
m1 o1

v

which portends a very small signal voltage because of a presumably large M1 channel resistance,
a realistic forward transconductance (gm1) for transistor M1, and the amplifier gain (Av). Three
interesting aspects to this miniscule small signal voltage unfold. First, if V2s is indeed very
small, the signal component, Ix, of the M2 drain current that arises from our mathematical
ohmmeter is necessarily very small, thereby portending a high output resistance, as we have confirmed with (5-101). We are therefore moved to say that the feedback amplifier, whose voltage
gain serves to reduce signal voltage V2s, encourages the high output resistance, Rout, we deduced
for the regulated cascode. The second noteworthy point is that our mathematical ohmmeter voltage, Vx, can be interpreted as a perturbation, Vkk, in applied voltage Vkk. Moreover, our
mathematical ohmmeter current can be viewed as a signal-induced change, say Ik, in the drain
current, Ik, which transistors M1 and M2 conduct. We can therefore conclude, with the aid of (515), that the high output resistance supported by the feedback amplifier ensures a low sensitivity
of output (drain) current to voltage Vkk in that
V
Vkk
Vkk
x 
(5-103)
I k  I x 

.
R
R
g
1

A
r
out
out
m1

v
 o1
The third point to be made surrounds the nature of the net voltage, V2, which is developed from the drain to the source on transistor M2, in light of the conclusion that the signal
component, V2s, of this voltage is very small. Figure (5.44) renders clear the fact that
V  V
V .
(5-104)
2
bias
d
Since Vbias eschews any signal component and V2 boasts almost zero signal component, differential voltage Vd necessarily follows as a voltage displaying virtually no signal component. From
(5-96),
V
V  V
 a ,
V  V
(5-105)
2
bias
d
bias A
v
which suggests that if voltage gain Av is large (an often challenging design requirement, to be
sure), the drain-source voltage, V2, of transistor M2 is held nominally constant at the bias level,
Vbias. Stated in another way, a high gain amplifier forces the differential input voltage of the amplifier in question toward zero. Since holding a circuit voltage constant is akin to classic voltage
regulation, we now understand why the amplifier in the regulated cascode is said to “regulate”
voltage V2. Even if Av is not very large, the amplifier output voltage, Va, which excites the gate
of transistor M1 is virtually divorced of signal voltage because of small V2s. In this case, we say
that voltage V2 is regulated to a value that is less than Vbias by an amount that equals the quiescent value of voltage Va divided by gain Av.
5.6.2. ENHANCED OUTPUT IMPEDANCE CURRENT SINK
A modified version of the regulated cascode current −one that is particularly suited for
circuits using deep submicron MOS technology devices− sink appears in Figure (5.43)[4].
Submicron transistors invariably require low voltage biasing to preclude excessive electric fields
in the device channels and impedance enhancement methods that compensate for relatively small
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Chapter 5
MOSFET Biasing
drain-source channel resistances. The network boasts low voltage operating capabilities because
of the low voltage reference cell comprised of transistors M3 and M4 and the applied bias voltage, Vbias. As we describe in Section (5.4.2), Vbias places transistor M3 on the cusp of operating
in its saturation domain, while M4 operates in (or very near) saturation with a drain-source voltage that is nominally its threshold potential. Current Ibias and designable parameter p2 are selected to satisfy power dissipation limits. Along with applied voltage Vkk, Ibias and p2 ensure that
all other transistors operate in saturation. Ordinarily, p is a number that is greater than one.
Vdd
Vkk
I
k
Rout
Iin
Ibias
p2Ibias
M1
Vbias
M4
M6
M7
xk
x1
x1
xk
M3
M5
M2
xk
x1
xk
Figure (5.43). Schematic diagram of the enhanced output resistance current sink. The network
is the regulated cascode sink in Figure (5.41), modified for deployment in networks that exploit deep submicron technology MOSFETs.
5.6.2.1. Static Investigation
Under static, or quiescent (zero input signal), circumstances, the circuit in Figure (5.43)
yields
I I
k
bias
 I
d2
I
d5
,
(5-106)
where Id2 and Id5 are the quiescent drain currents conducted by transistors M2 and M5, respectively. Since the gate-source voltages of M2 and M5 are identical and M2 has a gate aspect ratio
that is a factor of k larger than the gate aspect ratio of transistor M5, Id2 = kId5. Moreover, Id5 =
Id3/k owing to the current mirroring nature of the M3-M5 connection. We also note that the static
drain current, Id3, of transistor M3 is the input current, Iin. Thus, the output current, Ik, of the subject current sink is, using the preceding equation
1

I  I I I
 1   I  I
.
(5-107)
k
d2
d5
bias
bias
k  in

If Ibias is selected so that Ibias = Iin /k, output current Ik mirrors Iin with unity scale factor; that is, Ik
= Iin. But if Ibias = Iin /k = Id5, (5-107) shows that current Ik does not divide between transistors
M2 and M5. Instead, current Ik flows solely into the drain of transistor M2. If Ibias flows into M5
and Ik flows into M2, no current is conducted by the metallization that connects the drain of
transistor M2 to the drain terminal of M5. If we indeed wish current Ik to be identical to input
current Iin, we are well advised to adopt the computer-aided design tack of carefully adjusting
current Ibias until null current flow is observed at the aforementioned branch interconnect between the drain terminals of transistors M2 and M5. In this manner, we pragmatically adjust the
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Chapter 5
MOSFET Biasing
nominal setting of Ibias = Iin /k to account for subtle device performance differences incurred by
CLM, BITM, and other high order modeling phenomena that we ignore, or at least de-emphasize
peremptorily.
The network in Figure (5.43) also projects
p2I
bias
 
n7
V
gs7
V
hn

2
,
(5-108)
where we are using, in general, βni and Vgsi to represent the transconductance coefficient and
static gate-source voltage, respectively, of the ith MOSFET. Moreover and as has become our
normal analytical strategy, we adopt the simple long channel approximation that ignores CLM,
body effect (which invokes identical threshold voltages for all transistors in the schematic diagram at hand), DIBL, and all other second order phenomena. Since transistors M6 and M7 are
identical, inclusive of gate aspect ratios, βn6 = βn7. We also see that
I
bias
 
n7

V
gs6
V
hn

2
The foregoing two equations deliver
V
 pV
  p  1 V
gs7
gs6
.
hn
(5-109)
(5-110)
.
In view of the facts that βn5 = βn7 the gate aspect ratio of M3 is k-times that of M5, and
current Iin flows in the drain of transistor M3,
2
I
in  
V
(5-111)
V
,
n7 gs5
hn
k
which is to say that the drain saturation voltage, Vdsat5, of transistor M5 is
I
in .
 V
V 
(5-112)
V
dsat5
gs5
hn
k


n7
If we choose to set the drain-source voltage of M5, and thus of M2, to Vdsat5, Figure (5.43), (5109), (5-110), and (5-112) combine to deliver
I
I
in   V

V
  p  1 V
V
  p  1 bias . (5-113)
V
dsat5
gs6
gs7
gs6
hn

k

n7
In short, transistor M5 is biased at its saturation domain cusp if
I
in   p  1 2 I

 bias .
k

n7
(5-114)
We can advance two important points in conjunction with the last result. The first of
these is that by holding the drain saturation voltage of M5, and thus M2, to Vdsat5, the voltage
drop from the source of transistor M1 to ground is held to a minimum. Of course, minimal voltage developed from the source of M1 to ground complements the intent to set the drain-source
voltage of transistor M5 at its drain saturation value. This means that the applied voltage, Vkk,
need only supply the net voltage, (Vdsat5 + Vdsat1), where Vdsat1 represents the drain saturation voltage of M1. In other words, Vkk need only be a relatively small voltage (of the order of twice
drain saturation value) for the current sink to operate properly. And, of course, small Vkk conflates admirably with the design constraints implicit to deep submicron technology. The second
point to be made recalls (5-107), which confirms that Ibias = Iin /k makes current Ibias flow through
the drain of M5, while output current Ik flows in the drain of M2. In other words, no current
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Chapter 5
MOSFET Biasing
flows through the M2-M5 drain interconnect. From (5-114), Ibias = Iin /k, implies that parameter
p must ideally be two; that is p = 2. We are therefore afforded the luxury of a nominal setting
for parameter p, which we can adjust carefully to set the drain-source voltage of M5 to its drain
saturation level, despite uncertainties in key transistor model parameters. It is interesting that
while Ibias effectively controls the current conducted by the M2-M5 drain metallization, p sets the
drain-source voltage of M5 and therefore, the drain-source voltage of M2. In a word, the circuit
designer is gifted the luxury of tweaking two nominally independent circuit variables to achieve
proper operation of the current sink in Figure (5.43).
5.6.2.2. Small Signal Investigation
The small signal model for quantifying the low frequency output resistance, Rout, of the
enhanced output impedance current sink appears in Figure (5.44). In arriving at this model, we
have neglected BITM in all transistors, and in transistor M6, we have ignored the drain-source
channel resistance, ro6. The latter approximation is appropriate in that ro6 shunts resistance 1/gm6
in the small signal model of M6. This shunt resistance combination collapses to 1/gm6 in that we
expect gm6ro6 >> 1. All three current sources, Iin, Ibias, and p2Ibias, are presumed ideal sources of
constant current. In addition to projecting infinitely large resistances across their respective
terminals, these current sources offer no signal components. Analogously, voltage Vbias is taken
as a source of constant voltage, which is to say that it too produces no signal component. Since
Iin and Vbias contain no signal, no gate-source signal voltages can be developed on transistors M2
and M5. In light of the drain connection of these two transistors, this means that M2 and M5
combine to forge a net resistance, (ro2||ro5), from the source terminal of transistor M1 to ground.
While zero static current is conducted by the M2-M5 drain interconnect, we note with interest
that this same metallization establishes signal feedback from the source terminal of M1 to the
gate-source terminals of M6 and thus, to the gate of transistor M7. The basic function of this
feedback is similar to the feedback offered by the amplifier in the regulated cascode sink of Figure (5.41). Of course, the output resistance follows as the ratio, Vx /Ix, of our mathematical
ohmmeter variables, Vx and Ix.
Rout
Vx
gm1Va
Vb
 Va 
1/gm6
gm7Vb
ro1
Ix
Ixgm1Va
ro7
ro2||ro5
gm7Vb
Ix
0
Figure (5.44). Low frequency, small signal equivalent circuit for calculating the output resistance, Rout, of the current sink in Figure (5.43).
In Figure (5.47), a conventional circuit analysis produces
V 
b
 ro2 ro5  I x ,
(5-115)
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Chapter 5
MOSFET Biasing
V  g
a
and
V  r
x
o1
 o2 ro5  I x ,
r V  r
m7 o7 b
(5-116)
 I x  gm1Va    ro2 ro5  I x .
(5-117)
Upon inserting (5-115) into (5-116) and then putting the resultant form of (5-116) into (5-117),
we obtain
V
R
 x  r  1  g r
1 g r  r r
,
(5-118)
out
o1 
m1 o1
m7 o7  o2 o5
I

x



which clearly implies a very large output resistance. For large values of (gm1ro1) and (gm7ro7), the
output resistance in (5-118) reduces to
R
 r  1  g r
1 g r  r r
out
o1 
m1 o1
m7 o7  o2 o5
(5-119)
 g r
g r
r r
.


m1 o1


m7 o7
  o2
o5



In principle, this resistance can be enormous (of the order of several hundreds of MEGΩ.
5.6.3. LOW VOLTAGE, HIGH RESISTANCE CURRENT SINK
A popular variation of the regulated cascode circuit is the configuration submitted in
Figure (5.45)[5]. The two notable features of this current sink are the low voltage biasing module
formed of transistors M4 and M6 and the regulated cascode output stage contrived of transistors
M1 through M3. The regulated cascode cell enables the realization of a very large output resistance, Rout. Along with its active degeneration via transistor M3, it also facilitates a controllable
and predictable output current, Ik. The combination of these performance traits encourages the
deployment of the subject current sink in such high performance applications as data and
information processors, communication systems, and data converters. Moreover, the low voltage
cell, which we studied in Section (5.4.2), allows the realization of high Rout and both predictable
and reliable Ik at low voltage and low power levels. These formidable attributes explain the
popularity of the biasing network in a myriad of portable electronic systems.
+Vdd
Vkk
Iin
IQ1
IQ2
VQ1
M4
x1
M6
Ik
VQ2
M5
M2
x1
x1
Vref
Rout
M1
xk
M3
xk
x1
Figure (5.45). Low voltage, regulated cascode, current sink featuring the
low voltage biasing cell examined in Section (5.4.2) and
active source degeneration via transistor M3.
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Chapter 5
MOSFET Biasing
We shall execute both a static analysis and a small signal analysis of the low voltage,
high impedance current sink. These analyses, and especially their static constituent, are somewhat intricate, and their proper engineering interpretation is a challenge. But it is precisely these
intricacies and challenges that motivate us to undertake the analytical effort, for its proper execution serves to test our comprehension of fundamental MOSFET biasing concepts.
5.6.3.1. Static Analysis
For our first order manual analyses, we shall continue to subscribe to our traditional
assumptions of negligible CLM, BITM, carrier mobility degradation, and other high order physical modeling phenomena. The fruits of the resultant simplified analysis lay a sturdy foundation
upon which we can ultimately rest our definitive computer-aided optimization of the network.
Noting that transistors M4 and M6 share the same gate aspect ratio, (5-78) gives for the
output voltage, Vref, of the low voltage biasing subcircuit,
V V
Q1
hn
V

,
(5-120)
ref
2
where, of course, Vhn is the threshold voltage of all NMOS transistors. Voltage Vref is applied
across the gate-source terminals of transistor M6. It is also the voltage established at the drain
node of transistor M4 with respect to circuit ground. Since the static input current, Iin, which
may derive from an off chip current source, flows through the drain of transistor M4, Vref also
appears across the gate-source terminals of M4. In addition, Vref couples directly to the gatesource terminals of transistor M3, whose gate aspect ratio is k-times larger than that of transistor
M6. In view of the facts that transistor M1 conducts the current flowing through M3 and has a
gate aspect ratio that is identical to that of M3, voltage Vref appears across the gate-source terminals of transistor M1. At this juncture, we therefore see that Vref is the voltage that appears across
the gate-source terminals of M6, M4, M3, and M1. Additionally, Vref is the voltage developed
with respect to ground at the drain node of transistor M4.
Using our simple MOSFET model, we have
I
in
 
n6

V
ref
V
hn

2
,
(5-121)
and because M6 and M3 comprise a current mirror,
I
k
 
n3

V
ref
V
hn

2
 k
n6

V
ref
V
hn

2
 kI
in
.
(5-122)
In the last equation, we have made use of the design stipulation that the gate aspect ratio of
transistor M3 (and of M1) is k-times that of transistor M6. We therefore see that to the extent that
care is exercised to assure the validity of our simplifying modeling approximations, the
predictability of current Ik rests on our ability to realize input current Iin predictably.
As we have already documented, Vgs4 = Vref. The drain-source voltage, Vds6, of transistor M6, which is identical to the gate-source voltage, Vgs5, of transistor M5, is
V
 V
 V V
 V V
.
(5-123)
ds6
gs5
Q1
gs4
Q1
ref
But if we use (5-120) to eliminate voltage variable VQ1 in (5-123), we find that
V
 V
 V V
 V V .
ds6
gs5
Q1
ref
ref
- 474 -
hn
(5-124)
Chapter 5
MOSFET Biasing
No less than four interesting points surface from the last expression. The first of these is that the
drain-source bias on M6, and hence, the gate-source bias applied to M5, is controlled exclusively
by input current Iin. Specifically and appealing to (5-121),
I
in .
(5-125)
V
 V
 V V
 V V

ds6
gs5
Q1
ref
ref
hn
 n6
The second point is that because the gate-source bias of transistor M6 is Vref, the drain-source
voltage of M6 is exactly its idealized drain saturation voltage, (Vref − Vhn), which is indeed the
drain saturation voltage for low, drain to source electric fields. Thus, we are assured that transistor M6 is saturated. Third, if transistor M4 is to operate in its saturation regime, it requires a
drain-source voltage, Vds4, of
V
ds4
 V
ref
or equivalently,
V
 2V
ref
hn
V
ds6

 V
 V
ref
ref
V
hn
V
 V
hn
ref
V
hn
(5-126)
,
(5-127)
.
In addition to constraining Vref to a relatively small voltage, the subject inequality reassuringly
mirrors our generalized reference voltage constraint in (5-78). Fourth and finally, we can easily
confirm the saturation regime operation of transistor M5. In particular, its drain source voltage,
Vds5, is VQ1 and by (5-120),
V
 V
 2V
V .
(5-128)
ds5
Q1
ref
hn
On the other hand, recall from (5-125) that the gate-source voltage of M5 is
V
 V
V .
gs5
ref
(5-129)
hn
It follows that M5 is saturated if (2Vref − Vhn) ≥ (Vref − Vhn) − Vhn, which is equivalent to the obviously satisfied constraint, Vref ≥ −Vhn.
Current IQ1 flows through the drain of transistor M5, while current IQ2 is conducted by
transistor M6. Recalling (5-129),
I
Q1
 
n5
Vref  2Vhn 
2
 
n6
Vref  2Vhn 
2
 V  2V 
ref
hn 
 I 
in  V
V 
hn 
 ref
2
2
(5-130)


V
hn

 ,
 I 1
in 
V V 
ref
hn 

which asserts that IQ1 is necessarily slightly smaller than input current Iin. If set IQ2 = IQ1, we
resultantly expect the gate-source voltage, Vgs2, of transistor M2 to be the same as the voltage,
Vgs5, which is stipulated by (5-129). More pragmatically, we expect that the current, IQ2, which
gives rise to Vgs2 = Vgs5 = (Vref − Vhn), to differ slightly from current IQ1, owing to the presumptions to which we have adhered in the course of this static analysis. Regardless of the value of
current IQ2 that renders Vgs2 = Vgs5, we can assert VQ2 = VQ1 = (2Vref − Vhn), in accord with (5120). For this operating environment, the voltage developed with respect to ground at the gate
terminal of transistor M2 is forced to mirror the voltage we observe at the gate of transistor M5.
Accordingly, M2 and M3 are saturated for the same reasons that ensure the saturation domain
operation of transistors M5 and M6, respectively.
We complete the delineation of the static design conditions for the circuit before us by
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Chapter 5
MOSFET Biasing
ascertaining the minimum value to which node voltage Vkk must subscribe if transistor M1 is to
be confined to its saturation regime. To this end, we note that the drain-source voltage, Vds1, to
which transistor M1 is subjected is
 V
V
ds1
kk
V
gs2
 V
kk
V
 V
gs5
kk

 V
ref
V
hn
.
(5-131)
Since the gate-source voltage, Vgs1, of M1 is Vgs1 = VQ2 − (Vref −Vhn), the saturation of M1 commands
V
kk

 V
ref
V
hn
V
Q2

 V
ref
V
hn
   2V
ref
V
hn
  V
ref
V
hn
 , (5-132)
where we have invoked our earlier conclusion that VQ2 = VQ1 = (2Vref − Vhn). The inequality in
(5-132) collapses to the design condition,
V  2V
V .
(5-133)
kk
ref
hn
In a word, voltage Vkk can be no smaller than one threshold potential below twice the reference
potential developed at the gate of transistor M6.
 2Vref  Vhn
+Vdd
IQ2
Vref
M4
Vref  Vhn
x1
VQ1
M5
x1
2Vref  Vhn
IQ1
2Vref  Vhn
Iin
Ik
VQ2
M2
M1
xk
Vkk
Rout
Vref Vhn
x1
Vref
M3
xk
M6
x1
Figure (5.46). Low voltage, regulated cascode current sink with requisite node voltages defined as functions of reference voltage Vref and NMOS threshold potential Vhn.
The myriad of voltages we need to quantify so that we can ensure the desired saturation
regime operation of all NMOS transistors in the current sink of Figure (5.45) can understandably
foster confusion and even engineering uncertainty. In an attempt to dispel these problems, we
provide in Figure (5.46) the schematic diagram with all node voltages defined in terms of reference and threshold potentials. This type of a diagram, but with actual numerical voltages inserted, as opposed to the indicated generalities, is a recommended prerequisite to running simulations in that it serves as a convenient reference for ascertaining whether the circuit is functioning
properly under static operating conditions. In the diagram, we show Iin as an adjustable source of
current that can be varied to mitigate parametric uncertainties while attempting to achieve the
target reference potential, Vref. Similarly, we allow for a tunable current IQ2 so that we can set, as
accurately as possible, the static node voltage at the gate of transistor M2. Ideally, IQ2 = IQ1 but
in the real world of device mismatches and parametric uncertainties, we can proffer as much as a
10% to 15% difference between these currents.
Before proceeding, it is worth interjecting that on the assumption that voltage Vref is
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Chapter 5
MOSFET Biasing
desirably temperature invariant, the parametric ratio, Iin/βn, should project an appropriately negative temperature coefficient. We arrive at this contention because (5-125) shows that voltage Vref
is a linear superposition of threshold potential Vhn and the square root of the ratio, Iin/βn. We
know, by virtue of the studies we undertook in Section (4.5.5), that threshold voltage Vhn displays a positive temperature coefficient. Accordingly, the square root of Iin/βn must offset this
positive temperature coefficient if there is any hope of maintaining Vref nominally independent of
temperature. Observe that this requirement is helped along by transconductance metric βn, which
is proportional to carrier mobility and therefore exudes a negative temperature coefficient.
5.6.3.2. Small Signal Analysis
As we argued earlier, a measure of quality for a current sink or source is the Thévenin
resistance it presents at the network port to which the current sink or source connects. In the
present case, our current sink connects to a network node that supports a sufficiently large voltage, Vkk. Recall that at this node, a large Thévenin output resistance, Rout, is desired to minimize
the sensitivity of current Ik to perturbations in voltage Vkk.
We shall determine resistance Rout in the circuit schematic diagram of Figure (5.45) by
applying our mathematical ohmmeter strategy to an appropriate small signal model of the current
sink. Before displaying this model, it is wise to discuss its topological composition. The model
in question need only embrace transistors M1 through M3 since grounding the source terminal of
transistor M5 precludes the subcircuit comprised of transistors M4 through M6 from interacting
dynamically with the M1 through M3 subcircuit. To be sure, the gate of transistor M6 is incident
with the gate of M3. But (5-81) reminds us that the resistance seen looking back from the gate of
M3 is small and approximately equal to 1/gm6. Moreover, if Iin emulates an ideal source of constant current, no signal impinges on the M3 gate since current source Iin isolates said gate from
any perturbations witnessed in the power line voltage, Vdd. With no signal applied to the M3
gate, and given that both the bulk and source terminals of M3 are grounded, the small signal
model for transistor M3 is simply a channel resistance, ro3, connected between its drain terminal
and circuit ground. We shall also presume that current sources IQ1 and IQ2 are ideal.
Continuing with the model development, transistor M2, like transistor M3, has no bulksource voltage and therefore, there is no bulk transconductance generator in its drain-source circuit. Of the three transistors of present interest, only M1 displays both small signal CLM and
BITM effects. The resultant small signal model is the topology appearing in Figure (5.47). In
this model, we have used (4-173) to represent the small signal effects of BITM in transistor M1.

gm1Va
b1gm1Vb

gm2Vc
Ix

 Va 
ro2
ro1 Vx
Rout
Vc

ro3
Ix
Ix
 gm1Va
b1gm1Vb

Vb

Figure (5.47). Small signal equivalent circuit for determining the Thévenin output resistance,
Rout, of the current sink shown in Figures (5.45) and (5.46).
In Figure (5.47), we see that that the controlling voltages, Vc, Vb, and Va are given by
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Chapter 5
MOSFET Biasing
V
 V
V
 g
c
b
 r I
o3 x
(5-134)
,
and
a
In addition,
V
x
 r
o1

r V V   1 g
m2 o2 c
c
r
r
I
m2 o2 o3 x
.
 I x  g m1Va  b1g m1Vb   ro3I x .
Upon substituting (5-134) and (5-135) into (5-136), we arrive at the conclusion,
V
R
 x  r  1  1    g r g r  r .
out
o1 
b1
m2 o2 m1 o1  o3
I

x

(5-135)
(5-136)
(5-137)
In view of the fact that products of transistor transconductances and channel resistances tend to
be large, we can approximate this result as
V
R
 x  g r g r r .
(5-138)
out
m1 o1 m2 o2 o3
I
x


Since the general product, gmro, is usually of the order of at least ten, (5-138) enables our
expectation of an output resistance, Rout, which is in the neighborhood of two orders of a magnitude larger than the drain-source channel resistance of a single transistor. The latter resistance
(channel resistance) is generally at least several thousand ohms in prudently biased, deep submicron MOSFETs.
5.7.0. REFERENCES
[1]. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
1997, pp. 135-146.
[2]. G. R. Wilson, “A Monolithic Junction FET n-p-n Operational Amplifier, IEEE J. of Solid-State
Circuits, vol. SC-3, pp. 341-348, 1968.
[3]. Q. A. Khan, S. J. Wadhwa, and K. Misri, “Low Power Startup Circuits for Voltage and Current
Reference With Zero Steady State Current,” Proc. 2003 ISLPED Conf., pp. 184-188, Aug. 2527, 2003.
[4]. U. Gatti, F. Maloberti, and G. Torelli, “A Novel CMOS Linear Transconductance Cell for
Continuous Time Filters,” Proc. of the IEEE Int. Symp. on Circuits and Systems, pp. 11731176, May 1990.
[5]. E. Säckinger and W. Guggenbühl, “A High-Swing, High-Impedance MOS Cascode Circuit,”
IEEE J. of Solid-State Circuits, vol. 25, pp. 289-298, Feb. 1990.
EXERCISES
PROBLEM #5.1
The divider circuit in Figure (5.1a) is modified to the configuration depicted in Figure (P5.1) in
which the bulk terminal of transistor M2 is grounded, as opposed to being returned to the source terminal of the device. Consequently, the observed threshold voltage, Vh2 of M2 differs from the threshold voltage, Vh1, which is indigenous to transistor M1.
(a). If W1/L1 = k122(W2/L2), derive an expression for output voltage Vref as a function of the supply
voltage, Vdd, and the threshold voltages, Vh1 and Vh2.
- 478 -
Chapter 5
MOSFET Biasing
(b). Use the relevant parameters in Table (4.1) to deduce the threshold voltage difference, (Vh1 −
Vh2), at room temperature, where the intrinsic carrier concentration can be taken as ni = 1010
atoms/cm3. Assume a reference output voltage, Vref, of 1.25 volts.
Id
Vdd
M2
Vref
M1
Figure (P5.1)
PROBLEM #5.2
Design the circuit in Figure (P5.1) to deliver Vref = 1.50 volts when Vdd = 3 volts. The static power
dissipated by the circuit is to be no more than 2 mW. Use the HSPICE parameters in Table (4.1) to
submit a simulation that displays how voltage Vref varies with supply voltage Vdd to confirm the propriety of the design.
PROBLEM #5.3
Use the HSPICE parameters in Table (4.1) to submit a simulation of the circuit designed in the
preceding exercise. The simulation must display how voltage Vref varies with operating temperature
when Vdd = 3 V. Consider temperatures of 0 °C, 27 °C, 50 °C, 75 °C, 100 °C, and 125 °C.
PROBLEM #5.4
In the network of Figure (P5.4), which is a slightly modified form of the NMOS current mirror
shown in Figure (5.3a), the steady state values of Vdd and Vkk are Vdd = 3.5 volts and Vkk = 1.75 volts.
Corresponding to these voltages, the steady state values of Iref and Ik are Iref = 100 μA and Ik = 1.0
mA. For the HSPICE or alternative SPICE simulations requested below, use the NMOS parameters
itemized in Table (4.1) to model the transistors. In these simulations, set the drawn channel lengths
of transistors M1 and M2 to L = 1.5 μM, and pick the gate widths of the two transistors to assure
proper operation of the mirror in the steady state. The resistance, Rr, associated with current source
Iref is Rr = 55 KΩ, while capacitance Cr is 30 fF. Once you have chosen the gate widths of both
transistors, make sure that you appropriately set the area and periphery parameters, As, Ad, Ps, and Pd
so that a proper account is made of high frequency effects in the transistors.
Vdd
Vkk
Iref
Rr
Cr
Id1

Ik
M2
Zout
x k21
Vref M1

Figure (P5.4)
(a). Simulate a static sweep of the current, Ik, versus voltage Vdd, for 0 ≤ Vdd ≤ 5 volts.
i. Over what range of Vdd is current Ik held fast to within ±10%?
ii. How does this output current sensitivity to Vdd compare with the pertinent disclosures in
Example #5.2?
(b). Simulate the small signal frequency response of the magnitude of the driving point output
- 479 -
Chapter 5
MOSFET Biasing
impedance, Zout, making sure to maintain the quiescent operating point in the course of executing this simulation.
i. What is the significance of the low frequency value of Zout?
ii. Does capacitance Cr dominantly affect the magnitude response of Zout, especially at signal
frequencies for which the magnitude of the output impedance degrades from its low frequency value by a factor of the square root of two?
(c). Repeat both parts of Part (a), but now, execute a static output current sweep with respect to voltage Vkk for 0 ≤ Vkk ≤ 3 volts. How does the static output current sensitivity to Vkk relate to the
low frequency output impedance?
(d). Simulate the frequency responses of the real and imaginary components of the driving point
output admittance, Yout = 1/Zout.
i. What engineering significance can be attached to the low frequency value of the inverse of
the real part of impedance Zout?
ii. Plot the simulated output capacitance as a function of signal frequency.
iii. What engineering significance can be attached to the low frequency value of the output
capacitance?
PROBLEM #5.5
In an attempt to highlight MOSFET temperature issues, consider a p-channel MOSFET having a donor impurity concentration in the substrate of Nsub = 1014 atoms/cm3. At a reference temperature of
To = 27 °C, the PMOS transistor, which is biased for a drain current of Id = 500 μA, delivers βp =
850 μmhos/volt, and a threshold voltage of Vhp = 650 mV. Assume a reference temperature intrinsic
carrier concentration of 1010 atoms/cm3. Determine the requisite source-gate voltage, Vsg, such that
the room temperature, 500 μA of drain current, is sustained at an elevated operating temperature of
100 °C.
PROBLEM #5.6
Derive expressions for the Thévenin resistances, Rt1, and Rt3, introduced in the small signal, cascode
mirror models shown in Figure (5.11). The cascode mirror itself appears in Figure (5.10). In the
course of deriving these relationships, neglect neither CLM nor BITM. However, finalize your
resistance conclusions by invoking justifiable approximations with respect to the transistor model
parameters.
PROBLEM #5.7
In the network of Figure (P5.7), which is a slightly modified form of the cascode current mirror
shown in Figure (5.10), the steady state value of Vdd is Vdd = 3.5 volts. In concert with this power
line voltage and a value of voltage Vkk that is 10% larger than its minimum required value, the steady
state values of Iref and Ik are Iref = 100 μA and Ik = 1.0 mA. For the HSPICE or alternative SPICE
simulations requested below, use the NMOS parameters itemized in Table (4.1) to model the transistors. In these simulations, set the drawn channel lengths of transistors M1 and M2 to L = 1.5 μm,
and pick the gate widths of the transistors to assure proper operation of the mirror in the steady state.
The resistance, Rr, associated with current source Iref is Rr = 80 KΩ, while capacitance Cr, which is
also associated with this reference source, is Cr = 25 fF. Once you have chosen the gate widths of
both transistors, make sure that you appropriately set the area and periphery parameters, As, Ad, Ps,
and Pd so that a realistic account is made of high frequency effects in the transistors. As mentioned
at the beginning of this chapter, bulk connections, while not explicitly depicted in the schematic diagram of Figure (P5.7), are presumed connected to ground potential.
(a). Simulate a static sweep of the current, Ik, versus voltage Vdd, for 0 ≤ Vdd ≤ 5 volts. Over what
range of Vdd is current Ik held fast to within ±10%?
(b). Simulate the small signal frequency response of the magnitude of the driving point output
impedance, Zout, making sure to maintain the quiescent operating point in the course of executing this simulation.
i. What is the significance of the low frequency value of Zout?
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Chapter 5
MOSFET Biasing
ii. Does capacitance Cr dominantly affect the magnitude response of Zout, especially at signal
frequencies for which the magnitude of the output impedance degrades from its low frequency value by a factor of the square root of two?
Vdd
Vkk
Iref
Rr
Ik
Cr
Rout
M1
M2
x1
xk
M3
M4
x1
xk
Figure (P5.7)
(c). Repeat Part (a), but now, execute a static output current sweep with respect to voltage Vkk for 0
≤ Vkk ≤ 3 volts. How does the static output current sensitivity to Vkk relate to the low frequency
output impedance?
(d). Simulate the frequency responses of the real and imaginary components of the driving point
output admittance, Yout = 1/Zout.
i. What engineering significance can be attached to the low frequency value of the inverse of
the real part of impedance Zout?
ii. Plot the simulated output capacitance as a function of signal frequency.
iii. What engineering significance can be attached to the low frequency value of the output
capacitance?
PROBLEM #5.8
For the modified Wilson current sink shown in Figure (P5.8), use the low frequency, small signal
equivalent circuit of a MOSFET to derive an expression for the indicated resistance, Rin, established
between circuit ground and the drain/gate node of transistor M1. In this equivalent circuit, ignore
body effect but account for channel resistance, as required. Comment as to the effect exerted on this
nodal resistance by the ratio, k, of gate aspect ratios. Bulk connections are presumably made to network ground.
Vdd
Vkk
Ik
Rr
Rin
Rout
M1
M2
x1
xk
M3
M4
x1
xk
Figure (P5.8)
PROBLEM #5.9
In some current mirrors, such as the modified Wilson sink given in Figure (P5.8), the reference cur- 481 -
Chapter 5
MOSFET Biasing
rent, Iref, is realized on chip with an active circuit. In this case, Iref derives as the drain current of
PMOS transistor M5. In the simulations requested below, use the HSPICE transistor model parameters itemized in Tables (4.1) and (4.2). In these simulations, let the channel lengths of all transistors
be 1.5 μM. The gate widths of transistors M1, M3, and M5 are 5 μM. For steady state operation, Vdd
= 3.8 volts, while Vkk = 2.7 volts.
Vdd
Vkk
Ik
Vbias
M5 Iref
Rout
M1
M2
x1
xk
M3
M4
x1
xk
Figure (P5.9)
(a). Using HSPICE or equivalent simulation software, adjust voltage Vbias to obtain Iref = 100 μA.
With Iref = 100 μA, output current Ik should nominally equal 1 mA.
(b). Simulate the static transfer characteristic of Ik -versus- voltage Vkk for 0 ≤ Vkk ≤ 4 volts. Discuss
the results in light of the work executed in Example #5.3.
(c). Simulate the static transfer characteristic of Ik -versus- voltage Vdd for 0 ≤ Vdd ≤ 5 volts. How
might the M5 subcircuit be modified to improve this static transfer characteristic?
PROBLEM #5.10
In the simplified Wilson current sink of Figure (P5.10), reference current Iref derives as the drain current of PMOS transistor M5. In the simulations requested below, use the HSPICE transistor model
parameters itemized in Tables (4.1) and (4.2). In these simulations, let the channel lengths of all
transistors be 1.5 μM. The gate widths of transistors M3 and M5 are 5 μM. For steady state
operation, Vdd = 3.8 volts, while Vkk = 2.7 volts.
Vdd
Vkk
Ik
Vbias
M5
Rout
Iref
M2
Rin
xk
M3
M4
x1
xk
Figure (P5.10)
(a). Using HSPICE or equivalent simulation software, adjust voltage Vbias to obtain Iref = 100 μA.
With Iref = 100 μA, output current Ik should nominally equal 1 mA.
(b). Simulate the static transfer characteristic of Ik -versus- voltage Vkk for 0 ≤ Vkk ≤ 4 volts. Discuss
the results in light of the work executed in Example #5.3.
(c). Use the low frequency, small signal model to deduce an expression for the indicated output
resistance, Rout. Ignore body effect in all transistors and ignore channel length modulation
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Chapter 5
MOSFET Biasing
whenever it is appropriate to do so. What effect does the M5 channel resistance, ro5, have on
Rout?
(d). Use the low frequency, small signal model to deduce an expression for the indicated input
resistance, Rin. Ignore body effect in all transistors and ignore channel length modulation
whenever it is appropriate to do so. What effect does the M5 channel resistance, ro5, have on
Rin?
PROBLEM #5.11
In the circuit of Figure (5.22), let Input #1 and Input #2 be driven by the same small signal voltage,
say Vcs. Assume that in response to this applied input voltage, current Id3 remains unchanged.
(a). Explain clearly why the voltage responses at Output #1 and Output #2 are zero when current Id3
remains unaffected by the applied input signals.
(b). If current Id3 is indeed unchanged when voltage Vcs are applied to both input ports of the amplifier, what is the resultant change in voltage Vkk. Do not execute a definitive small signal
analysis to answer this query. Rather, submit your answer in the form of valid, qualitative
engineering arguments.
PROBLEM #5.12
In the degenerated current sink of Figure (P5.12), the gate aspect ratios of transistors M1, M2, M3,
and M4 are such that
W3
W
W
W
 k31 1  k31 2  k31 4 .
L3
L1
L2
L4
All transistors show negligible bulk-induced threshold modulation, while CLM can be ignored in all
devices, except transistor M3.
Ip
Vdd Vkk
M2
W2 /L2
Ik
Rp
Rout
Vref
M1
W1 /L1
M3
Cp
W3 /L3
M4
M5
W4 /L4
W5 /L5
Figure (P5.12)
(a). If current Ik is to be determined as Ik = k31Ip, how must the gate aspect ratio of transistor M5 be
selected?
(b). Why is it appropriate to neglect channel length modulation in transistors M1, M2, M4, and M5,
but not in transistor M3?
(c). Which transistors experience bulk-induced threshold voltage modulation? For each of these
transistors, what is the static bulk-source voltage?
(d). Determine analytical expressions for resistance Rp and capacitance Cp. The capacitance is to
behave nominally as a short circuit for frequencies exceeding the value, fl.
(e). Derive an analytical expression for the indicated output resistance, Rout. Discuss the effect that
transistor M5 has on this output resistance.
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Chapter 5
MOSFET Biasing
PROBLEM #5.13
In the balanced, folded cascode, differential amplifier of Figure (P5.13), all transistors operate in
their saturation domains and project negligible mobility degradation, negligible CLM, and negligible
threshold voltage body effect. All NMOS transistors are matched, inclusive of their gate aspect ratios, while the PMOS devices, M3, M4, M5, and M6 are likewise matched, inclusive of their respective gate aspect ratios. Moreover, while transistor M11 is a chip device that is similar to matched
transistors M3 and M4, the gate aspect ratios of M3 and M4 (and, of course, M5 and M6) are kp-times
larger than that of M11. Finally, the indicated tail current, Ik, is sufficiently large to render
inconsequential any I/O nonlinearities that may be incurred by reasonable amplitudes of the applied
differential input signal, Vdi. What is the quiescent drain current conducted by transistors M5 and
M6? Express your answer in terms of currents Ik, Ibias, and kp.
Vdd
Vbias1
x1
x kp
M11
x kp
x kp
x kp
M4
M5
M6
Vo
M3
M8
Vbias2
M7
Ibias
Vdi
2

M1
M2



Ik
M9
M10
Vdi
2
CL

Vgg

Figure (P5.13)
PROBLEM #5.14
Vx
Rout
Io

Ii
VB


A

M1
M3
xK
M2
x1
xK
Figure (P5.14))
The amplifier in the high impedance current sink of Figure (P5.14) is ideal in the senses of having
infinitely large input resistances at both of its input ports, zero output resistance at its output port,
- 484 -
Chapter 5
MOSFET Biasing
and constant, finite, positive voltage gain, A. All NMOS devices are identical except for the fact
that the gate aspect ratios of transistors M2 and M3 are each larger than the gate aspect ratio of M1
by a factor of K. The traditional square law relationship, Id = n(Vgs − Vh)2, applies to all transistors,
with the understanding that parameter βn is directly proportional to gate aspect ratio. Observe that
the drain of transistor M3 is connected to a node that supports a quiescent voltage of Vx. Finally,
current Ii is a constant and derives from an ideal, constant current source. The applied voltage, VB,
likewise derives from a constant source of voltage.
(a). In terms of current Ii, device threshold voltage, Vh, and device parameter βn, determine the M3
gate-source voltage, Vgs3, which supports the indicated output current, Io.
(b). In terms of Ii, Vh, βn, and amplifier gain A, what minimum value of voltage VB is required to ensure that transistor M2 operates in saturation?
(c). Assuming voltage VB satisfies the constraint imposed in Part (b), what minimum value of voltage Vx is required to assure saturation of transistor M3? Express this minimum voltage in
terms of Ii, and βn.
(d). Use small signal analysis to find the indicated low frequency output resistance, Rout, in terms of
amplifier gain A and the forward transconductances and channel resistances of pertinent transistors
PROBLEM #5.15
In the majority of portable electronic networks, it is desirable to render the static current, Iload, supplied to an arbitrary load as independent as possible of the power supply voltage, say Vdd. It is also
advantageous to have this static current nominally independent of the effective load resistance, Rload,
through which it flows. To these ends, the biasing circuit shown in Figure (P5.15) can achieve
supply-independent biasing and load-independent biasing if voltage Vdd is large enough to ensure the
saturation regime operation of all transistors in the diagram. In the indicated schematic diagram, the
bulk terminals of the two NMOS transistors are incident with circuit ground, while the bulk terminals of the three PMOS transistors are returned to the +Vdd supply line. All NMOS transistors are
identical, as are all PMOS devices, subject to the following gate aspect ratio provisos.
(1). The gate aspect ratio of transistor M4 is W4 /L4 = 20.
(2). The gate aspect ratio of M5 is W5 /L5 = α2(W4 /L4) = 20α2.
(3). The gate aspect ratios of both M1 and M2 are 5; that is, W1 /L1 = W2 /L2 = 5.
(4). The gate aspect ratio of M3 is W3 /L3 = 10(W1 /L1) = 10(W2 /L2) = 50.
Vdd
M1
M3
M2
IQ4
Rm
M4
IQ5
Iload
R
Rk
M5
Figure (P5.15)
(a). Derive an expression for the indicated biasing current, Iload, by using the simple SchichmanHodges, square law model of a MOSFET. Reduce this expression for the case of a large resis- 485 -
Chapter 5
MOSFET Biasing
tance, Rm. In particular, ignore the effects of CLM, BITM, mobility degradation incurred by
both vertical and lateral channel electric fields, and all other higher order phenomena. The result requested should be expressed exclusively in terms of n-channel transistor parameter Kn,
geometry factor α, and circuit resistance R.
(b). What purpose is served by resistance Rm?
(c). Aside from producing a small load current, Iload, an excessively large resistance value, R, breeds
at least one other detriment to acceptable circuit operation. What is this shortfall?
(d). What undesirable operating condition arises from too large a value of the effective load resistance, Rk?
PROBLEM #5.16
The biasing circuit in Problem #P5.15 is to be designed to deliver Iload = 125 μA when Vdd = 2.5
volts. All transistors boast 0.5 μM channel lengths, and their SPICE Level 3 model parameters appear in Tables (4.1) and (4.2). Remember that for all simulations, the capacitance area and periphery parameters, As, Ad, Ps, and Pd, must be specified to reflect the adopted gate aspect ratio of each
transistor.
(a). Design the circuit by specifying all transistor gate aspect ratios and all resistance values. Be
aware that there is no unique answer. There are only reasonable design answers, based on the
simulations you must execute.
(b). Simulate the static transfer characteristic, Iload versus Vdd, for 0 ≤ Vdd ≤ 5 volts. What is the
minimum required value of supply voltage Vdd, which is commensurate with a load current that
is at least 90% of its design target? How might this minimum voltage be reduced? Comment
as to the sensitivity of Iload with respect to Vdd and offer suggestions as to how this sensitivity
can be improved.
(c). Simulate the transient drain current responses of all transistors for the case when Vdd is a 2.5
volt step activated at time t = 0. What, if any, transistors are candidates for potentially catastrophic current overstress?
PROBLEM #5.17
Using the simple square law volt-ampere model of a MOSFET (no CLM, no mobility degradation,
no BITM, no second order effects in general), derive an expression for the indicated current, Iload, in
the biasing network of Figure (P5.17). The two PMOS devices have identical gate aspect ratios but
otherwise, do not presume that all transistors, which are fabricated on the same chip, have identical
gate aspect ratios. All transistors operate in their saturation regimes.
+Vdd
M1
M2
R
Iload
M3
M4
Figure (P5.17)
PROBLEM #5.18
The subcircuit formed of transistors M1, M2, M3, and M4 in Figure (P5.18) is the self-biasing
configuration addressed Section (5.5.1). Recall that this network suffers from a potential startup
problem, wherein it is possible that the subcircuit gives the useless steady state response IQ1 = IQ2 =
- 486 -
Chapter 5
MOSFET Biasing
0. In an attempt to mitigate this possible shortfall, the second subcircuit comprised of transistors M5
and M6, resistances R1 and R2, and capacitance C is appended as depicted in the schematic diagram.
The gate aspect ratios of M1 and M2 are identical, while the gate aspect ratio of M4 is k2-times larger
than that of M3.
SW
M1
M2
IQ1
M3
+Vdd
R2
IQ2
C
M4
M5
R1
M6
R
Figure (P5.18)
(a). Explain the operation of startup subcircuit immediately subsequent to closing switch SW at time
t = 0, which is tantamount to turning on the biasing circuit.
(b). Derive the design-oriented constraint that ensures the M5-M6-R1-R2 compensation subcircuit is
nominally non-conductive in the steady state. Why is it desirable to have this network nonconductive in the steady state? Use the simple Schichman-Hodges model for the transistors.
PROBLEM #5.19
The current, Iref, in the self-biased cascode of Figure (P5.19) is the current of an ideal, constant current sink. In what range of values must the voltage, RIref, dropped across resistance R lie to ensure
that transistors M1 and M2 are biased in their saturation domains? Use the simple square law model
of the volt-ampere characteristic of a MOSFET. The gate aspect ratios of the two active devices are
not necessarily the same.
+Vdd
M2
M1
R
Iref
Figure (P5.19)
- 487 -
Chapter 5
MOSFET Biasing
PROBLEM #5.20
In the supply independent biasing network of Figure (5.37), derive an expression for the smallest
allowable value, say Vmin, of voltage Vdd that guarantees the operation of all MOSFETs in the considered network in their respective saturation domains. Express this minimum voltage in terms of circuit and device parameters and current IQ.
PROBLEM #5.21
Figure (5.40) depicts a plausible startup module for the supply-independent network offered in Figure (5.37). An alternative and simpler startup scenario utilizes a single resistance, say Rp, between
ground, and the gate of transistor M7, as shown in Figure (P5.21). Unlike the startup subcircuit proposed in Figure (5.33), the resistance approach proposed herewith dissipates steady state power.
However, the power increment incurred by deploying Rp can be kept to a minimum by selecting
resistance Rp suitably large. Demonstrate analytically that a null current state is impossible in the
configuration of Figure (P5.21).
Vdd
x1
x1
x kp
M4
M3
M5
IQ
IQ
M1
M2
x1
x k212
Rp
Io
Rl
R
Figure (P5.21)
PROBLEM #5.22
The transistor in the subcircuit shown in Figure (P5.22) is to operate in its saturation domain. Body
effect can be ignored tacitly, but due account should be made of channel length modulation phenomena.
+Vdd
Rdd
R2
R1
IQ
M
Figure (P5.22)
(a). Deduce the quiescent design criterion that ensures transistor M6 operates in its saturation domain.
(b). Derive an expression for the indicated small signal resistance, Rdd.
- 488 -
Chapter 5
MOSFET Biasing
PROBLEM #5.23
Return to Example #5.5 and use HSPICE or equivalent computer-aided analysis software to examine
the transient response of current Ik to step excitation of voltage Vkk in both the uncompensated and
compensated versions of the current sink. In particular, let Vkk be a zero to 3.5 volt pulse waveform
having 1 nSEC rise and fall times, a 2 μSEC pulse width, and a period of 5 μSEC. Execute the
simulation for at least three time periods. Examine and assess both responses from the standpoints
of steady state performance, the time required to settle to steady state operation, overshoots and
undershoots, and general stability considerations.
PROBLEM #5.24
In the current sink of Figure (P5.24), all transistors are biased in saturation, have negligible CLM
and BITM, and all project negligible mobility degradation; in short, the static volt-ampere
characteristics of all transistors subscribe to the classic, long channel, Schichman-Hodges relationship. All transistors are fabricated on the same chip. But while transistors M1 and M2 have identical gate aspect ratios, transistors M3 and M4, respectively, have gate aspect ratios that are k-times
larger than the gate aspect ratios of the other two devices. In the design process, resistance R is chosen, and independent current source Iref is adjusted, to ensure that the drain-source voltage, Vds1, of
transistor M1 is its idealized drain saturation value, Vdsat = (Vgs1 − Vhn), where Vhn represents the
threshold potential of the NMOS transistors. Finally, capacitance C is large enough to emulate a
short circuit for all relevant nonzero frequencies.
Iref
Io
Vdd
Vo
Rout
R
M2
x1
C
M4
xk
M1
M3
x1
xk
Figure (P5.24)
(a). Determine the following static voltages:
i. the voltage, expressed in terms of current Iref, device transconductance metric βn1, and threshold potential Vhn, to which capacitor C charges in the steady state;
ii. the voltage, expressed in terms of current Iref and device transconductance metric βn1, developed across resistance R;
iii. in terms of current Iref and device transconductance metric βn1, the minimum required value
of voltage Vo that ensures operation of transistors M3 and M4 in saturation;
(b). Determine the requisite value of resistance R in terms of reference current Iref and transconductance parameter, βn.
(c). Derive an expression for the indicated small signal output resistance, Rout. In the course of
addressing this problem, do not ignore channel resistances in transistors M3 and M4.
(d). Determine the approximate time constant associated with capacitance C. In this calculation,
channel resistances in all active devices can be ignored tacitly.
PROBLEM #5.25
In the biasing network shown in Figure (P5.25a), all MOSFETs operate in their saturation regimes
where they boast negligible body effect, negligible mobility degradation, and negligible CLM.
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Chapter 5
MOSFET Biasing
Transistors M1 and M2 are identical pairs, inclusive of gate aspect ratios, as are transistors M3 and
M4, as indicated in the diagram. Transistor M5 is matched to M4, but has a gate aspect ratio that is
bigger than that of either M3 or M4 by a factor of P. The bipolar junction transistors, Q1, Q2, and
Q3, are matched devices, with the proviso that while Q1 and Q3 have identical emitter-base junction
injection areas, the emitter-base junction area of Q2 is a factor of M larger than the junction area of
either Q1 or Q3. With reference to Figure (P5.25b), the static volt-ampere characteristics of each
PNP bipolar junction transistor is given by
I e  I c  A j J s eVeb VT ,
where for large static beta, the emitter current, Ie, approximates the collector current, Ic. Moreover,
Aj represents the emitter-base junction injection area, Js is the density of bipolar saturation current,
Veb is the static voltage applied from the emitter to the base, and VT is the familiar Boltzmann voltage.
Vdd
M4
M3
M5
W3 /L1
W3 /L1
W1 /L1
W1 /L1
M1
PW3 /L1
Iref
Vref
M2
R1
Q1
Aj
Rout
R2
Q2
Q3
MAj
Aj
(a).
C

Veb

Ie
Q
Aj
Ic
(b).
Figure (P5.25)
(a). In terms of appropriate circuit resistances, Boltzmann voltage VT, and parameters P and M, develop an expression for the reference current, Iref.
(b). Assume that the temperature coefficient, dVeb/dT, of the emitter-base voltages of the bipolar
junction transistors is the constant, (−Se ). How must the resistance ratio, R2/R1, be chosen if the
reference output voltage, Vref, is to boast zero temperature coefficient? Assume that resistance
ratio R2/R1 is independent of operating temperature.
(c). Respond clearly and briefly to the following queries.
i. What makes voltage Vref substantially independent of power line voltage Vdd?
ii. What makes an idealized zero temperature coefficient to Vref possible in this problem?
iii. What fundamental purpose is served by capacitance C?
iv. Is the low frequency output resistance, Rout, large or small? Explain briefly!
PROBLEM #5.26
Convert the regulated cascode current sink of Figure (5.41) into a regulated cascode current source.
Submit a circuit diagram of the current source.
PROBLEM #5.27
In the network shown in Figure (P5.27), all transistors operate in saturation and show negligible
body effect. The NMOS transistors, M1 and M2, are identical and have identical gate aspect ratios,
while for the physically similar PMOS devices, the gate aspect ratio of transistor M3 is k-times that
of transistor M4. The currents, Ikk and Iss derive from ideal, constant current sinks.
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Chapter 5
MOSFET Biasing
(a). In terms of relevant circuit and/or transistor parameters, determine the quiescent values of the
currents, I1, I2, I3, and Io.
(b). Derive an expression for the indicated output resistance, Rout. Ignore channel length modulation
only if you can justify its tacit neglect.
+Vdd
x1
xk
M4
M3
I1
I3
Rout
Ikk
I2
M1
Rl
M2
Io
Iss

Vgg

Figure (P5.27)
PROBLEM #5.28
The NMOS transistor in the common source amplifier of Figure (P5.28) has a gate aspect ratio, W/L,
of 10, a threshold voltage, Vhn, of 1 volt, and a channel length modulation voltage, Vλ, of 45 volts.
Approximate the bulk-induced threshold modulation voltage, Vθ, as 0 volts. Also, measurements
taken in the laboratory show that for a gate-source voltage, Vgs, of 1.5 V and a drain-source voltage,
Vds, of 400 mV, the static drain current conducted by the transistor is Id = 60 μA. The indicated load
resistance, Rl, is 10 KΩ, while the source resistance, Rs, is 300 Ω.
2.5 V
Rd
Rout
Vo
Rs
Rl

Vs

Id

Vbias

2.5 V
Figure (P5.28)
(a). Compute the values of resistance Rd and bias voltage Vbias so that the transistor conducts a static
drain current, Id, of 500 μA when the static value of the output voltage, Vo, is 0 V. Be advised
that when computing the requisite bias voltage, Vbias, an acceptable first order approximation is
the tacit neglect of CLM phenomena.
(b). What is the error incurred in static drain current as a result of the neglect of channel length
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Chapter 5
MOSFET Biasing
modulation?
[Assume that the approximate operating point corresponding to the computed input bias voltage prevails for the remaining parts of this question.]
(c). Give a general expression for, and compute the value of, the small signal Thévenin output port
resistance, Rout.
(d). Give a general expression for, and compute the value of, the small signal low frequency
transconductance, Gm, which is recalled to be the ratio of the Norton load current to the signal
source voltage.
PROBLEM #5.29
In the PMOS common source amplifier of Figure (P5.29), the transistor has a gate aspect ratio, W/L,
of 20 μM/3 μM, a threshold voltage, Vhn, of 700 mV, and a channel length modulation voltage, Vλ,
which can be taken to be infinitely large. Assume that the bulk-induced threshold modulation voltage, Vθ, is 0 volts. Also, measurements taken in the laboratory confirm that Kp = μpCox = 30 μA/V2.
The indicated load resistance, Rl, is 10 KΩ, while the source resistance, Rs, is 300 Ω.
2.5 V
Rs

Rout
Vs
Vo

Rd

Vbias

Rl
Id
2.5 V
Figure (P5.29)
(a). Compute the values of resistance Rd and bias voltage Vbias so that the transistor conducts a static
drain current, Id, of 500 μA when the static value of the output voltage, Vo, is 0 V.
[Assume that the approximate operating point corresponding to the computed input bias voltage
prevails for the following remaining parts of this question.]
(b). Give a general expression for, and compute the value of, the small signal Thévenin output port
resistance, Rout.
(c). Give a general expression for, and compute the value of, the small signal low frequency Norton
transconductance, Gm.
PROBLEM #5.30
In the CMOS common source amplifier of Figure (P5.30), the p-channel device, transistor M2, has
a gate aspect ratio, W/L, of 20 μM/3 μM, a threshold voltage, Vhn, of 700 mV, and a CLM voltage,
Vλ, that can be presumed infinitely large. Assume further that its BITM voltage, Vθ, is 0 volts.
Measurements taken in the laboratory confirm that Kp = μpCox = 30 μmho/volt. On the other hand,
M1 is an NMOS device having a gate aspect ratio, W/L, of 10, a threshold voltage, Vhn, of 1 volt,
and a CLM voltage, Vλ, of 45 volts. Assume that its BITM voltage, Vθ, is 0 volts. For this transistor, a gate-source voltage, Vgs, of 1.5 V and a drain-source voltage, Vds, of 400 mV, delivers a static
drain current of Id = 60 μA. The indicated load resistance, Rl, is 5 KΩ, while the source resistance,
Rs, is 300 Ω.
(a). Compute the values of the biasing voltages, Vbias2 and Vbias1, so that the transistors conduct static
drain currents of Id2 = Id1 = 100 μA when the static value of output voltage Vo is 0 V.
[Assume that the approximate operating point corresponding to the computed input bias voltage
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Chapter 5
MOSFET Biasing
prevails for the following remaining parts of this question.]
(b). Give a general expression for, and compute the value of, the small signal Thévenin output port
resistance, Rout.
2.5 V

M2
Vbias1

Id2
Rs
Vo
M1

Rout
Rl
Vs

Id1

Vbias2

2.5 V
Figure (P5.30)
(c). Give a general expression for, and compute the value of, the small signal low frequency Norton
transconductance, Gm.
PROBLEM #5.31
The biasing task underlying the design of even relatively simple CMOS amplifiers can rarely be
accomplished by inspection. Moreover, the biasing requirements can rarely be cast in convenient
closed mathematical forms. A case in point is the amplifier depicted in Figure (P5.31). The PMOS
transistor in this configuration has Kp = 90 μmho/volt, Wp/Lp = 100, Vhp = 800 mV, Vθ = 0, and Vλ →
∞. On the other hand, the NMOS device is characterized by Kn = 150 μmho/volt, Wn/Ln = 10, Vhp =
700 mV, Vθ = 0, and Vλ → ∞. The supply line voltage, Vdd, is 3.3 volts, the source resistance, Rs, is
50 Ω, and the load resistance, Rl, is 1 KΩ. The design objective is to select the biasing voltages, Vbias
and Vgg, such that both transistors operate in their respective saturation regions when the output voltage, Vo, swings from its minimum allowable value to its maximum possible value.
Vdd

M2
Vbias

Id2
Rs

Vo
Id1
M1
Rl
Vs


Vgg

Figure (P5.31)
(a). Convince yourself that the maximum possible value of the output voltage, Vo, is realized when
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Chapter 5
MOSFET Biasing
transistor M1 is cutoff. Under this cutoff condition, evaluate
i.
the current, Id2, conducted by transistor M2;
ii.
the numerical value of the maximum output voltage, say Vomax;
iii. the numerical value of the biasing voltage, Vbias, required to sustain the current, Id2;
iv. the anticipated change in current Id2 if Vo is allowed to fall below its maximum value.
(b). What is the required value of the biasing voltage, Vgg, commensurate with minimum output voltage and saturation operation of both transistors? What current is conducted by the load and
transistor M1 under this minimum output voltage condition?
(c). Subject to the foregoing saturation constraints, determine the maximum possible, peak to peak
swings in
i.
the current, Id2, conducted by transistor M2;
ii.
the current, Id1, conducted by transistor M1;
iii. the output voltage, Vo;
iv. the net effective input voltage, (Vgg + Vs).
(d). What value of Vgg would you pick to ensure saturation region operation of transistor M1, despite the possibility of maximum output voltage swing?
PROBLEM #5.32
In the reference biasing circuit of Figure (P5.32), both transistors exhibit negligible CLM, negligible
carrier mobility degradation, and negligible body effect. Observe that the gate aspect ratio of
transistor M2 is larger than the gate aspect ratio of M1 by a factor of k2. The constant current, Ik, can
be presumed to derive from an ideal current source.
Ik
+Vdd
R
Vref
M2
x k2
Rout
M1
x1
Figure (P5.32)
(a). In terms of current Ik, what condition must circuit resistance R satisfy to ensure that transistor
M2 operates in its saturation domain.
(b). Assuming that M2 indeed operates in saturation, determine, in terms of parameter k, the indicated output resistance, Rout.
(c). Assuming that parameter k is held as a fixed constant, give two design recommendations that
support low output resistance.
PROBLEM #5.33
The network in Figure (P5.33) is proposed as a biasing circuit that establishes a current sink current,
IQ, which is reasonably independent of the supply line voltage, Vdd. In all transistors, CLM, mobility
degradation, BITM, and other high order modeling phenomena are ignored. This means that the
NMOS drain currents, Id, relate to their applied gate-source voltages Vgs and threshold voltages, Vhn,
trough the classic, square law, Schichman-Hodges expression. Observe in the schematic diagram
that while all NMOS and PMOS devices are respectively identical integrated circuit transistors, the
gate aspect ratio of transistor M5 is k-times larger than that of either transistors M1 or M2.
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Chapter 5
MOSFET Biasing
(a). In terms of resistance R, threshold voltage Vhn, transconductance factor βn1, and gate aspect
variable k, derive an expression for the indicated current, IQ.
(b). In terms of the same variables noted in the preceding part of this problem, what is the minimum
allowable value of static voltage Vx?
+V dd
+V x
M3
M4
Rout
x1
x1
Id1
IQ
Id2
M1
x1
M2
x1
R
M5
xk
Figure (P5.33)
(c). If channel length modulation is not ignored, what, in terms of relevant transistor parameters, is
the indicated output resistance, Rout?
(d). The circuit at hand provides a sinking bias current, IQ; that is IQ is sunk through a transistor and
thence to ground from a circuit node that supports a suitable voltage, Vx. Can transistor M5 and
its circuit connections be modified so the circuit sources the current IQ? By current “sourcing”
is meant a current injected to ground from an appropriately connected transistor.
(e). Is circuit boot up or start up a problem with the network at hand?
PROBLEM #5.34
In the self-biasing network of Figure (P5.34), the PMOS and NMOS transistors are respectively
identical, transistors M1, M2, and M3 have identical gate aspect ratios, and the gate aspect ratio of
transistor M4 is K2-times larger than the gate aspect ratio of M3. For static analysis purposes, CLM
can be ignored. All transistors operate in their saturation regimes.
+Vdd
Rss
M3
M4
W/L
K2W/L
W/L
W/L
Iout
C
M1
M2
Figure (P5.34)
(a). Derive an expression for the indicated quiescent output current, Iout; express your result in terms
of resistance Rss, gate aspect ratio parameter K, and relevant transistor parameters.
(b). To the extent that all transistors operate in saturation, respond to the following queries as
clearly, but as briefly, as possible.
i.
Is the static output current, Iout, independent of supply voltage, Vdd?
ii. Is the static output current, Iout, independent of temperature?
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Chapter 5
MOSFET Biasing
Is the static output current, Iout, independent of such processing parameters as gate width,
channel length, and gate oxide thickness?
(c). If CLM is not ignored, would static current Iout remain independent of Vdd? Briefly explain your
conclusion without re-solving the problem for current Iout.
iii.
PROBLEM #5.35
One way of examining the first order effect of channel length modulation in the biasing structure of
Figure (P5.34) commences with allowing Vdd to take on a small voltage change, say ΔVdd. Then, a
solution is found for the small signal transconductance, Gdd Δ ΔIout/ΔVdd, where ΔIout is understood to
be the change in output current that results from the presumed small change, ΔVdd, in supply voltage
Vdd.
(a). For the biasing network in Figure (P5.34), draw the small signal equivalent circuit pertinent to
an evaluation of the aforementioned transconductance, Gdd. Neglect channel resistances in
transistors M1 and M4, but not in transistors M2 and M3. Assume that the change in power
supply voltage is caused by noise incurred at frequencies that are large enough to enable
capacitance C in the biasing structure to be represented by a signal short circuit.
i.
Do not necessarily presume that corresponding small signal transistor parameters are identical. To this end, what is the relationship between the small signal transconductances, gm1
and gm2, of transistors M1 and M2, respectively?
ii. What is the transconductance parameter interrelationship of transistors M3 and M4?
(b). Evaluate the transconductance, Gdd, implied by the model deduced in Part (a).
(c). What channel resistance must be very large if Vdd is to have negligible impact on current Iout?
(d). Why is it reasonable to ignore the channel resistances of transistors M1 and M4?
(e). Recalling that we are interested in gauging the effect that voltage Vdd has on output current Iout,
why is it inappropriate to ignore the channel resistances in all transistors? Explain your conclusion!
(f). Do we need to have small or large Gdd if current Iout is to be invulnerable to any electrical noise
incurred along the power supply bus?
PROBLEM #5.36
In the current mirror shown in Figure (P5.35a), all transistors are matched, inclusive of their gate aspect ratios, and all devices operate in their saturation domains. The bulk terminals of all transistors
are returned to ground and although these connections do not achieve zero bulk-source bias in all
transistors, BITM is ignored tacitly in all devices.
Vdd
Iref
Io
M3
M4
M1
M2
Rout
Vdd
Iref
Io
M4
M1
(a).
M2
(b).
Figure (P5.36)
(a). Give an expression that relates the static output current, Io, to the applied static reference current, Iref.
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Chapter 5
MOSFET Biasing
(b). A colleague of yours argues that transistor M3 is superfluous and that the circuit shown in Figure (P5.36b) works just as well. You argue that because of your unimpeachable education, you
can see that while the alternative configuration is fundamentally functional, your original circuit
in Figure (P5.36a) provides superior current mirroring. What rationale in support of the excellent current mirroring provided by your circuit did you provide to your depraved technical colleague?
(c). Derive an expression for the output resistance, Rout, in the current mirror in Figure (P5.36a).
Why is it reasonable to ignore channel resistance in transistors M2 and M3 but unreasonable to
invoke this approximation for transistors M1 and M4?
PROBLEM #5.37
In the low voltage, high resistance current sink diagrammed in Figure (P5.37) and studied in Section
(5.6.3), derive expressions for the indicated driving point resistances, Rg4 and Rd5. Assume that all
current sources are ideal, constant currents, and ignore BITM throughout. Furthermore, assume all
MOSFETs operate in their respective saturation regimes. Ignore transistor channel resistances if and
only if you can clearly justify such neglect.
+Vdd
Vkk
Iin
IQ1
IQ2
Rd5
Rg4
VQ1
M4
x1
Ik
Rout
VQ2
M5
M2
x1
x1
Vref
M6
M1
xk
M3
xk
x1
Figure (P5.37)
PROBLEM #5.38
x kp
x kp
M2
M1
+Vdd
VB1
x1
M4
x1
M3
VQA
VB2
M5
M6
x kn
x1
M6
x9
M5
x1
VQB
VQC
R
Figure (P5.38)
The network shown in Figure (P5.38) is used to establish three static voltages, VQA, VQB, and VQC,
which can be used to bias other monolithic subcircuits that are not shown in the subject figure. Bias
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Chapter 5
MOSFET Biasing
sources VB1 and VB2 are constant voltages implemented by circuitry that is not shown in the diagram.
Assuming negligible CLM, BITM, and all other high order modeling phenomena, use the square
law, Schichman-Hodges model to analyze the circuit. Your analysis should minimally offer the
following results.
(a).
(b).
(c).
(d).
A general expression for output voltage VQA.
A general expression for output voltage VQB.
A general expression for output voltage VQC.
General expressions for the static voltages established at all circuit nodes. An implicit design
requirement is that all transistors operate in their respective saturation regimes.
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