Mismatch in Circuit Design
V.M. Brea
PhD Course
2005-2007
Dept. of Electronics and Computer Science
University of Santiago de Compostela
Santiago de Compostela
Spain
Outline
„
„
„
„
„
Introduction
Mismatch- definition
Mismatch- models
Pelgrom Model
Final Remarks
Introduction (I)
„
Hardware approach to problems like:
„
Numerical Computation
„
„
„
„
„
Modeling
Vision Computing, Image Processing
Data base
Communication …
Data Acquisition
„
Sensors and Actuators
Introduction (II)
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Buy- off-the-shelf general purpose solutions
„
„
„
„
„
„
Supercomputers
PCs
DSPs
FPGAs
PLDs
Microcontrollers …
Introduction (III)
„
Build- chip design, Application Specific
IC (ASIC)
„
„
„
„
„
VHDL
VHDL-AMS
Standard cells
Mixed-Signal
Analog
Introduction (IV)
„
Hierarchy of IC Requirements and Choices
Overall Circuits
Requirements
and Choices
1.- Chip Power
2.- Chip Speed
3.- Functional
Density
4.- Chip Cost
5.- Architecture
Etc.
Overall MOSFET
Requirements
and Choices
1.- Vdd
2.- MOSFET Lea
Kage
3.- MOSFET Drive
Current
4.- Parasitic Series
Resistance
5.- Transistor Size
6.- Vt Control
7.- Reliability
MOSFET Scaling
and Design
Choices
1.- Tox, Lg, xj, Rs
2.- Channel
Engineering
3.- Oxynitride or
High K Gates
4.- Classical Planar
Or Non-Classical
CMOS Structures
Etc.
Process
Integration
Choices
1.- Thermal
Processing
2.- Overall
Process Flow
3.- Process
Modules
4.- Material
Properties
5.- Boron
Penetration
Introduction (V)
„
Top-down Design Flow of an ASIC
Natural Language
-Description of the
application
-Initial Specifications
Computing Software
Stage
-High-level Language
C, C++, Matlab …
-Additional Constraints
Specific Software
-Toos suited to the Hard
ware Model or Architec
ture
Hardware-Level
Design
Introduction (VI)
„
Errors in Circuit Design (I)
„
„
System-level- misconceptions, ill-posed problems
…
Hardware-level
„
Modeling
„
„
„
VHDL
RTL
SPICE, Spectre, Eldo Models …
Introduction (VII)
„
Errors in Circuit Design (II)
„
Hardware-level
„
Systematic Errors
„
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Wrong Technology and/or Operating Conditions
Low CMRR, Fan-out, PSRR …
Offset
Finite Output Impedance
Gain
Bandwidth
Harmonic Distortion- linearity
Post-layout Simulations
Etc.
Introduction (VIII)
„
Errors in Circuit Design (III)
„
Random Errors
„
„
„
„
Noise
Mismatch
Layout Errors- design
Manufacturing Errors- catastrophic failures
Manufacturing and Random errors drop
yield in a technology process
Mismatch- Definition (I)
„
„
Mismatch is the process that causes timeindependent random variations in physical
quantities of identically designed devices
Importance„
„
„
„
Analog
Digital
Mixed-Signal
Key- Mismatch Modeling
Mismatch- Definition (II)
„
Analog
„
„
„
„
Mixed-Signal
„
„
„
Offset in OA
Current mirrors- dc errors
Filters- cutt-off frequency
D/A and A/D Converters
Sense Amplifiers in DRAM cells
Digital
„
Transient Errors- Frequency
Mismatch- Definition (III)
„
Mismatch- types of
„
„
„
„
Lot-to-lot
Wafer to wafer
Inter-die (die to die)
Intra-die (device to device)
Mismatch is either characterized with in-house
methods (time consuming- user or foundry),
or with a mathematical model
Mismatch Models (I)
„
Circuit-based
„
„
Few parameters (2-3)
Many parameters (5-7)
„
„
Many of them correlated, difficult to use in
hand-analysis
Device-based
„
Many parameters, more precise, not usable
in hand-analysis, only in computer
simulations
Mismatch Models (II)
„
Circuit-based
„
Pelgrom and extensions- 3 parameters
„
„
„
Lovett- narrow devices show more mismatch
Seville- 5 parameters
Drennan- Motorola, 7 parameters
Process gradients are dealt with layout styles
like common-centroid, symmetry, and/or use
of dummy devices. Their effect is that of
systematic errors; not random
Pelgrom Model (I)
„
Parameters
„
Equations
VT 0 , γ , β
2
A
σ 2 (∆ V T 0 ) = VT 0 + S VT2 0 D 2
WL
2
A
γ
2
+ S γ2 D 2
σ (∆ γ ) =
WL
⎛ σ (∆ β
⎜⎜
β
⎝
) ⎞⎟
2
A β2
2
2
=
+
S
D
β
⎟
WL
⎠
Pelgrom Model (II)
„
„
Goal- to have expressions for rapid hand-analysis and trade-offs
evaluation
2
Assumptions
2 2
„ Closely spaced devices
A
S D <<
WL
„
In today technologies, for the two former parameters to be
comparable, D should be around 1mm. The above assumption is
reasonable
VBS = 0 ⇒ σ (∆γ ) = 0
„
No substrate effect. If there is any, an extra mismatch degradation
term must be added
Pelgrom Model (III)
„
Remark- For independent and normally distributed deviations in x
and y, the standard deviation of a function Z=f(x,y) is:
2
⎛ ∂f ⎞ 2
⎛ ∂f ⎞ 2
2
σ (Z ) = ⎜ ⎟ σ ( x ) + ⎜⎜ ⎟⎟ σ ( y )
⎝ ∂x ⎠
⎝ ∂y ⎠
2
„
Then for two functions Z (one subtracting from the other), we can
write:
∂f
∂f
∆Z = Z1 − Z 2 =
∆x + ∆y
∂x
∂y
2
⎛ ∂f ⎞ 2
⎛ ∂f ⎞ 2
σ (∆Z ) = ⎜ ⎟ σ (∆x ) + ⎜⎜ ⎟⎟ σ (∆y )
⎝ ∂x ⎠
⎝ ∂y ⎠
2
2
σ (∆Z ) = 2σ (Z )
Pelgrom Model (IV)
„
Across-regions equations (square-law):
⎛ σ (∆I DS ) ⎞ ⎛ σ (∆β ) ⎞ ⎛ g m ⎞ 2
⎟⎟ = ⎜⎜
⎜⎜
⎟⎟ + ⎜ ⎟ σ (∆VT )
⎝ I DS ⎠ ⎝ β ⎠ ⎝ I ⎠
2
2
2
⎛ σ (∆β ) ⎞
1
⎟⎟
⎜
σ (∆VGS ) = σ (∆VT 0 ) +
2 ⎜
(g m / I ) ⎝ β ⎠
2
2
2
Pelgrom Model (V)
„
Mismatch in strong inversion:
2
⎛ σ (∆I DS ) ⎞ ⎛ σ (β ) ⎞
4σ (VT 0 )
⎟⎟ = ⎜⎜
⎜⎜
⎟⎟ +
2
I
β
⎠ (VGS − VT )
DS
⎠ ⎝
⎝
2
2
(
VGS − VT ) ⎛ σ (β ) ⎞
⎜⎜
⎟⎟
σ (∆VGS ) = σ (VT 0 ) +
2
2
2
4
⎝ β ⎠
2
Pelgrom Model (VI)
„
The former equations can be approximated
(see table I and plot) by:
2
⎛ σ (∆I DS ) ⎞
4σ 2 (VT 0 )
4 AVT
0
⎟⎟ ≈
⎜⎜
=
2
2
I
(
)
(
)
−
−
V
V
WL
V
V
DS
⎠
⎝
GS
T
GS
T
2
A
σ 2 (∆VGS ) ≈ VT 0
WL
2
Pelgrom Model (VII)
Table I
Pelgrom Model (VIII)
Pelgrom Model (IX)
Mismatch on the design of elementary
stages- Current Mirror (I)
„
Design- trade-off
„ Three parameters- area, speed and power
„ Performance- combination of the three parameters above
3I B
gm1
=
BW =
2π (CGS 1 + CGS 2 ) 2π ( A + 1)(VGS − VT )CoxWL
P = ( A + 1)I BVDD
Accrel
I inRMS
=
3σ (I os )
Pelgrom Model (X)
Mismatch on the design of elementary
stages- Current Mirror (II)
„
We define the performance equation (PE):
2
Speed . Accuracy 2 BWAccrel
PE =
=
Power
P
„
To calculate the errors in Ios (Accrel), we first go through the
errors in the currents of M1 and M2 (current mirror transistors, in
and out, respectively). For M1, we can write:
2 AVT 0
1
IB
σ (IUNIT ) =
2 (VGS − VT ) WL
Pelgrom Model (XI)
Mismatch on the design of elementary
stages- Current Mirror (III)
„
For the standard deviation of the current of M2, we formulate:
σ (I OUT ) = Aσ (IUNIT )
„
And as the standard deviation is referred to the input current, the
standard deviation of the input offset current is as follows:
σ (I OS ) =
σ 2 (I OUT )
A2
2 AVT 0
IB
(VGS − VT ) WL
+ σ 2 (IUNIT ) =
A +1
A
Pelgrom Model (XII)
Mismatch on the design of elementary
stages- Current Mirror (IV)
„
With this, and assuming a typical bias modulation index of ½,
Accrel and PE become:
Accrel
WL (VGS − VT )
A
=
A +1
12 AVT 0
2
(
BWAccrel
VGS − VT )
A
PE =
=
3
2
P
V
96πCox AVT
(
)
A
+
1
0 DD
„
For large gains A, we would have:
2
(
Gain 2 BWAccrel
VGS − VT )
=
2
P
96πCox AVT
0VDD
Pelgrom Model (XIII)
Mismatch on the design of elementary
stages- Current Mirror (V)
„
Conclusions
„
„
„
„
Total performance (PE) depends on technology constants and on the
chosen bias point. It is independent of the transistor sizes
The best total performance comes with large (VGS-VT) values. Concern(VGS-VT) usually upper bounded by Vdd/2
Larger (VGS-VT) values lead to better accuracy numbers at the cost of
lower speeds. In order to increase speed, higher IB must be used,
resulting in higher power dissipation. The trade-off in the design of a
current mirror is quite clear
Finite output impedances and noise are additional concerns in current
mirror design
Pelgrom Model (XIV)
Mismatch on the design of elementary
stages- One Transistor Voltage Ampl. (I)
„
„
Goal- As in the current mirror, the goal is to find the best total
performance (PE)
For the figure displayed on the blackboard we can write:
⎞
Vout
R2 ⎛
1 − 1 / (gmR2 )
⎟⎟
A(s ) =
= − ⎜⎜
Vin
R1 ⎝ 1 + 1 / ( gmR1 ) + s / (gm / CGS ) ⎠
⎞
R2 ⎛
1
⎟⎟
A(s ) ≈ − ⎜⎜
R1 ⎝ 1 + s / ( gm / CGS ) ⎠
BW ≈ gm / (2πCGS )
3I B
BW =
2π (VGS − VT )WLCox
Pelgrom Model (XV)
Mismatch on the design of elementary
stages- One Transistor Voltage Ampl. (II)
„
For the power dissipation and the relative accuracy the next
equations hold:
P = VDD I B
Accrel
„
VinRMS
VDD WL
=
=
3σ (VOS ) 6 2 AVT 0Gain
Combining the three former equations we achieve:
2
Gain 2 BWAccrel
VDD
=
2
P
24π (VGS − VT )AVT 0Cox
Pelgrom Model (XVI)
Mismatch on the design of elementary
stages- Differential Pair Voltage Ampl. (I)
„
Similarly to the One Transistor Voltage amplifier, the next equations hold:
BW = gm / (2πCGS )
P = 2VDD I
Accrel
VDD WL
=
6 2 AVT 0Gain
2
Gain 2 BWAccrel
VDD
=
2
P
96π (VGS − VT )AVT
0Cox
„
This equation is esentially the same as that of a single transistor amplifier
Pelgrom Model (XVII)
Mismatch on the design of elementary
stages- Load Compensated OTA (I)
„
Input stage in OAs
„
„
Goal- to find the best total performance
New Constraint- to achieve safe phase and gain margins
„
The second pole plays a role in the gain-bandwidth (GBW) product
f2 =
„
gm2
3I B
=
2π (CGS 2 a + CGS 2b ) 4πCoxW2 L2 (VGS − VT )2
GBW must be made Kstab times smaller than the second pole in
order to ensure stability with feedback configurations, thus:
GBW =
f2
3I B
=
K stab 4πK stabCoxW2 L2 (VGS − VT )2
Pelgrom Model (XVIII)
Mismatch on the design of elementary
stages- Load Compensated OTA (II)
„
As for the Accrel:
Accrel =
AinVDD W2 L2
VinRMS
=
2
2
3σ (VOS ) 6 2Gain AVTN
+ AVTP
⎛ σ (VT 02 ) ⎞
⎟⎟ =
σ 2 (VOS ) = σ 2 (VT 01 ) + ⎜⎜
⎝ Ain ⎠
2
2
A
AVT
1
0p
VT
2
2
0n
+
=
AVT
0 n + AVT 0 p
2
2
W1 L1 W2 L2 Ain W2 L2 Ain
2
(
„
)
Where Ain is the internal gain of the amplifier from the
differential input to the upper current mirror:
g m1 (VGS − VT )2
W1
=
=
Ain =
g m 2 (VGS − VT )1
W2
Pelgrom Model (XIX)
Mismatch on the design of elementary
stages- Load Compensated OTA (III)
„
Now, with the power dissipation, we have an expression for the
total performance of the OTA:
P = 2 I BVDD
2
Gain 2GBWAccrel
VDD
=
2
2
+
192πK stab Cox AVT
P
A
0n
VT 0 p
(
„
)
⎛
⎞
Ain
⎜
⎟
.⎜
⎟
⎝ (VGS − VT )1 ⎠
Using GBW=Gain.BW we reach the final PE:
2
Gain 3 BWAccrel
VDD
PE =
=
2
2
192πK stabCox AVT
P
0 n + AVT 0 p
(
)
⎛
⎞
Ain
⎜
⎟
.⎜
⎟
(
)
V
V
−
GS
T
1⎠
⎝
Pelgrom Model (XX)
Mismatch on the design of elementary
stages- Load Compensated OTA (IV)
„
Conclusions
„
„
„
Total performance (PE) depends on technology
constants and on the chosen bias point
The best total performance comes with low (VGSVT) values in the transistors operating in voltage
mode (the differential pair), and with large (VGSVT) values in the current mirror
Stability brings in more constraints leading to
higher power dissipation values
Pelgrom Model (XXI)
Mismatch on the design of elementary
stages- Feedback syst. & OTA Design (I)
„
Goal- to find PE for a general OA with feedback
GBW = ACL BWCL
g mIN
=
2πCd
2I B
P = I BVDD ,
= g mIN
(VGS − VT )
P = πACL BWCL CdVDD (VGS − VT )
„
With Cd being the capacitor associated with the dominant pole of the
open-loop transfer function of the OTA and gmin being the
transconductance of the input stage
Pelgrom Model (XXII)
Mismatch on the design of elementary
stages- Feedback syst. & OTA Design (II)
„
As in former analysis we have:
2
rel
Acc
V C
=
48 A C A
(
VGS − VT )
C
P = 48π
VDD
2
DD in
2
2
CL ox VT 0
ox
2
VT 0
A
⎛ Cd ⎞
⎟⎟
A BWCL Acc ⎜⎜
⎝ Cin ⎠
3
CL
2
rel
Pelgrom Model (XXIII)
Mismatch on the design of elementary
stages- Feedback sys. & OTA Design (III)
„
Conclusions
„
„
„
The minimal power consumption is limited by the
technology, i.e. effect of mismatch. Likewise, PE is mainly
limited by the input transistor
To optimize PE in a voltage processing system, the input
stages have to be biased with low (VGS-VT) values; even in
weak inversion
Differently from open loop stages, in which the power
consupmtion is proportional to the square of the Gain, now
there is a cubic dependence on the Gain. This is caused by
another constraint in a feedback system, that is, the stability
requirements
Pelgrom Model (XXIV)
Mismatch on the design of elementary
stages- Gen. multi-stage volt. design (I)
„
In this case, the relative accuracy of the total system is determined
by the input signal RMS and the equivalent input referred offset
voltage as follows:
⎛ σ (VOS 2 ) ⎞ ⎛ σ (VOS 3 ) ⎞
⎟⎟ + ⎜⎜
⎟⎟ + ...
σ (VOSeq ) = σ (VOS1 ) + ⎜⎜
⎝ A1 ⎠ ⎝ A1 A2 ⎠
2
2
2
„
The former expression is dominated by the offset in the first stage.
The designer has to come up with the largest possible gain in the
first stage A1
Pelgrom Model (XXV)
Mismatch on the design of elementary
stages- Gen. multi-stage volt. design (II)
„
If the offset is dominated by that of the first stage, the next equation will
hold:
Accrel =
„
VinRMS
V
≈ inRMS
σ (VOSeq ) 3σ (VOS1 )
The source resistance Rs and the input capacitance C1 set the upper
boundary for the system speed:
2
AVT
2
2
0
C1 = CoxWL, σ (VOS ) =
3
2WL
2
Cox AVT
1
0
C1 =
, f lim =
2
2πRs C1
3σ (VOSeq )
2
rel
f lim Acc
2
VinRMS
≈
2
6πRs Cox AVT
0
Pelgrom Model (XXVI)
Mismatch on the design of elementary
stages- Gen. multi-stage volt. design (III)
„
Conclusions
„
„
The best possible matching has to be achieved in the first
stage (input) where the signal levels are the smallest. The
largest possible amplification has to be done as soon as
possible
Accuracy and speed are interdependent, and their relation is
fixed by the technology process
Pelgrom Model (XXVII)
Mismatch on the design of elementary
stages- Circuit Design Guidelines
„
Current Processing Stages
„
„
Design with as large a (VGS-VT) as possible. Limited by
other specifications like signal swing and power supply
voltage
Voltage Processing Stages
„
Design with as low a (VGS-VT) as possible. Limited by the
required speed
Pelgrom Model (XXVIII)
Mismatch on the design of elementary
stages- Mismatch vs. Noise (I)
„
„
„
Currently, the power dissipation is the main concern
in high performance circuit design, e.g. uPs
Mismatch and noise impose a minimum power
consumption for a circuit to work at a certain
frequency
Mismatch is caused by technology parameters,
whereas noise is caused by physical constants. Which
is the most important factor in the power dissipation
of a system?
Pelgrom Model (XXIX)
Mismatch on the design of elementary
stages- Mismatch vs. Noise (II)
„
Analysis of Power/cycle in a class B system with a source
resistance R driving a load capacitor C:
VsRMS
P = 8 fCV
, DR =
3σ (VOS )
And as the accuracy of a system is related to the input
capacitance, we can write:
2
2
sRMS
„
C1 ≈
Cox AVT 0
3σ 2 VOSeq
( )
2
2
P = 24Cox AVT
fDR
0
„
Due to the effect of mismatch, an analog system consumes at
least this power to perform a signal processing operation at a
frequency f with an accuracy or dynamic range DR
Pelgrom Model (XXX)
Mismatch on the design of elementary
stages- Mismatch vs. Noise (III)
„
The limit imposed by noise is given by:
kT
V
=
C
2
P = 8kTfDR
2
nRMS
„
The mismatch limit (technology dependent) is dominant over that
of noise (see plot)
Pelgrom Model (XXXI)
Mismatch on the design of elementary
stages- Mismatch vs. Noise (IV)
Pelgrom Model (XXXII)
Mismatch on the design of elem. stagesTechniques to reduce impact of mismatch
„
Auto-zero
„
Chopping
„
Trimming
Pelgrom Model (XXXIII)
Scaling (I)
„
„
AVT is mainly determined by fluctuations of dopant
atoms under the gate. Tox also plays a role. The
trend is to have a decreasing standard deviation on
AVT with shrinking technologies (see plots)
Beta is mainly determined by fluctuations in the
mobility factor. No consistent theory has been found
yet. The trend of the standard deviation on Beta with
shrinking technologies is not that clear, although it
might look like the same as that of AVT (see plots)
Pelgrom Model (XXXIV)
Scaling (II)
Pelgrom Model (XXXV)
Scaling (III)
Final Remarks (I)
„
„
„
„
Matching of devices proportional to
area, and thus capacitance
Accuracy requirements- minimal circuit
area and capacitance
Power to get a given bandwidth
increases with the circuit capacitance
Bandwidth-accuracy-power- technology
dependent
Final Remarks (II)
„
„
„
MOS current processing circuits- high
(VGS-VT) and low gm/I values
MOS voltage processing circuits- low
(VGS-VT) and high gm/I values
For a given bandwidth and accuracy,
the limit imposed by mismatch is
dominant over noise