SATURATION REGION GATE VOLTAGE VGS DR A IN V O LTA G E
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MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 MCC092:LECTURE2TheMOSFETTask#1OperatingregionsTaskonpage3 Then-channelMOSFET 1.2 D OFFREGION SATURATIONREGION DRAINVOLTAGEVDS SupplyvoltageVDD=1.2V LINEARREGION Electrons move upwards G 0 S A 1.2 VGS= VDS= B 1.2 0 0.8 .8 VGS= VDS= 0.2 7GATEVOLTAGEV C 0.1 0 GS D 0.4 1.2 0.1 0.6 VGS= VDS= 1.2 VGS= 0 VDS= 0 IDS 1.2 I DS = k 2 (VDD − VX − VT ) 2 Whichoperatingregionhere? VX OFFREGION 1.2 VDD-VT VDD VX MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 GATEVOLTAGEVGS -0.3 Thep-channelMOSFET -1.2 0 DRAINVOLTAGEVDS -1.2 1.2 A B 1.2 0.8 .8 0 VGS= VDS= D 1.2 0 1.1 VGS= VDS= 1.2 1.2 0.6 0 1.1 VGS= VDS= C 1.2 VGS= VDS= MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 On the two previous pages calculate VGS and VDS for the nMOS transistor and the pMOS transistor. For each type of transistor mark where the points A-D are located in the transfer diagram in the upper right corner. Task#2MOStransistorparameters–equivalentresistanceandcapacitance In this course we generally use a 65 nm CMOS process. In the name “65 nm” refers to the minimum transistor length (which actually is 60 nm, a bit strange but that is the way it is). According to the manufacturer, the maximum currents that these minimum-length MOSFETs can deliver or sink for a gate voltage equal to VDD, are 600 µA/µm for the n-channel devices, and 300 µA/µm for the p-channel devices. Furthermore, the gate oxide capacitance, Cox, is 20 fF/µm2 for both pMOS and nMOS transistors. The supply voltage, VDD, is 1.2 V in this process. In the nMOS-transistor output diagram shown above, the red line corresponds to an effective resistance R that can be used to model the capability of the transistor to deliver or sink current over the entire drain voltage range between the supply voltages (0 V and VDD). (We will talk more about that when we get to the inverter in lecture 3). a) Calculate the effective resistances for 1 µm wide nMOS and pMOS transistors. b) Calculate the gate capacitance, CG, for the same 1 µm wide nMOS and pMOS transistors. c) Calculate the RC time constants RCG for the two nMOS and pMOS transistors above. d) What if we double the widths of the nMOS and pMOS transistors to 2 μm? What are the effects on the effective resistances, gate capacitances, and RC time constants? MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 SOLUTIONS: Then-channelMOSFET . D Electronsmove upwardsfrom sourcetohigher potentialdrain S A 1.2 0 B 0.8 .8 VGS=0.8V VDS=0.1V 1.2 Modified! C LINEARREGION B 0 1.2 VGS=1.2V VDS=1.2V OFFREGION DRAINVOLTAGEVDS SATURATIONREGION G A D 1.2 SupplyvoltageVDD=1.2V 0.2 1.2 GATEVOLTAGEV GS 7 0.1 Modified! 0.4 C 0.1 0.6 0 VGS=0.6V VDS=0.4V D 1.2 VGS=0.1V 0 VDS=1.2V 0 IDS 1.2 I DS = VX ByincreasingVXslowlytowardsVDD, theMOSFETturnsitselfgraduallyoff. k 2 (VDD − VX − VT ) 2 OFFREGION SATURATIONREGION VX MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 Thep-channelMOSFET micronwiden-channeldevicecan deliveramaximumdraincurrentof -1.2 A 300uA,whichisonlyhalfofwhatan C n-channelMOSFETcandeliverdueto alowerholemobility. S Holesmove downwards fromsourceto lowerpotential drain G D 0 DRAINVOLTAGEVDS InST0.65nmCMOSprocessaone GATEVOLTAGEVGS -0.3 B D -1.2 1.2 1.2 S A 0 G D 1.1 VGS=-1.2V VDS=-0.1V 1.2 1.2 1.2 B C D 0.8 .8 0.6 1.2 0 VGS=-0.4V VDS=-1.2V 0.9 VGS=-0.6V VDS=-0.3V 0 VGS=0V VDS=-1.2V Note!Ititespecially MCC092MOSFETexercisewsolution2016-09-01 Rev1.1 Task 2 a) From the graph we see that we have π = !!! !!"#$ . A 1 µm nMOS transistor can deliver 600 µA current and a pMOS transistor 300 µA and VDD is 1.2 V. So we have: !.! V !.! V π ! = !"" !A = 2 kΩ and π ! = !"" !A = 4 kΩ. b) The capactiance is in its simplest form (that is when we neglect edge effects) πΆ! = ππΏπΆ!" . It is the same for pMOS and nMOS transistors. We find πΆ! = 1 µm × 0.06 µm × 20 fF/µm2 = 1.2 fF. c) The time constant is π πΆ! . For the nMOS transitor we find: π ! πΆ! = 2 kΩ × 1.2 fF = 2.4 ps and for the pMOS transistor: π ! πΆ! = 4 kΩ × 1.2 fF = 4.8 ps. d) If we make the transistors 2 µm wide the effctive resistances will be half as large but the capacitances will be doubled, so the time constants will remain the same. So these time contants seem to be fundamental for a particular CMOS process. We will talk more about that next week.
