54
CHAPTER 4
ELECTRO-OPTICAL HYBRID LOGIC GATES
55
CHAPTER 4
ELECTRO-OPTICAL HYBRID LOGIC GATES
4.0 INTRODUCTION
This chapter is devoted to describe the circuit structures of electrooptical hybrid logic gates like, hybrid inverter, hybrid NOR, hybrid NAND,
hybrid OR, hybrid AND and hybrid EX-OR. To conceive and realize these
hybrid logic circuits, optoelectronic devices like Light Emitting Diodes
(LED’s), and laser diodes which can give optical outputs and three
terminal photo detectors like phototransistors, which can respond to
optical signals are needed. Since alignment of light source and detectors
are involved in realizing hybrid logic circuits, it is proposed to use
optocouplers as they are available with perfectly aligned Light Emitting
Diode (LED) and the phototransistor in a single IC package. Hence,
optocouplers have been used for implementing and verifying the
functionality of different hybrid logic circuits.
Computer aided circuit analysis provides additional information
about the circuit performance that is some times difficult to obtain with
laboratory prototype measurements. Hence, to evaluate the hybrid circuit
performance under varied conditions (the variations in circuit elements),
these circuits have been simulated using OrCAD CAPTURE 10.3 circuit
simulation tool which is explained in APPENDIX-A. In order to arrive at
circuits for different hybrid logic functions, the characteristics of LED and
phototransistor
are
required.
Hence,
the
characteristics
of
these
optoelectronic devices have been described and simulated using OrCAD
CAPTURE
circuit
simulation
tool
[113-115].
From
the
device
characteristics, electrical and optical logic levels are defined and are used
to test the functionality of various hybrid logic gates.
4.1 CHARACTERISTICS OF LED
By varying the current through the LED, the intensity of light
output is changed. There is no access to measure the light intensity of
LED in the optocoupler. An LED model available in the library of OrCAD
56
CAPTURE circuit simulation tool has been used to calculate the light
output power based on the current flowing through the LED.
The Light-Emitting Diode model represents a light-emitting diode as
an exponential diode in series with a current sensor. The LED model has
three ports: W-port is optical output power, p-port is electrical conserving
port associated with the diode positive terminal and n-port is electrical
conserving port associated with the diode negative terminal. The optical
power presented at the signal port w is equal to the product of the current
flowing through the diode and the optical power per unit current
parameter value.
The LED parameters of 4N32 optocoupler which are used in the
simulation are given in Table.4.1. The Circuit diagram for simulation of
LED characteristics is shown in Fig.4.1. The output power versus forward
current (the forward current is varied by varying the input voltage V i )
characteristics of LED in 4N32 optocoupler is shown in Fig.4.2. A
measure of light intensity is obtained by noting the current through the
LED from the characteristics given in Fig.4.2. The V-I characteristics of
LED present in the optocoupler have also been simulated and is given in
Fig.4.3.
Table4.1. Simulation parameters of LED
LED property
Description
Value
IS
LED saturation current
77fA
N
LED emission coefficient
1.76
LED series resistance
2Ω
RS
CJO
LED zero bias junction capacitance
18pF
M
LED CJ exponent
0.5
VJ
LED contact potential
1V
ISR
LED reverse current
BV
LED breakdown voltage
IBV
Reverse breakdown knee current
TT
Transit time
0.05µA
3V
10µA
5ns
57
LED
R1
386Ω
V1
W-PORT
0-5V
Fig.4.1 Circuit diagram for obtaining LED characteristics.
12mW
12mA
2
1
8mA
8mW
6mA
Output power Po
10mW
Forward current IF
10mA
2
6mW
4mA
4mW
2mA
2mW
0A
1
0W
0V
1
2
0.5V
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
Input voltage V1
Fig.4.2 Forward current and output power of LED as a function of
input voltage V1.
5.0V
58
12mA
10mA
Forward current IF
8mA
6mA
4mA
2mA
0A
0V
0.1V
0.2V
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1.0V
1.1V
1.2V
Forward voltage
Fig.4.3 V-I characteristics of LED.
From the above characteristics, it may be noted that LED output
power is 0mW for I F =0mA and 10mW for
I F =10mA. The forward voltage
V F across the LED is 1.15V for I F = 10mA.
4.2 CHARACTERISTICS OF PHOTOTRANSISTOR
The response of phototransistor for input light can’t be measured in
the optocoupler IC and therefore has been simulated using OrCAD
CAPTURE simulation tool. Instead of using the light intensity as the input
parameter, the equivalent LED current (I F ) has been used. The circuit
diagram for obtaining the characteristics of phototransistor in 4N32
optocoupler is shown in Fig.4.4. In this circuit, V 1 is the input supply
voltage used to changed the forward current (I F ) through LED, V i is the
electrical input voltage to change the base current (I B ) of phototransistor
(PT), V CE is the collector to emitter voltage of PT, I C is the collector current
of PT, or R 1 is the current limiting resistor flowing through LED, R B is the
base current limiting resistor of PT. The characteristics obtained includes,
I F versus I C for constant V CE (transfer characteristics), V 1 versus I C and
output characteristics of phototransistor (I C versus V CE for different base
59
currents) respectively. The forward current (I F ) through LED is varied by
changing the input voltage (V 1 ) in steps. These characteristics are
obtained using OrCAD CAPTURE tool and the simulated characteristics
are given in Fig.4.5, Fig.4.6 and Fig.4.7.
RB
IB →
Vi
IF →
R1
← IC
386Ω
V1
Fig.4.4 Circuit
optocoupler.
4N 32
diagram
for
obtaining
6V
the
V CE
characteristics
of
4N32
240mA
IB = 10 µA
200mA
IB = 8 µA
160mA
IB = 6 µA
IC (mA)
120mA
IB = 4 µA
80mA
IB = 2 µA
40mA
0A
0V
0.5V
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
4.0V
VCE (V)
Fig.4.5 Output characteristics of phototransistor (VCE Vs IC).
4.5V
5.0V
60
Fig.4.6 Transfer characteristics of 4N32 optocoupler (I F versus I C ).
10mA
8mA
Collector voltage IC
6mA
4mA
2mA
0A
0V
0.5V
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
Input voltage V1
Fig.4.7 Transfer characteristics of 4N32 optocoupler (V1 versus IC).
61
From the above transfer characteristics, it may be noted that the
phototransistor collector current I C =9.6mA for V 1 =5V. The optoelectronic
device characteristics obtained above will enable the implementation of
hybrid circuits in terms of voltages and currents. To realize the hybrid
inverter function, the hybrid inverter circuit is required to complement or
invert the input signal i.e., the output must be LOW if the input is HIGH
and vice versa. This is accomplished by diverting the current from the
current source into the hybrid inverter circuit. Hence, a current source is
needed to implement the hybrid inverter function which is discussed in
the following section.
4.3 CURRENT SOURCE
A current source is used in the hybrid circuit as a power source. An
ideal current source is a circuit element where the current through it is
independent of the voltage across it. A current source provides a constant
current, as long as the load is connected to the source terminals has
sufficiently low impedance. An ideal current source has an infinite output
impedance.
The collector of a bipolar transistor behaves as current source when
properly connected to an external power supply, because the output
impedance of this device is high. The circuit diagram of the current source
with load resistor R L is shown in Fig.4.8. The current that the current
source supplies depends on base resistance (R B ) and current gain h FE of
the transistor used. This current source configuration is used as a power
source for the hybrid logic circuits reported in the thesis. The proposed
hybrid inverter has been discussed in the following section.
V EE
RB
Q
RL
Fig.4.8 Circuit diagram of current source.
62
4.4 HYBRID INVERTER
Circuit diagram of proposed hybrid inverter, its principle of
operation, experimental results and the transient response have been
discussed in the following section.
4.4.1 Circuit diagram of proposed hybrid inverter
The circuit diagram of proposed hybrid inverter or hybrid NOT gate
is shown in Fig.4.9. It consists of a current source in series with a
phototransistor and a load consisting of an LED to provide optical output
and a series resistor R L across which electrical output is taken. The
phototransistor is used as a switch which can be operated with either
electrical or optical input signals. The input to the phototransistor is
either current through the base of the phototransistor or the light
generated and coupled to the phototransistor due to the current flowing
through
the
source
LED.
The
source
LED
and
the
darlington
phototransistor are obtained using 4N32 optocoupler. For the sake of
simplicity in drawing the circuit diagrams, the darlington phototransistor
is shown as simple phototransistor in all circuit diagrams. The Load LED
is also obtained from the same 4N32 optocoupler, making sure that
source LED and Load LED are identical. The current source is
implemented using BC558A transistor.
In this circuit, V i indicates the electrical input and I i (current
through source LED) is the optical input. V o is the electrical output and I o
(current through Load LED) is the optical output of the gate. V 1 is power
supply voltage used to vary the input current I i through source LED, V EE
is the power supply to the current source, R B1 is the base current limiting
resistor of phototransistor, R 1 is the current limiting resistor of source
LED current, R B is the base resistance of current source and R L is the
load resistor.
63
RB1
VEE
Vi
BC558A
R1
RB
→ Ii
source
LED
4N32
V1
Load
LED
Light
Output
Io↓
Vo
RL
Fig.4.9 Circuit diagram of proposed hybrid inverter.
4.4.2 Definition of electrical and optical logic level values
When
the
optical
input
Ii
(current
through
source
LED)
corresponding to logic HIGH is applied to the phototransistor, the
phototransistor is ON and most of the current from the current source
flows through it and very small negligible current flows through the Load
LED. This small current flowing through Load LED does not produce any
light. The output voltage V o across the load resistor R L is also very small.
Thus, a sufficiently large current flowing through source LED produces no
light output through the load
LED (optical logic LOW) and the output
voltage (V o ) across the resistor R L is also small (electrical logic LOW).
From the LED characteristics shown in Fig.4.2, it may be seen that a
forward current of 10mA flowing through the LED produces acceptable
light output (10mW). Hence, a forward current (I F ) of 10mA has been
taken as optical logic HIGH. Further, when a forward current (I F ) through
source LED is 0mA, there is no light from the source LED and the
phototransistor is cutoff. In this case, the entire current from the current
source flows through the Load LED producing acceptable light intensity
corresponding to optical logic HIGH. For the optical logic to be correct, it
is required that the output optical logic HIGH and the input optical logic
64
HIGH should be almost the same. This condition also decides the value of
current supplied by the current source and hence it is fixed at 10mA.
The application of an electrical voltage (V i ) of value 5V through a
series base resistor (R B1 ) of value 200kΩ is found to keep the
phototransistor in saturation, diverting almost the entire source current
of 10mA flowing through it. This ensures that, almost negligible amount
of current flows through the Load LED, giving rise to no light output thus
no output voltage. Hence, an electrical logic HIGH corresponding to 5V,
produces optical logic LOW (no light) and electrical logic LOW (no output
voltage). When there is no input voltage
applied i.e., V i =0V, the
phototransistor is in the cutoff region, the entire current of the current
source flows through Load LED, giving rise to light output corresponding
to I o of 10mA (optical logic HIGH) and an output voltage V o corresponding
to about 5V (electrical logic HIGH). Thus, an input electrical logic LOW
produces an optical logic HIGH and an electrical logic HIGH. Table4.2
summarizes the electrical and optical logic levels.
Table4.2 Definition of Electrical and Optical Input-Output logic levels
LOGIC LEVELS
INPUT
OUTPUT
Electrical logic LOW
0V
0V
Electrical logic HIGH
5V
5V
0mA/0mW
0mA/0mW
10mA/10mW
10mA/10mW
Optical logic LOW
(current through LED/LED
output power)
Optical logic HIGH
(current through LED/LED
output power)
To find suitable value of supply voltage (V EE ) and other components
for the current source, the hybrid inverter circuit has been constructed
and its performance has been measured as described below.
65
4.4.3 Experimental results
In order to verify the functionality, the proposed hybrid inverter
circuit of Fig.4.9 is implemented with a current source of 10mA. The
collector of BC558A transistor behaves as current source, when
connected to a power supply. To generate 10mA of current through the
current source, a supply voltage of 6.2V with a base resistance (R B ) of
87KΩ is used. The voltage drop across the source LED/Load LED is
around 1.15V for producing a current of 10mA. The value of resistor R 1 is
selected as 386Ω to provide an input current I i of 10mA through source
LED. To produce electrical logic HIGH corresponding to a voltage of 5V, a
series load resistor R L of value 500Ω is added to the Load LED. This
circuit thus satisfies the conditions that input logic levels and output logic
levels are almost the same and is shown in Fig.4.10. The performance of
this circuit for different electrical/optical input logic conditions is shown
in Table4.3.
RB1
200KΩ
VEE
Vi
R1
→ Ii
386Ω
source
LED
V1
Current
Source
4N32
Load
LED
Io↓
RL
RB
87KΩ
Light
Output
Vo
500Ω
Fig.4.10 Circuit diagram of hybrid inverter with component values.
Table4.3 Input-Output response of a hybrid inverter
Electrical input V i (V)
Electrical output
V o (V)
Optical output I o (mA)
0
4.8
9.6
5
0
0
Optical input I i (mA)
Electrical output
V o (V)
Optical output I o (mA)
0
4.8
9.6
10
0
0
66
4.4.4 Definition of tolerable electrical and optical input-output logic
levels and noise margins
In order to obtain the variations in the logic levels that can be
tolerated by the inverter circuit, electrical input voltage V i and optical
input I i (source LED current) are varied from 0V to 5V and 0mA to 10mA
respectively and the corresponding electrical and optical output values
are measured and transfer characteristics are plotted. These electrical
and optical transfer characteristics are shown in Fig.4.11 and Fig.4.12.
Fig.4.11 Voltage Transfer Characteristics (VTC) of a hybrid inverter.
From the Fig.4.11, it may be seen that when the electrical input
voltage V i is 0V, the electrical output voltage is 4.8V and optical output I o
(current through Load LED) is 9.6mA. When the electrical input voltage V i
is varied from 0V to 0.65V, the corresponding electrical output voltage V o
varies from 4.8V to 4.4V and optical output I o varies from 9.6mA to
9.2mA. These output variations are relatively small and perhaps tolerable
in cascadable logic circuits. Hence, the maximum logic LOW level input
voltage is fixed at 0.65V, as the phototransistor starts conducting if the
input voltage is greater than or equal to 0.7V. Consider the other extreme
case of input i.e., electrical logic HIGH input. When V i is 5V, electrical
67
output voltage is 0V and optical output I o (current through Load LED) is
0mA. From the experimental results obtained, it is found that when the
input voltage is varied between 0.7V and 5V, the electrical and optical
output variations are relatively small (electrical output is 0.1V and optical
output is 0.7mA). From the above discussion and experimental results
obtained, the tolerable electrical input-output logic levels and noise
margins are defined and are given in Table 4.4, where, V IL
is the
maximum input voltage that will be recognized as tolerable LOW input
logic level, V OH is the minimum output voltage that will be recognized as
tolerable HIGH output logic level and V IH is the minimum input voltage
that will be recognized as tolerable HIGH input logic level, V OL is the
maximum output voltage that will be recognized as tolerable LOW output
logic level, NM L is the is the electrical low noise margin and NM H is the is
the electrical high noise margin.
Fig.4.12 Current Transfer Characteristics (CTC) of a hybrid inverter.
From the Fig.4.12, it may be noted that that when optical input I i
(current through source LED) is 0mA (no light input), the optical output I o
(current through Load LED) is 9.6mA and the electrical output voltage is
4.8V. When the optical input I i is varied from 0mA to 4.5mA, it is found
68
that the electrical output voltage V o varies from 4.8V to 4.4V and optical
output I o varies from 9.6mA to 9.2mA. Consider the other extreme case of
input i.e., optical logic HIGH input. When I i is 10mA, the output of the
inverter is LOW i.e., I o is 0mA and V o is 0V. From the experimental
results obtained, it is found that when I i is varied from 6mA to 10mA, the
electrical and optical output variations are relatively small (electrical
output is 0.1V and optical output is 0.7mA). From the above discussion
and experimental results obtained, the tolerable optical input-output logic
levels and noise margins are defined and are given in Table 4.4, where, I IL
is the maximum input current flowing through source LED that will be
recognized as tolerable LOW input logic level, I OH is the minimum output
current flowing through Load LED that will be recognized as tolerable
HIGH output logic level and I IH is the minimum input current
flowing
through source LED that will be recognized as tolerable HIGH input logic
level, I OL is the maximum output current flowing through Load LED that
will be recognized as tolerable LOW output logic level, ONM L is the is the
optical low noise margin and ONM H is the is the optical high noise
margin.
Table4.4 Tolerable Electrical and Optical Input-Output logic levels and
noise margins hybrid inverter.
Electrical low
noise margin (V)
Electrical high
noise margin (V)
NM L = V IL - V OL
0.55
NM H = V OH - V IH
3.4
I OH (mA)
Optical low
noise margin
(mA)
ONM L = I IL - I OL
Optical high
noise margin
(mA)
ONM H = I OH - I IH
9.2mA
3.5
3.2
Tolerable electrical logic levels
V IL (V)
0.65V
V IH (V)
0.7V
V OL (V)
0.1V
V OH (V)
4.4V
Tolerable optical logic levels
I IL (mA)
I IH (mA)
4.5mA
6mA
I OL
(mA)
0.7mA
Computer aided circuit analysis provides additional information
about the circuit performance that is some times difficult to obtain with
laboratory prototype measurements. Hence, to evaluate the hybrid
inverter circuit performance under varied conditions (the variations in
69
circuit elements), the proposed hybrid inverter circuit is simulated using
OrCAD CAPTURE circuit simulation tool. The simulation performance of
the hybrid inverter is discussed in the following section.
4.4.5 Bias point analysis
In order to verify the functionality of a logic gate, the hybrid inverter
circuit of Fig.4.10 is simulated using bias point analysis procedure
explained in APPENDIX-A-1.4.1 with a current source of 10mA. The
simulation results of the circuit for different input logic conditions are
summarized in Table4.5. From the Table4.5, It may be seen that for all
input logic conditions, the simulated output values are within the defined
logic values. It is also found that the simulation results are in good
Table4.5 Summary of simulation results of a hybrid inverter
Electrical input V i (V)
Electrical output V o (V)
Optical output I o (mA)
0
4.8
9.6
5
0
0
Optical input I i (mA)
Electrical output V o (V)
Optical output I o (mA)
0
4.8
9.6
10
0
0
agreement with the experimental values given in Table4.3.
4.4.6 Transfer characteristics
The DC sweep analysis causes to sweep a source (voltage or
current), through a range of values. The electrical input voltage is swept
from 0V to 5V and its effect on the electrical optical output logic levels is
studied using the DC sweep analysis and the corresponding simulation
results are shown in Fig.4.13 along with tolerable electrical logic levels
and noise margins. Similarly, the source LED current (I F ) is varied by
sweeping the voltage source (V 1 ) in the hybrid inverter circuit and its
effect on electrical and optical output is also studied using the DC sweep
analysis procedure explained in APPENDIX-A-1.4.2. The corresponding
70
simulation results are shown in Fig.4.14 along with tolerable optical logic
levels and noise margins.
5.0V
VOH = 4.578V
4.0V
NML = VIL – VOL = 0.384V
NMH = VOH – VIH = 3.778V
3.0V
2.0V
1.0V
VOL = 0.211V
Vo
0V
0V
0.5V
1.0V
1.5V
2.0V
2.5V
3.0V
3.5V
Vi
VIL = 0.595V
VIH = 0.8V
Fig.4.13 Simulated VTC of hybrid inverter.
4.0V
4.5V
5.0V
71
10mA
IOH = 9.374
8mA
6mA
ONML = IIL – IOL = 3.812mA
ONMH = IOH – IIH =3.174mA
4mA
2mA
IOL= 0.885mA
Io
0A
0
0.01
0.2
1.2
2.4
3.7
4.9
6.2
7.4
8.7
10
Ii (mA)
IIL = 4.697mA
IIH = 6.2mA
Fig.4.14 Simulated CTC of hybrid inverter.
4.4.7 Transient response
To calculate the minimum input pulse width that can be applied for
obtaining undistorted output response, the input pulse width (PW) is
varied in steps and the output response of the hybrid inverter is obtained
using transient response analysis procedure explained in APPENDIX-A1.4.3. The transient response analysis causes the response of the circuit
to be calculated from TIME = 0 to a specified time. Pulse source is used
for transient analysis of the hybrid inverter. The general form of pulse
source is PULSE (V 1 V 2 t d t r t f PW PER), where, V 1 and V 2 must be
specified by the user and can be either voltages and currents, t d is delay
time, t r is rise time, t f is fall time, PW is pulse width and PER is period.
The pulse width of electrical input voltage (V i ) of hybrid inverter is varied
from 10ms to 1µs and the corresponding output response is shown from
Fig.4.15 to Fig.4.17.
72
Vi
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
Io
10mA
5mA
0A
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.15 Transient response of hybrid inverter with electrical input
PULSE (0V 5V 0ns 10ns 10ns 10ms 20ms).
Vi
5.0V
2.5V
Vo
0V
5.0V
2.5V
Io
0V
10mA
5mA
0A
0s
5µs
10µs
15µs
20µs
25µs
30µs
35µs
40µs
Time
Fig.4.16 Transient response of hybrid inverter with electrical input
PULSE (0V 5V 0ns 10ns 10ns 10µs 20µs).
73
Vi
5.0V
2.5V
0V
5.0V
Vo
4.3V
2.5V
0V
10mA
Io
8.6mA
5mA
0A
0s
0.5µs
1.0µs
1.5µs
2.0µs
2.5µs
3.0µs
3.5µs
4.0µs
Time
Fig.4.17 Transient response of hybrid inverter with electrical input
PULSE (0V 5V 0ns 10ns 10ns 1µs 2µs).
It is observed that the output logic levels are with in the defined
logic levels as long as the electrical input pulse width is greater than
1.4µs. Hence, the minimum electrical input pulse width that can be
applied to the inverter is 1.4µs. Similarly, for optical input the minimum
pulse width is observed at 1.6us and a typical case is shown in Fig.4.20.
74
Ii
20mA
10mA
0A
Io
10mA
5mA
0A
Vo
5.0V
2.5V
0V
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.18 Transient response of hybrid inverter with optical input
PULSE (0mA 10mA 0ns 10ns 10ns 10ms 20ms).
Ii
20mA
10mA
0A
Io
10mA
5mA
0A
Vo
5.0V
2.5V
0V
0s
5µs
10µs
15µs
20µs
25µs
30µs
35µs
40µs
Time
Fig.4.19 Transient response of hybrid inverter with optical input
PULSE(0mA 10mA 0ns 10ns 10ns 10µs 20µs).
75
Ii
20mA
10mA
Io
0A
10mA
5mA
Vo
0A
5.0V
2.5V
0V
0s
0.5µs
1.0µs
1.5µs
2.0µs
2.5µs
3.0µs
3.5µs
4.0µs
Time
Fig.4.20 Transient response of hybrid inverter with optical input
PULSE (0mA 10mA 0ns 10ns 10ns 1µs 2µs).
In the proposed hybrid inverter circuit, the input and output logic
levels are almost the same and are within the defined logic levels. Hence,
it can be used for building cascadable hybrid logic circuits. By modifying
the hybrid inverter circuit, the universal hybrid NOR and hybrid NAND
logic gates have been constructed and discussed in following sections.
4.5 UNIVERSAL HYBRID NOR GATE
Circuit diagram of hybrid NOR gate, its principle of operation,
experimental results and the transient response have been discussed in
the following sections.
4.5.1 Circuit diagram of hybrid NOR gate
Hybrid NOR gate has been implemented by modifying the hybrid
inverter
circuit
by
incorporating
another
parallel
branch
of
phototransistor (PT2) as shown in Fig.4.21. The hybrid NOR gate consists
of two phototransistors (PT1 and PT2) which are connected in parallel
with a load consisting of a Load LED to provide optical output and a
series
resistor
RL
across
which
electrical
output
is
taken.
The
phototransistors will be used as switches, which can be operated with
either electrical or optical input signals. The
input to the photo
76
transistors is either electrical voltage applied to the base or the light
generated due to the current flowing through the source LED and coupled
to the phototransistors. The source LED and the phototransistor are
obtained using 4N32 optocoupler. The Load LED is also obtained from
another 4N32 optocoupler, making sure that source LED and Load LED
are identical. The current source is implemented using BC558A
transistor.
In this circuit, V i1 and V i2 are the electrical inputs and I i1 and I i2 are
the optical inputs (current through source LED’s). V D1 and V D2 are the
supply voltages of source LED’s. V o is the electrical output and I o (current
through Load LED) is the optical output.
VEE
Current
Source
87KΩ
I =10mA
VD1
386Ω
Load
LED
VD2
Ii1
386Ω
Ii2
source
LED
source
LED
VO
PT1
PT2
Io
500 Ω
200KΩ
Vi1
Light
Output
RL
200KΩ
Vi2
Fig.4.21 Circuit diagram of Hybrid NOR gate.
4.5.2 Principle of operation
When both the electrical inputs V i1 and V i2 to the hybrid NOR gate
are at logic LOW, both the phototransistors does not conduct and most of
the current from the current source flows through the Load LED and load
resistance R L , producing a sufficiently large light intensity corresponding
to optical logic HIGH. The output voltage V o across the load resistor R L is
77
also high corresponding to electrical logic HIGH. Thus, when electrical
logic LOW corresponding to 0V are applied to both the inputs of hybrid
NOR gate, it produces both electrical HIGH and optical HIGH. Similar is
the case with the optical logic LOW inputs.
When the electrical inputs, either V i1 or V i2 or both are at logic
HIGH, either one of the phototransistors or both will be conducting. In
this case, almost the entire current from the current source flows through
the phototransistor(s). This ensures that almost zero or negligible current
flows through the Load LED and series load resistance R L , giving rise to
no electrical output and no optical output. Thus, the application of
electrical HIGH corresponding to 5V to either one or both of the inputs of
the hybrid NOR gate produces both electrical LOW and optical LOW
outputs. Similar is the case with the application of optical logic HIGH
inputs to the hybrid NOR gate.
4.5.3 Experimental results
In order to verify the functionality of the hybrid NOR gate, the
experiment is performed with different electrical and optical logic
conditions. The performance of the hybrid NOR gate for different input
logic conditions is shown in Table4.6.
Table4.6 Input-Output response of hybrid NOR gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
4.8
0
0
0
Electrical output
V o (V)
9.6
0
0
0
Optical output
I o (mA)
0
0
10
10
0
10
0
10
4.8
0
0
0
9.6
0
0
0
Optical inputs
I i1 (mA)
I i2 (mA)
78
From Table4.6, it may be noted that when the electrical inputs
either V i1 or V i2 or both are logic HIGH (5V), it produces an electrical
output (V o ) of 0V and optical output (I o ) of 0mA. These output values
corresponds to electrical logic LOW and optical logic LOW levels. When
both the electrical inputs V i1 and V i2 are logic LOW (0V), it produces
electrical output (V o ) of 4.8V and optical output (I o ) of 9.6mA. These
output values correspond to electrical logic HIGH and optical logic HIGH
levels.
Similarly, when the optical inputs either I i1 or I i2 or both are logic
HIGH (10mA), it produces an electrical output (V o ) of 0V and optical
output (I o ) of 0mA which corresponds to electrical logic LOW and optical
logic LOW. When both the optical inputs I i1 and I i2 are logic LOW (0mA), it
produces electrical output (V o ) of 4.8V and optical output (I o ) of 9.6mA,
which corresponds to electrical logic HIGH and optical logic HIGH. From
these experimental results, it may be noted that for all electrical and
optical input logic combinations, the electrical and optical output
measured values are within the defined logic levels. Thus, the hybrid NOR
logic function is demonstrated.
4.5.4 Transient response
To calculate the minimum input pulse width that can be applied,
the input pulse width is varied and the transient response of the hybrid
NOR
has been obtained. The pulse width of
one
electrical input is
varied from 5µs to 1µs by keeping the other input pulse width constant at
10µs and the output response for a typical cases are given in Fig.4.22 &
Fig.4.23 .
It is observed that the output response is within the tolerable logic
levels as long as the electrical input pulse width is greater than 1.6µs.
Hence, the minimum electrical input pulse width that can be applied to
the hybrid NOR is 1.6µs. Similarly, for optical response the minimum
input pulse width is observed at 1.8µs.
79
5.0V
Vi1
2.5V
0V
Vi2
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
10mA
Io
5mA
0A
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.22 Transient response of hybrid NOR gate for electrical inputs.
Vi1
5.0V
2.5V
0V
5.0V
Vi2
2.5V
0V
5.0V
Vo
4.3V
2.5V
0V
10mA
Io
8.6mA
5mA
0A
0s
2µs
4µs
6µs
8µs
10µs
12µs
14µs
16µs
18µs
20µs
Time
Fig.4.23 Transient response of hybrid NOR gate for electrical
4.6 UNIVERSAL HYBRID NAND GATE
Circuit diagram of hybrid NAND gate, its principle of operation,
experimental results and the transient response have been discussed in
the following section.
80
4.6.1 Circuit diagram of hybrid NAND gate
Hybrid NAND gate has been implemented by modifying the hybrid
inverter circuit by incorporating an additional series phototransistor (PT2)
as shown in Fig.4.24. The load consists of a Load LED to provide optical
output and a series resistance R L across which the electrical output is
taken. The phototransistors are used as switches, which can be operated
with either electrical or optical input signals. The
input to the
phototransistors is either electrical voltage applied to the base or the light
generated due to the current flowing through the source LED and coupled
to the phototransistors. The source LED and the phototransistor are
obtained using 4N32 optocoupler. The Load LED is also obtained from
another 4N32 optocoupler, making sure that source LED and Load LED
are identical. The current source is implemented using BC558A
transistor.
VEE
VD1
386Ω
87KΩ
 Ii1
Current
Source
 I=10mA
source
LED
PT1
200KΩ
Load
LED
Vi1
Light
Output
VD2
386Ω
 Ii2
VO
source
LED
IO 
PT2
500Ω
RL
200KΩ
Vi2
Fig.4.24 Circuit diagram of hybrid NAND gate.
In this circuit, V i1 and V i2 are the electrical inputs and I i1 and I i2
are the optical inputs (current through source LED’s). V o is the electrical
output and I o (current through Load LED) is the optical output.
81
4.6.2 Principle of operation
When both electrical or optical inputs to the hybrid NAND gate are
at logic HIGH, both the phototransistors will conduct and most of the
current from the current source flows through the phototransistors. This
ensures that almost negligible amount of current flows through the Load
LED giving rise to optical LOW and electrical LOW as outputs. Thus, the
application of either electrical or optical logic HIGH to both the inputs of
hybrid NAND gate produces electrical LOW and optical LOW as outputs.
When either one or both inputs of the hybrid NAND gates are at
either electrical or optical LOW logic, the phototransistor(s) does not
conduct and most of the current from the current source flows through
the Load LED, producing sufficiently large light intensity corresponding to
optical logic HIGH. The output voltage V o across the load resistance R L is
also high corresponding to electrical logic HIGH. Thus, either electrical or
optical LOW are applied to either one or both of the inputs of the hybrid
NAND gate, produces both electrical HIGH and optical HIGH outputs.
4.6.3 Experimental results
In order to verify the functionality of the hybrid NAND gate, the
experiment is performed with different electrical and optical logic
conditions. The performance of the hybrid NAND gate for different input
logic conditions is shown in Table4.7.
Table4.7 Input-Output response of hybrid NAND gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
Optical inputs
I i1 (mA)
I i2 (mA)
0
0
0
10
10
0
10
10
4.8
4.8
4.8
0
Electrical output
V o (V)
4.8
4.8
4.8
0
9.6
9.6
9.6
0
Optical output
I o (mA)
9.6
9.6
9.6
0
82
From the Table4.7, it may be noted that, when the electrical inputs
either V i1 or V i2 or both are logic LOW, it produces both electrical HIGH
and optical HIGH as outputs. When both the electrical inputs V i1 and V i2
are HIGH, it produces electrical LOW and optical LOW as outputs.
Similarly, when the Optical inputs either I i1 or I i2 or both are LOW, it
produces both electrical HIGH and optical HIGH as outputs. When both
the optical inputs I i1 and I i2 are HIGH, it produces electrical LOW and
optical LOW as outputs. From Table4.7, it may be seen that for all input
conditions, the output values are within the defined logic values. Thus,
the hybrid NAND logic function is demonstrated.
4.6.4 Transient response
To calculate the minimum input pulse width that can be applied for
obtaining undistorted output response, the input pulse width) is varied
and the output response of the hybrid NAND has been measured. The
pulse width of
the electrical input signals are varied from 10ms to 1µs
and the output response for a typical case is given in Fig.4.25.
Vi1
5.0V
2.5V
0V
Vi2
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
Io
10mA
5mA
0A
0s
10µs
20µs
30µs
40µs
50µs
60µs
70µs
80µs
Time
Fig.4.25 Transient response of hybrid NAND gate for electrical inputs.
83
It is observed that the output response is within the defined logic
levels as long as the electrical input pulse width is greater than 1.7µs.
Hence, the minimum input pulse width that can be applied to the hybrid
NAND is 1.7µs. The optical response for a typical case is given in Fig.4.26
and the minimum optical pulse width is observed at 1.5µs.
20mA
Ii1
10mA
0A
Ii2
20mA
10mA
0A
10mA
Io
8.6 mA
5mA
0A
5.0V
Vo
4.3 V
2.5V
0V
0s
2µs
4µs
6µs
8µs
10µs
12µs
14µs
16µs
18µs
20µs
Time
Fig.4.26 Transient response of hybrid NAND gates for optical inputs.
4.6.5 3-input hybrid NAND gate
The circuit diagram of 3-input hybrid NAND gate is shown in
Fig.4.27. This 3-input hybrid NAND gate is obtained from 2-input hybrid
NAND gate by incorporating an additional phototransistor (PT3) in series
with the PT1 and PT2. The phototransistors are used as switches, which
can be operated with either electrical or optical input signals. The input
to the phototransistors is either electrical voltage applied to the base or
the light generated due to the current flowing through the source LED
and coupled to the phototransistors. The load consists of a Load LED to
provide optical output and a series resistance R L across which the
electrical output is taken. The current source is implemented using
BC558A transistor. In this circuit, V i1, V i2 and V i3 are the electrical inputs
84
and I i1 , I i2 and I i3 are the optical inputs (current through source LED’s).
V D1, V D2 and V D3 are the supply voltages of source LED’s. V o is the
electrical output and I o (current through Load LED) is the optical output.
VE E
VD1
386Ω
Current
Source
↓Ii1
source
LED1
RB
87KΩ
Load
LED
PT1
↓Io
200KΩ
VD2
RB1
Vi1
386Ω
Vo
RL
↓Ii2
source
LED2
200KΩ
500Ω
PT2
RB2
Vi2
VD3
386Ω
↓Ii3
source
LED3
200KΩ
PT3
RB3
Vi3
Fig.4.27 Circuit diagram of 3-input hybrid NAND gate.
To verify the functionality of the 3-input NAND, the circuit is
simulated and the transient responses are shown from Fig.4.28 to
Fig.4.30. From the transient response, it may be noted that the hybrid
NAND gate produces electrical LOW and optical LOW at the output if
and only if all the three electrical or optical inputs are HIGH, otherwise it
produces electrical HIGH and optical HIGH. Thus, the functionality of 3input hybrid NAND gate is demonstrated. Fig.4.28 shows the transient
response of the hybrid NAND for all electrical inputs (V i1 ,V i2 ,V i3 ).
Similarly, Fig.4.29 gives the transient response of the hybrid NAND for all
85
optical inputs (I i1 ,I i2 ,I i3 ). Further, it may be noted from the Fig.4.30 that
one can also apply optical (I i1 ) and electrical (V i2 ,V i3 ) input combinations.
5.0V
Vi1
2.5V
0V
Vi2
5.0V
2.5V
0V
Vi3
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
Io
10mA
5mA
0A
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.28 Transient response of 3-input NAND gate for electrical inputs.
Ii1
20mA
10mA
0A
Ii 2
20mA
10mA
0A
Ii 3
20mA
10mA
0A
10mA
Io
5mA
0A
Vo
5.0V
2.5V
0V
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.29 Transient response of 3-input NAND gate for optical inputs.
86
20mA
Ii
10mA
0A
Vi2
5.0V
2.5V
0V
Vi3
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
Io
10mA
5mA
0A
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
Time
Fig.4.30 Transient response of 3-input NAND gate for optical (Ii1) and
electrical (Vi2, Vi3) input combinations.
4.7 HYBRID OR GATE
Two approaches have been discussed for implementing hybrid OR
gate. In the first approach, the hybrid OR gate is implemented by
cascading the universal hybrid NOR and hybrid inverter. In the second
approach, the hybrid OR is implemented using alternate circuit topology,
where a voltage source is used instead of a current source as the source
of power for the circuit. In the following sections, both the approaches
have been discussed.
4.7.1 Implementation of hybrid OR using universal hybrid NOR gate
Hybrid OR logic gate has been implemented by cascading a
universal hybrid NOR circuit and a hybrid inverter circuit i.e., the output
of the NOR circuit is connected to the input of the inverter as shown in
Fig.4.31. Either the electrical output V o1 or the optical output (LED
output) of the NOR gate can be applied to the input of the hybrid inverter.
In this circuit, the electrical output V o1 of the NOR gate is coupled to the
input of the inverter.
87
VEE
87KΩ
VEE
Current
Source
Current
Source
87KΩ
↓I =10mA
VD1
386Ω
source
LED
↓Ii2
386Ω
PT1
200KΩ
LED
VD2
↓Ii1
↓I =10mA
PT3
source
LED
200KΩ
PT2
200KΩ
Load
LED
Light
Output
Vo1
Io1 ↓
RL1
500Ω
Io ↓
Vo1
RL
500Ω
Vi1
Vi2
hybrid NOR gate
hybrid inverter
Fig.4.31 Implementation of hybrid OR gate using universal NOR gate.
To verify the hybrid OR logic function, the experiment is performed
for different input logic conditions. Table4.8 shows the input-output
response of hybrid OR gate. From Table4.8, it may be seen that the
output is high, if one of the input or both the inputs are high. Thus, the
hybrid OR logic function is demonstrated using universal hybrid NOR
gate and hybrid NOT gate.
Table4.8 Input-Output response of hybrid OR gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
0
4.8
4.8
4.8
Electrical output
V o (V)
0
9.6
9.6
9.6
Optical output
I o (mA)
0
0
10
10
0
10
0
10
0
4.8
4.8
4.8
0
9.6
9.6
9.6
Optical inputs
I i1 (mA)
I i2 (mA)
88
4.7.1.1 Transient response
To calculate the minimum input pulse width that can be applied,
the pulse width of the electrical input voltage (V i ) is varied from 10ms to
1µs and the corresponding output response is given in Fig.4.32. It is
observed that the output logic levels are with in the defined logic levels as
long as the electrical input pulse width is greater than 1.3µs. Hence, the
minimum input pulse width that can be applied to the hybrid OR gate is
1.3µs. It is also observe that the output logic levels are satisfied for all the
input logic conditions.
Vi1
5.0V
2.5V
0V
Vi2
5.0V
2.5V
0V
Vo
5.0V
2.5V
0V
Io
10mA
5mA
0A
0s
5µs
10µs
15µs
20µs
25µs
30µs
35µs
40µs
Time
Fig.4.32 Transient response of hybrid OR gate for electrical inputs.
Similarly the pulse width of the optical input (I i ) is varied from
10ms to 1µs and the corresponding output response is given in Fig.4.33.
It is observed that the optical output logic levels are with in the defined
logic levels as long as the electrical input pulse width is greater than
1.4µs. Hence, the minimum input pulse width that can be applied to the
hybrid OR gate is 1.4µs.
89
Ii1
20mA
10mA
0A
Ii 2
20mA
10mA
0A
Io
10mA
5mA
0A
5.0V
Vo
2.5V
0V
0s
5µs
10µs
15µs
20µs
25µs
30µs
35µs
40µs
45µs
50µs
55µs
60µs
Time
Fig.4.33 Transient response of hybrid OR gate for optical inputs.
4.7.2 Implementation of hybrid OR gate using alternate circuit
topology
In the previous section, implementation of hybrid OR gate using
universal hybrid NOR gate has been explained. In this section,
implementation of hybrid OR gate using a alternate circuit topology is
explained.
4.7.2.1 Principle of operation
The circuit diagram of the hybrid OR gate is shown in Fig.4.34. It
consists of two phototransistors PT1 and PT2 which are paralleled at their
collector and emitter terminals. The phototransistors are used as switches
which can be operated either with electrical or optical input signals with
proper biasing of the base terminal. The load consists of an LED to
provide optical output and a series resistor R L across which electrical
output is taken. In this circuit, V i1 and V i2 are the electrical inputs and I i1
and I i2 (current through source LED’s) are the optical inputs. V o is the
electrical output and I o is the optical output (current through Load LED)
of the gate.
90
VCC = 5V
VD2
VD1
386Ω
Ii 2
↓
I i1
↓
source
LED1
200KΩ
source
LED2
PT2
PT1
200KΩ
RB1
Load
LED
Vi1
I o↓
RL
386Ω
RB2
Vi2
Vo
325Ω
Fig.4.34 Circuit diagram of hybrid OR gate using alternate circuit
topology.
When the electrical inputs either V i1 or V i2 or both are HIGH, it
produces both electrical HIGH and optical HIGH as outputs. When both
the electrical inputs V i1 and V i2 are LOW, it produces electrical LOW and
optical LOW as outputs. When the Optical inputs either I i1 or I i2 or both
are HIGH, it produces both electrical HIGH and optical HIGH as outputs.
When both the optical inputs I i1 and I i2 are LOW, it produces electrical
LOW and optical LOW as outputs.
The hybrid OR circuit is implemented using phototransistors and
LEDs from optocouplers. It is found from the characteristics that a
current of 10mA flowing through the LED produces acceptable light
intensity. The voltage drop across the LED is around 1.15V for producing
a current of 10mA. It is found from the characteristics that a saturation
collector current of 10mA flows through the phototransistor for an LED
current of 10mA in the optocoupler. By adjusting the load resistor R L , a
load current of 10mA is obtained which makes the phototransistor to get
into the linear region. The value of V CE under this condition is found to be
91
0.6V. Therefore, for the phototransistor to support 10mA of collector
current, a V CE of 0.6V is needed. For a supply voltage of 5V, collector
emitter voltage of 0.6V for phototransistor, and a voltage drop of 1.15V
across Load LED, the value of load resistor R L to provide the load current
of 10mA, is found to be 325Ω. Note that LEDs from identical optocouplers
are used at the input (source LED’s) as well as at the output (Load LED).
4.7.2.2 Experimental results
To verify the hybrid OR logic function, the experiment is
performed for the defined logic levels. Table4.9 shows the input-output
response of hybrid OR gate. From Table4.9, it may be seen that for all
input logic conditions, the output values measured are within the defined
logic values. Thus, the hybrid OR logic function is demonstrated.
Table4.9 Input-Output response of hybrid OR gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
0
3.15
3.15
3.15
Electrical output
V o (V)
0
9.6
9.6
9.6
Optical output
I o (mA)
0
0
10
10
0
10
0
10
0
3.15
3.15
3.15
0
9.6
9.6
9.6
Optical inputs
I i1 (mA)
I i2 (mA)
4.7.2.3 Discussion of results
From the Table4.9, it is clear that the optical output logic values
obtained are almost the same as the optical input logic values and these
values do not provide any problem in driving the stages that follow.
The electrical output corresponding to logic HIGH is only 3.15V
which is not within the defined logic HIGH level. This value is not enough
to drive the next stage. To use the hybrid OR gate in cascadable systems,
92
the electrical output corresponding to logic HIGH is to be boosted to 5V.
This can be achieved by incorporating two stages of inversion using
transistors Q1 and Q2 in the Hybrid OR circuit of Fig.4.34. The modified
hybrid OR circuit is shown in Fig.4.35. The performance of this hybrid OR
gate for different input logic conditions is shown in Table4.10. From the
Table4.10, it may be seen that the electrical output level corresponding to
logic HIGH is the same as that of electrical input HIGH i.e., 5V. But this
modified hybrid OR gate is not suitable to use in building larger
cascadable hybrid systems because of additional buffer stage requirement
to drive the stages that follow.
VCC = 5V
VD2
VD1
386Ω
386 Ω
Ii2
Ii1
source
LED2
source
LED1
PT2
PT1
200KΩ
200KΩ
Load
LED
Vi2
5V
Vi1
Io
Vo
R
330Ω
220Ω
Vo
Q2
Q1
330Ω
325 Ω
Fig.4.35 Circuit diagram of modified hybrid OR gate.
93
Table4.10 Input-Output response of modified hybrid OR gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
0
5
5
5
Electrical output
V o (V)
0
9.6
9.6
9.6
Optical output
I o (mA)
0
0
10
10
0
10
0
10
0
5
5
5
0
9.6
9.6
9.6
Optical inputs
I i1 (mA)
I i2 (mA)
4.7.3 Comparison of the two approaches
Implementation of hybrid OR gate using first approach i.e., using
universal hybrid NOR and inverter needs three phototransistors and two
electrical transistors. Implementation of hybrid OR gate using alternate
circuit topology requires only two phototransistors and two electrical
transistors.
The
first
approach
is
preferable
from
the
point
of
cascadability than the second one.
4.8 HYBRID AND GATE
Two approaches have been discussed for implementing hybrid AND
gate. In the first approach, the hybrid AND gate is implemented by
cascading the universal hybrid NAND gate and hybrid inverter. In the
second approach, the hybrid AND gate is implemented using alternate
circuit topology, where a voltage source is used instead of a current
source as the source of power for the circuit. In the following sections,
both the approaches have been discussed and compared.
4.8.1 Implementation of hybrid AND gate using universal hybrid
NAND gate
Hybrid AND gate can be obtained by cascading a universal hybrid
NAND gate and a hybrid NOT gate i.e., the output of the NAND circuit is
connected to the input of the NOT as shown in Fig.4.36. Either the
94
electrical output V o1 or the optical output (LED output) of the hybrid
NAND gate can be applied to the input of the NOT gate. In this circuit, the
electrical output V o1 of the hybrid NAND gate is coupled to the input of
the NOT gate. To verify the hybrid AND logic function, the experiment is
performed for different input logic conditions. Table4.11 shows the inputoutput response of hybrid AND gate. From the Table4.11, it may be seen
that the output is HIGH, if and only if both the inputs are HIGH. Thus,
the hybrid AND logic function is demonstrated using a universal hybrid
NAND gate and hybrid NOT gate.
VEE
VD1
87KΩ
386Ω Ii1
↓
VEE
Current
Source
↓
source
LED
↓
I = 10mA
PT1
PT3
Load
200KΩ LED
Vi1
Io1
↓
386Ω Ii2
source
LED
I = 10mA
LED
200KΩ
VD2
Current
Source
87KΩ
↓
RL1
Light
output
Vo1
Io ↓
500Ω
VO
RL 500Ω
PT2
200KΩ
Vi2
hybrid NAND gate
hybrid inverter
Fig.4.36 Implementation of hybrid AND using universal NAND gate.
95
Table4.11 Input-Output response of hybrid AND gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
5
5
0
5
0
5
0
0
0
4.8
Electrical output
V o (V)
0
0
0
9.6
Optical output
I o (mA)
0
0
10
10
0
10
0
10
0
0
0
4.8
0
0
0
9.6
Optical inputs
I i1 (mA)
I i2 (mA)
4.8.1.1 Transient response
To calculate the minimum input pulse width that can be applied for
obtaining undistorted output response, the input pulse width (PW) is
varied in steps and the output response of the hybrid AND gate has been
obtained. The pulse width of the electrical input signals is varied from
1ms to 1µs and the output response for a typical case is given in Fig.4.37.
5.0V
Vi1
2.5V
0V
V(Vi2)
5.0V
2.5V
0V
V(Vo)
5.0V
2.5V
0V
Io(mA)
10mA
5mA
0A
0s
10ms
20ms
30ms
40ms
50ms
60ms
70ms
80ms
Time
Fig.4.37 Transient response of hybrid AND gate for electrical inputs.
96
It is observed that the output response is not distorted as long as
the electrical input pulse width is greater than 1.4µs. Hence, the
minimum input pulse width that can be applied to the hybrid AND is
1.4µs. The optical response for a typical case is given in Fig.4.38 and the
minimum optical input pulse width is observed at 1.3µs.
Ii(mA)
20mA
10mA
0A
Ii(mA)
20mA
10mA
0A
Io(mA)
10mA
5mA
0A
V(Vo)
5.0V
2.5V
0V
0s
10ms
20ms
30ms
40ms
50ms
60ms
70ms
80ms
Time
Fig.4.38 Transient response of hybrid AND gate for optical inputs.
4.8.2 Implementation of hybrid AND gate using alternate circuit
topology
In the previous section, realization of hybrid AND gate using
universal hybrid NAND gate has been explained. In this section,
implementation of hybrid AND gate using alternate circuit topology is
explained.
4.8.2.1 Principle of operation
The circuit diagram of the hybrid AND logic gate is shown in
Fig.4.39.The circuit consists of two phototransistors (PT1 and PT2), a LED
and a resistor R L connected in series serve as load to provide optical and
electrical outputs. V i1 and V i2 are the electrical inputs and I i1 and I i2 are
the optical inputs (current through source LED’s) of the logic gate. V o is
97
the electrical output and I o is the optical output (current through Load
LED) of the logic gate.
VCC = 5V
VD1
386Ω
Ii1
source
LED1
PT1
VD2
200KΩ
Vi1
386Ω
Ii2
source
LED2
PT2
200KΩ
Load
LED
Vi2
Io
RL
Vo
R
Fig.4.39 Circuit diagram of hybrid AND gate using alternate circuit topology.
When any of the electrical inputs or both the inputs are LOW, the
AND gate produces an electrical LOW and an optical LOW as a output.
When both the electrical inputs V i1 and V i2 are HIGH, it produces logic
HIGH at electrical and optical output. When the optical inputs either I i1 or
I i2 or both are LOW, it produces both electrical LOW and optical LOW as
outputs. When both the optical inputs I i1 and I i2 are HIGH, it produces
electrical HIGH and optical HIGH as outputs.
The hybrid AND circuit is implemented using phototransistors and
LEDs from optocouplers. It is found from the characteristics that a
current of 10mA flowing through the LED produces acceptable light
intensity. The voltage drop across the Load LED is around 1.15V for
98
producing a current of 10mA. It is found from the characteristics of a
phototransistor that a saturation collector current of more than 10mA
flows through the phototransistor for a LED current of 10mA in the
optocoupler. By adjusting the load resistor R L , a collector current of 10mA
is obtained which makes the phototransistor to get into the linear region.
The value of V CE under this condition is found to be 0.6V. Therefore, for
the phototransistor to support 10mA of collector current, a V CE of 0.6V is
needed. For a supply voltage of 5V, collector emitter voltage of 0.6V for
each phototransistor, and a voltage drop of 1.15V across LED, the value
of load resistor R L to provide the load current of 10mA, is found to be
265Ω.
4.8.2.2 Experimental Results
To verify the hybrid AND logic function, the experiment is
performed for different electrical/optical logic values. Table4.12 shows the
input-output response of hybrid AND gate.
Table4.12 Input-Output response of hybrid AND gate
Electrical inputs
Electrical output
V o (V)
Optical output
I o (mA)
V i1 (V)
V i2 (V)
0
0
0
0
0
5
0
0
5
0
0
0
5
5
2.55
9.6
Electrical output
V o (V)
Optical output
I o (mA)
Optical inputs
I i1 (mA)
I i2 (mA)
0
0
0
0
0
10
0
0
10
0
0
0
10
10
2.55
9.6
99
4.8.2.3 Discussion of results
From the Table4.12, it is clear that the optical output logic values
obtained are almost the same as the optical input logic values and these
values do not create any issues in driving the stages that follow. The
electrical output corresponding to logic HIGH is only 2.55V which is not
within the defined logic HIGH level. This value is not enough to drive the
next stage. The electrical output corresponding to logic HIGH should be
boosted to 5V, in order to use hybrid AND gate in cascadable systems.
This can be achieved by incorporating two stages of inversion using
transistors Q1 and Q2 in the hybrid AND circuit of Fig.4.39. The modified
hybrid AND circuit is shown in Fig.4.40.
VCC = 5V
VD1
386Ω
Ii1
source
LED1
PT1
VD2
200KΩ
386Ω
Vi1
Ii2
source
LED2
PT2
5V
200KΩ
Load
LED
330Ω RL
220Ω
Vi2
Vo
Io
Q1
Q2
320Ω
265Ω
Fig.4.40 Circuit diagram of modified hybrid AND gate.
100
The performance of this hybrid AND gate for different input logic
conditions is shown in Table4.13. From the Table4.13, it may be seen that
the electrical output level corresponding to logic HIGH is same as that of
electrical input HIGH i.e., 5V. But this modified hybrid AND gate is not
suitable to use in building larger cascadable hybrid systems because of
additional buffer stage requirement to drive the stages that follow.
Table4.13 Input-Output response of modified hybrid AND gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
0
0
0
5
0
0
5
0
0
0
5
5
5
9.6
Optical inputs
Electrical output
Optical output
I i1 (mA)
I i2 (mA)
V o (V)
I o (mA)
0
0
0
0
0
10
0
0
10
0
0
0
10
10
5
9.6
4.8.3 Comparison of the two approaches
Implementation of hybrid AND gate using universal hybrid NAND
gate
needs
three
phototransistors
and
two
electrical
transistors.
Implementation of hybrid AND gate using this circuit topology requires
only two phototransistors and two electrical transistors. The first
approach is preferable from the point of cascadability than the second
one.
4.9 HYBRID EX-OR GATE
Circuit diagram of proposed hybrid EX-OR gate, its principle of
operation, experimental results and the transient response have been
discussed in the following section.
4.9.1 Circuit diagram
The EX-OR logic function is described by the following boolean
expression,
A⊕B = A. Β + Α .B
⋅⋅⋅Eq.(4-1)
101
From Eq.(4-1), it may be noted that the hybrid EX-OR gate can be
realized using two hybrid NOT gates, two hybrid AND gates and one
hybrid OR gate. To understand the basic operation, the internal transistor
details of hybrid EX-OR gate is shown in Fig.4.41. Hybrid NOT, AND and
OR gates have already been discussed in detail in the previous sections.
Realization of Eq.(4-1) requires the presence of two input signals (A and
B) and their complements ( Α and Β ). These inputs are either electrical
and/or optical signals. Complement inputs are obtained using hybrid
NOT gates. The phototransistors PT1 and PT2 which are connected in
series will form one hybrid AND gate. Similarly, PT3 and PT4 gives
another hybrid AND gate. The hybrid AND gate has already been
explained in section 4.8.2. The phototransistors PT5 and PT6 which are
connected in parallel will form the hybrid OR gate and is already
discussed in section 4.7.2. The load of the hybrid EX-OR gate consists of
a LED (designated as Load LED in Fig.4.41 to provide optical output I o
(current through Load LED) and a series resistor R L of 440Ω is used
across which electrical output V o is taken.
VCC
A
PT1
Β
PT2
LED1
VCC
PT5
PT6
Load
LED
IO↓
PT3
Α
PT4
B
LED2
Light
Output
VO
RL
Fig.4.41 Simplified circuit diagram of hybrid EX-OR gate.
102
4.9.2 Principle of operation
The operation of the hybrid EX-OR gate can be explained in more
detail by considering the operating modes of the six phototransistors PT1,
PT2, PT3, PT4, PT5 and PT6 in the Fig.4.41. When both the electrical
inputs V i1 and V i2 are same (either LOW-LOW or HIGH-HIGH), the
phototransistors PT5 and PT6 are turned OFF and no current flows
through the Load LED and the EX-OR gate produces both electrical LOW
and optical LOW as outputs. When the electrical inputs V i1 and V i2 are
different (either LOW-HIGH or HIGH-LOW), either PT5 or PT6 are ON and
sufficient current flows through the Load LED and the EX-OR gate
produces electrical HIGH and optical HIGH as outputs. Similarly, when
the optical inputs I i1 and I i2 are same (either LOW-LOW or HIGH-HIGH), it
produces both electrical LOW and optical LOW as outputs. When the
optical inputs I i1 and I i2 are different (either LOW-HIGH or HIGH-LOW), it
produces electrical HIGH and optical HIGH as outputs.
4.9.3 Experimental results
The performance of the hybrid EX-OR gate for different input
logic conditions is shown in Table4.14.
Table4.14 Experimental results of hybrid EX-OR gate
Electrical inputs
Electrical output
Optical output
V i1 (V)
V i2 (V)
V o (V)
I o (mA)
0
0
0
0
0
5
4.3
9.6
5
0
4.3
9.6
5
5
0
0
Optical inputs
Electrical output
Optical output
I i1 (mA)
I i2 (mA)
V o (V)
I o (mA)
0
0
0
0
0
10
4.3
9.6
10
0
4.3
9.6
10
10
0
0
When both the inputs A and B to the EX-OR gate are same (either
logic LOW or logic HIGH), the phototransistors PT5 and PT6 are OFF and
no current flows through the load and the EX-OR gate produces electrical
LOW and optical LOW as outputs. If the inputs A and B are different,
103
either PT5 or PT6 are ON and sufficient current flows through the load
and the EX-OR gate produces both electrical HIGH and optical HIGH as
outputs.
From the Table4.14, it is clear that the optical output logic values
obtained are almost the same as the input logic values. But the electrical
output corresponding to logic HIGH value obtained is only 4.3V which
needs to be boosted to 5V level by incorporating an electrical buffer stage
at the output of the logic gate in order to drive the stages that follow. But
this hybrid EX-OR gate is not suitable to use in building larger cascadable
hybrid systems because of additional buffer stage requirement to drive the
stages that follow. Hence, hybrid EX-OR gate has been realized using
hybrid AND, OR circuit topologies which are explained in 4.8.1 and 4.7.1
sections. The block diagram is shown in Fig.4.42. The transient response
of this hybrid EX-OR gate is discussed in the following section.
A
Vi1
Ii1
EleInp
Output
A
OptInp
EleInp1 Output
EleInp2
OptInp1
OptInp2
AB
EleInp1
EleInp2
Output
OptInp1
OptInp2
HNOT_G1
HAND_G1
HOR_G
Vi2
Ii2
Output
EleInp
OptInp
HNOT_G2
B
EleInp1 Output
EleInp2
OptInp1
OptInp2
AB
HAND_G2
B
Fig.4.42 Block diagram of hybrid EX-OR gate.
A⊕B
104
4.9.4 Transient response
To calculate the minimum input pulse width that can be applied,
the pulse width of one electrical input V i1 is kept constant at 10µs and the
other electrical input V i2 is varied from 5µs to 1µs and the output
response of the hybrid EX-OR has been observed. The output response for
a typical case is given in Fig.4.43. It is observed that the output logic
levels of the hybrid EX-OR gate are within the defined logic levels as long
as the electrical input pulse width is greater than 1.5µs. Hence, the
minimum electrical input pulse width that can be applied to the hybrid
EX-OR gate is 1.5µs.
Vi1
5.0V
2.5V
0V
Vi2
5.0V
2.5V
0V
5.0V
Vo
4.3V
2.5V
0V
10mA
Io
8.6mA
5mA
0A
0s
2µs
4µs
6µs
8µs
10µs
12µs
14µs
16µs
18µs
20µs
Time
Fig.4.43 Transient response of hybrid EX-OR for electrical inputs.
Similarly, the pulse width of one optical input I i1 is kept constant
at 10µs and the other optical input I i2 is varied from 5µs to 1µs and the
output response of the hybrid EX-OR has been observed. The output
response for a typical case is given in Fig.4.43. It is observed that the
output logic levels of the hybrid EX-OR gate within the defined logic levels
as long as the optical input pulse width is greater than 1.7µs.
105
Io1 (mA)
20mA
10mA
0A
Io2 (mA)
20mA
10mA
0A
Io (mA)
10mA
5mA
0A
V o(V)
5.0V
2.5V
0V
0s
10µs
20µs
30µs
40µs
50µs
60µs
70µs
80µs
Time
Fig.4.44 Transient response of hybrid EX-OR for optical inputs.
4.10 COMBINATIONAL HYBRID LOGIC CIRCUITS
Implementation of the hybrid EX-OR gate using hybrid AND, OR
gates which are obtained from universal hybrid gates has indicated that
hybrid optoelectronic logic circuits are cascadable and large hybrid digital
functions can be realized. In continuation of this thought process, it is
further demonstrated that usable and large combinational circuits can be
realized by implementing combinational hybrid circuits namely, hybrid
half adder, hybrid full adder and hybrid 4-bit adder. These combinational
hybrid
circuits
have
been
implemented
using
hierarchical
design
procedure explained in APPENDIX-A-1.6. Creating larger and complex
circuit blocks by instantiating smaller circuit blocks is called hierarchical
design. A design procedure in which one first creates a lowest level
smaller circuit block and then create larger and complex hierarchical
circuit blocks using these lowest-level circuit blocks is called bottom up
design procedure. Bottom up design procedure is used for implementing
the hybrid combinational circuits. These hybrid circuits have been
discussed in the following section.
106
4.10.1 Hybrid Half Adder
Hybrid half adder is a combinational arithmetic logic circuit which
is used to perform addition of two single bits and produces a SUM and a
CARRY. Block diagram of a hybrid half adder that is realized using hybrid
AND, OR gates which are obtained from universal NAND, NOR gates is
shown in Fig.4.45(a) and the complete circuit diagram is shown in
Fig.4.45(b). The two inputs (A and B) to the hybrid half adder are either
electrical or optical and produces both electrical and optical SUM and
CARRY are the outputs. The Boolean expressions for the outputs are
given by,
SUM = A⊕B
⋅⋅⋅Eq.(4-2)
CARRY = A.B
⋅⋅⋅Eq.(4-3)
The SUM is logic HIGH, when A and B are different; and CARRY is
logic HIGH, when both A and B are logic HIGH. The inputs A and B to the
hybrid half adder are either electrical and/or optical signals. The
limitation of half adder is that it does not consider a carry from the
previous addition.
EleInp1
EleInp
A
Output
A
OptInp
EleInp2
Output
OptInp1
AB
EleInp2
Output
OptInp1
SUM= A⊕B
OptInp2
OptInp2
HNOT_G1
EleInp1
HAND_G1
HOR G
EleInp1
EleInp1
EleInp
B
Output
B
EleInp2
Output
OptInp1
OptInp
OptInp2
HNOT G2
HAND G2
AB
EleInp2
Output
OptInp1
OptInp2
HAND_G3
Fig.4.45(a) Block diagram of a hybrid half adder.
CARRY = A.B
106
200KΩ
A
386Ω
200KΩ
VEE
87KΩ
VEE
87KΩ
386Ω
AB
200KΩ
A
500Ω
200KΩ
386Ω
VEE
87KΩ
200KΩ
386Ω
VEE
87KΩ
AB
200KΩ
87KΩ
200KΩ
500Ω
386Ω
HNOT_G1
VEE
500Ω
500Ω
500Ω
HAND_G1
106
200KΩ
386Ω
200KΩ
VEE
87KΩ
200KΩ
500Ω
HNOT_G2
200KΩ
VEE
87KΩ
386Ω
B
200KΩ
386Ω
87KΩ
386Ω
VEE
87KΩ
200KΩ
200KΩ
386Ω
500Ω
VEE
87KΩ
500Ω
500Ω
HAND_G2
B
HOR_G
VEE
B
SUM=A +
500Ω
HAND_G3
Fig.4.45(b) Full circuit diagram of hybrid half adder
CARRY = A.B
107
4.10.2 Bias point analysis
To verify the functionality of hybrid half adder, bias point analysis
is carried out using OrCAD CAPTURE simulation tool. The output
response for different electrical, optical and electrical/optical input
combinations is given in Table4.15.
From the simulation results given in Table4.15, it may be seen that
for all the given input logic values, the output SUM and CARRY values of
the hybrid half adder are within the defined logic values. Thus, the
functionality of hybrid half adder is verified.
Table4.15 Simulation results of hybrid half adder
Electrical inputs (V)
Electrical output (V)
Optical output (mA)
V i1
V i2
SUM
C OUT
SUM
C OUT
0
0
0
0
0
0
0
5
4.8
0
9.6
0
5
0
4.8
0
9.6
0
5
5
0
4.8
0
9.6
Optical inputs (mA)
Electrical output (V)
Optical output (mA)
I i1
I i2
SUM
C OUT
SUM
C OUT
0
0
0
0
0
0
0
10
4.8
0
9.6
0
10
0
4.8
0
9.6
0
10
10
0
4.8
0
9.6
Hybrid inputs
Electrical output (V)
Optical output (mA)
V i1 (V)
I i2 (mA)
SUM
C OUT
SUM
C OUT
0
0
0
0
0
0
5
0
4.8
0
9.6
0
0
10
4.8
0
9.6
0
5
10
0
4.8
0
9.6
4.10.3 Transient response
To calculate the minimum input pulse width that can be applied for
obtaining undistorted output response, the input pulse width is varied
and the output response of the hybrid half adder has been obtained. The
pulse width of
the electrical input signals are varied from 5µs to 1µs and
the output response for a typical case is given in Fig.4.46.
108
Vi1 (V)
5.0V
2.5V
0V
Vi2 (V)
5.0V
2.5V
0V
Vo2(V)
Vo1(V)
5.0V
2.5V
0V
5.0V
2.5V
Io1(mA)
0V
10mA
5mA
Io2(mA)
0A
10mA
5mA
0A
0s
10µs
20µs
30µs
40µs
50µs
60µs
70µs
80µs
90µs
100µs
Time
Fig.4.46 Transient response of hybrid half adder for electrical inputs.
It has been observed that the output logic levels are within the
defined logic levels as long as the electrical input pulse width is greater
than 1.8µs and the optical input pulse width is greater than 2µs. Hence,
the minimum input pulse width that can be applied to the hybrid half
adder is 1.8µs for electrical inputs and 2µs for optical inputs. The optical
Ii1(mA)
response for a typical case is given in Fig.4.47.
20mA
10mA
0A
Ii2(mA)
20mA
10mA
0A
Ii2(mA)
Ii1(mA)
10mA
5mA
0A
10mA
5mA
Io1(mA)
0A
5.0V
2.5V
0V
Io2(mA)
5.0V
2.5V
0V
0s
10µs
20µs
30µs
40µs
50µs
60µs
70µs
80µs
90µs
100µs
Time
Fig.4.47 Transient response of hybrid half adder for optical inputs.
109
4.11 HYBRID FULL ADDER
In the previous section, hybrid half adder has been demonstrated
using
bottom
up
hierarchical
design.
The
hybrid
half
adder
is
implemented using 2 hybrid inverters, 3 hybrid AND gates and 1 hybrid
OR gate. The hybrid full adder requires much higher complexity than the
hybrid half adder. Using hybrid half adder as a low level circuit block, the
hybrid full adder circuit has been implemented and discussed as follows.
4.11.1 Implementation of Hybrid Full Adder
Hybrid full adder is an arithmetic combinational logic circuit which
is used to perform the addition of two single bits taking previous carry
into account and produces SUM and CARRY. The three inputs (A, B and
C) to the full adder are either electrical and/or optical and produce both
electrical and optical SUM and CARRY outputs. The block diagram of
hybrid full adder which is realized by making use of two hybrid half
adders is shown in Fig.4.48. Two inputs (A and B) are added in one of the
half adder. The Sum and Carry produced in the first half adder are given
by the following boolean expressions,
SUM = A⊕B
⋅⋅⋅Eq.(4-4)
CARRY = AB
⋅⋅⋅Eq.(4-5)
The SUM produced in this hybrid half adder will be given as one of
the input to the second hybrid half adder along with the previous Carry
bit generated. The boolean expressions of the second hybrid half adder
outputs are given by,
SUM=A⊕B⊕C
⋅⋅⋅Eq.(4-6)
CARRY=AB+BC+CA
⋅⋅⋅Eq.(4-7)
The inputs to the hybrid full adder are either electrical or/and
optical signals. In this block diagram V i1 , V i2 and V i3 are the electrical
inputs and I i1 , I i2 and I i3 are the optical inputs. The boolean expressions
given in Eq.(4-6) and Eq.(4-7) gives the Sum and Carry of the hybrid full
110
adder. From these expressions, it is very clear that the Sum output of the
hybrid
full
adder
becomes
logic
HIGH
when
the
number
of
electrical/optical logic input HIGH’s are odd; and Carry becomes logic
HIGH when two or more electrical/optical inputs are logic HIGH.
Vi1
EleInp1
EleInp2
SUM2
(A⊕B)C
Ii1
OptInp1
OptInp2
SUM=A⊕B⊕C
CARRY2
HALFADDER_B1
EleInp1
EleInp2
Output
OptInp1
OptInp2
A⊕B
CARRY=AB+BC+CA
HOR_G
Vi3
Vi2
EleInp1
EleInp2
Ii3
Ii2
OptInp1
OptInp2
SUM1
CARRY1
AB
HALFADDER_B2
Fig.4.48 Block diagram of hybrid full adder using hybrid half adders
4.11.2 Bias point analysis
To verify the functionality of hybrid full adder, bias point analysis is
carried out using OrCAD CAPTURE simulation tool. The output response
for different electrical and optical input logic combinations is given in
Table4.16. From the Table4.16, it is very clear that the SUM output of the
hybrid
full
adder
becomes
logic
HIGH
when
the
number
of
electrical/optical input logic HIGH are odd; and CARRY becomes logic
HIGH when two or more electrical/optical inputs are logic HIGH.
From the simulation results given in Table4.16, it may be seen that
for all the input logic values, the output SUM and CARRY values of the
hybrid full adder are within the defined logic values. Thus, the
functionality of hybrid full adder is verified.
111
Table4.16 Simulation results of hybrid full adder
Electrical inputs (V)
Electrical output
(V)
SUM
C OUT
Optical output
(mA)
SUM
C OUT
V i3
V i2
V i1
0
0
0
0
0
0
0
0
0
5
4.8
0
9.6
0
0
5
0
4.8
0
9.6
0
0
5
5
0
4.8
0
9.6
5
0
0
4.8
0
9.6
0
5
0
5
0
4.8
0
9.6
5
5
0
0
4.8
0
9.6
5
5
5
4.8
4.8
9.6
9.6
Optical output (mA)
Electrical output
(V)
SUM
C OUT
Optical output
(mA)
SUM
C OUT
I i3
I i2
I i1
0
0
0
0
0
0
0
0
0
10
4.8
0
9.6
0
0
10
0
4.8
0
9.6
0
0
10
10
0
4.8
0
9.6
10
0
0
4.8
0
9.6
0
10
0
10
0
4.8
0
9.6
10
10
0
0
4.8
0
9.6
10
10
10
4.8
4.8
9.6
9.6
4.11.3 Transient response
To calculate the minimum input pulse width that can be applied for
obtaining undistorted output response, the input pulse width (PW) is
varied and the output response of the hybrid full adder has been
obtained. The pulse width of the electrical input signals are varied from
1ms to 1µs and the output response for a typical case is given in Fig.4.49.
It has been observed that the output response is not distorted as long as
the electrical input pulse width is greater than 1.6µs. Hence, the
minimum input pulse width that can be applied to the hybrid full adder is
1µs. Similar is the case with optical inputs and the response for a typical
case is given in Fig.4.50.
112
Vi1 (V)
5.0V
2.5V
Vi2 (V)
0V
5.0V
2.5V
0V
Vi3 (V)
5.0V
2.5V
Vo1 (V)
0V
5.0V
2.5V
0V
Vo2 (V)
5.0V
2.5V
0V
io1 (mA)
10mA
5mA
io2 (mA)
0A
10mA
0A
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
45ms
50ms
Time
Fig.4.49 Transient response of hybrid full adder for electrical inputs.
Ii1
20mA
10mA
0A
Ii2
20mA
10mA
0A
Ii3
20mA
10mA
0A
Io1
10mA
5mA
0A
Io2
10mA
5mA
0A
Vo1
5.0V
2.5V
0V
Vo2
5.0V
0V
0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
40ms
45ms
50ms
Time
Fig.4.50 Transient response of hybrid full adder for optical inputs.
113
4.12 4-BIT HYBRID ADDER
The 4-bit hybrid adder is implemented by making use of the hybrid
half adder and hybrid full adder circuit blocks and has been discussed in
the following.
4.12.1 Implementation of 4-bit hybrid adder
The
block
diagram
of
4-bit
hybrid
binary
adder which
is
implemented using one hybrid Half Adder (HA) and three hybrid Full
Adders (FA) is shown in Fig.4.51.
HALFADDER
Ele Inp1
VA0
VB0
SUM
S 0 = VA0 ⊕ VB0
Ele Inp2
OptInp1
OptIn p2
CARRY
C1
FULLADDER1
Ele Inp1
Ele Inp2
VA1
S 1=VA1 ⊕ VB1 ⊕ C1
SUM
EleInp3
VB1
OptInp1
OptInp2 CARRY
C2
OptInp3
FULLADDER2
Ele Inp1
Ele Inp2
VA2
S 2=VA2 ⊕ VB2 ⊕ C2
SUM
Ele Inp3
VB2
OptInp1
OptInp2 CARRY
C3
OptInp3
FULLADDER3
Ele Inp1
Ele Inp2
VA3
SUM
S 3=VA3 ⊕ VB3 ⊕ C3
Ele inp3
VB3
OptInp1
OptInp2 CARRY
OptInp3
C0UT =V A3.V B3⊕V B3.C3⊕ V A3.C3
Fig.4.51 Block diagram of 4-bit hybrid adder.
114
The 4-bit hybrid adder circuit is used to perform addition of two 4bit numbers. The 4-bit input numbers being added are (A3, A2, A1, A0
and B3, B2, B1, B0) either electrical or optical. A3 and B3 are the most
significant bits while A0 and B0 are the least significant bits. The 4-bit
hybrid adder produces both electrical and optical 4-bit SUM (S3S2S1S0)
and 1-bit CARRY as the outputs.
4.12.2 Bias point analysis (DC calculations)
To verify the functionality of 4-bit hybrid adder, bias point analysis
is carried out using OrCAD CAPTURE simulation tool. There are 256
different input combinations possible with two 4-bit numbers. The output
response for some of the input logic combinations are given in Table4.17.
From the simulation results given in Table4.17, it may be seen that for
the given input logic level values, the output SUM and CARRY values of
the 4-bit hybrid adder are within the defined logic values. Thus, the
functionality of 4-bit hybrid adder is verified.
Table4.17 Simulation results of 4-bit hybrid adder
Electrical inputs (V)
Electrical output (V)
Optical output (mA)
Addend
V A3
0
0
5
5
5
5
5
5
V A2
0
5
5
0
0
0
5
5
V A1
Augend
V A0
VB
VB
VB
VB
3
2
1
0
5
5
5
5
5
5
0
5
5
0
0
0
5
0
5
5
0
0
5
5
0
5
5
0
0
0
0
5
5
0
5
5
0
5
5
0
0
5
5
0
5
0
5
5
5
5
5
5
Optical inputs (mA)
Addend
I A3
0
10
10
10
10
10
10
10
I A2
0
10
10
0
0
0
10
10
I A1
0
0
0
10
0
0
10
10
SUM
V S3
4.8
4.8
0
4.8
0
0
4.8
4.8
I B3
10
0
0
10
10
10
10
10
I B2
10
10
10
10
0
0
10
10
I B1
10
0
10
10
10
10
0
10
V S1
V S0
SUM
I B0
10
10
0
0
10
0
10
10
VC
4.8 4.8 4.8 0
4.8 4.8 4.8 0
0
4.8 0
4.8
0
0
0
4.8
4.8 0
0
4.8
0
4.8 4.8 4.8
0
4.8 4.8 4.8
4.8 4.8 0
4.8
Electrical output (V)
Augend
I A0
0
0
0
0
10
10
0
10
V S2
C OUT
V S3
4.8
0
0
4.8
0
0
4.8
4.8
V S2
4.8
0
0
0
4.8
0
0
4.8
V S1
4.8
0
4.8
0
0
4.8
4.8
4.8
SUM
I S3
I S2
9.6
9.6
0
9.6
0
0
9.6
9.6
9.6
9.6
0
0
9.6
0
0
9.6
Optical
C OUT
V S0
4.8
4.8
0
0
0
4.8
4.8
0
VC
0
4.8
4.8
4.8
4.8
4.8
4.8
4.8
I S1
C OUT
I S0
9.6 9.6 0
9.6 9.6 0
9.6 0
9.6
0
0
9.6
0
0
9.6
9.6 9.6 9.6
9.6 9.6 9.6
9.6 0
9.6
output (mA)
SUM
I S3
9.6
0
0
9.6
0
0
9.6
9.6
I S2
9.6
0
0
0
9.6
0
0
9.6
IC
I S1
9.6
0
9.6
0
0
9.6
9.6
9.6
C OUT
I S0
9.6
9.6
0
0
0
9.6
9.6
0
IC
0
9.6
9.6
9.6
9.6
9.6
9.6
9.6
115
4.13 Summary
The basic hybrid building blocks like, hybrid inverter, NAND, NOR,
EX-OR, AND and OR logic gates have been discussed and demonstrated
in this chapter. These basic hybrid logic blocks can be used in building
hierarchical circuits, as the input and output logic levels are almost the
same and within the defined logic levels. The hybrid EX-OR gate has been
implemented by making use of the hybrid AND, OR gates which are
obtained from universal hybrid NAND and NOR gates and inverters and it
clearly indicated that hybrid optoelectronic logic gates are cascadable and
large hybrid combinational circuits can be realized. In continuation of this
thought process, it is further demonstrated that usable and large
combinational circuits can be realized
by implementing combinational
hybrid circuits like, hybrid half adder, hybrid full adder and hybrid 4-bit
adder. These combinational hybrid circuits have been implemented using
hierarchical design procedure with OrCAD Capture. A bottom up design
methodology is used for implementing the hybrid combinational circuits.
The basic logic circuits that are used in realizing digital systems are
the combinational circuits and sequential circuits. Hybrid logic gates and
combinational circuits have been discussed in this chapter. Hybrid
sequential circuits have been discussed in the next chapter.