Propagation Delay
CMOS Inverter: Transient Response
V DD
V DD
tpHL = f(R on.C L)
Rp
= 0.69 R onCL
V out
V out
CL
CL
Rn
V in = 0
(a) Low-to-high
V in = V DD
(b) High-to-low
Computing the Capacitances
V DD
V DD
M1 and M2 are either in cut-off or
in saturation mode during the first
half (up to 50%) of the output
transient.
M2
V in
C g4
Cdb 2
C gd 12
M4
V out
Cdb 1
Cw
M1
Vout 2
C g3
M3
The channel capacitance is either
completely located between gate
and bulk (cut-off) or gate and
source (saturation).
Interconnect
Fanout
Simplified (lumped)
Model
Vin
The lumped model requires the
gate-drain capacitance to be
replaced by a capacitor to ground.
So we take the Miller effect.
V out
CL
Diffusion capacitances C db1 and Cdb2 are due to
the reverse-biased pn-junction (same as we did
for diode & MOS case – Ceq=KeqCj0)
Thus, the only contribution to C gd12
are the overlap capacitances of
both M1 and M2.
− Φ0
K eq =
[(Φ 0 − Vhigh )1− m − (Φ 0 − Vlow )1− m ]
(Vhigh − Vlow )(1 − m)
m
Miller Effect
Cgd 1
∆V
V out
Vout
∆V
Vin
M1
2Cgd1
∆V
M1
Vin
“A capacitor experiencing identical but opposite voltage swings
at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.”
C gd = 2C GD 0W
∆V
CGD0 is the overlap capacitance per unit width
Gate Capacitance (Cg4 , Cg3)
V DD
V DD
Assumptions
(1)
M2
V in
C g4
Cdb 2
C gd 12
M4
V out
Cdb 1
Cw
M1
Vout 2
C g3
M3
Interconnect
(2)
Fanout
Simplified (lumped)
Model
Vin
V out
CL
Ignores Miller effect on the
gate-drain capacitance. This
is acceptable since the
connecting gate would not
switch before the 50% point
is reached, and Vout2 remains
constant in the interval of
interest.
The channel capacitance of
the connecting gate is
constant over the interval of
interest. In reality it varies
from 2/3CoxWL in saturation
to WLC ox in linear and cutoff.
C fan−out = Cgate ( NMOS) + C gate ( PMOS )
C fan−out = (CGS 0 n + CGD 0 n + Wn Ln Cox ) + (CGS 0 p + CGD 0 p + W p Lp Cox )
Propagation Delay: First Order Analysis
Integrate the capacitor (dis)charge current.
tp =
v2
C L (v )
∫v i (v) dv
1
This is very difficult to solve since both CL(v) and i(v) are nonlinear functions of v.
We fall back to the simplified switch model of the inverter. The voltage
dependencies of the “on” resistance and the load capacitance are addressed
replacing both by a constant linear element with a value averaged over the
interval of interest.
Req =
I DSAT
1
V DD
V
3 VDD
7
dV
≈
(
1
−
λVDD )
VDD / 2 VDD∫/ 2 I DSAT (1 + λV )
4 I DSAT
9
W
= k'
L
2

VDSAT 
 (VDD − VT )VDSAT −



2


CMOS Inverter Propagation Delay
VDD
tpHL = f(R on.CL)
Ron=Req
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
t
t pLH = 0.69 Reqp C L
tp =
t pHL + t pLH
2
© Digital Integrated Circuits 2nd
 Reqn + Reqp 

= 0.69C L 
2


Inverter
Transient Response
Hand calculated
tpHL=0.69x(13Kohm/1.5)x6.1fF=36psec
tpLH=0.69x(31kohm/4.5)x6.1fF=29psec
Thus, tp=32.5psec
Spice
tpHL=39.9psec
tpLH=31.7psec
3
Vin
2.5
2
(V)
1.5
out
V
tp = 0.69 CL (Reqn+Reqp)/2
1
tpHL
tpLH
0.5
0
-0.5
0
0.5
1
1.5
t (sec)
© Digital Integrated Circuits 2nd
2
2.5
x 10
-10
Inverter
The previous example might give the impression that manual
analysis always leads to close approximations of the actual
response. This is not necessarily the case. Large deviations can
often be observed between first and higher order models. The
purpose of the manual analysis is to get a basic insight into the
behavior of the circuit and to determine the dominant parameters.
A detailed simulation is indispensable!
© Digital Integrated Circuits 2nd
Inverter
Delay as a function of VDD (ignoring
channel-length modulation)
5.5
5
4.5
t p(normalized)
4
For high VDD values (V DD>VTn+VDSATn /2), the
delay is virtually independent of V DD.
3.5
3
It comes as no surprise that Req has the same
behavior with V DD.
2.5
When V DD<VTn+VDSATn /2 ~ 2VTn, a sharp increase
in delay is seen.
This operation region
should be avoided if achieving high performance
is a primary goal.
2
1.5
1
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
V (V)
DD
© Digital Integrated Circuits 2nd
Inverter
Design for Performance
q
Keep capacitances small (diffusion capacitances, gate
capacitances, wiring capacitance, and fanout)
q
Increase transistor sizes
§ watch out for self-loading! Once the intrinsic capacitance
(diffusion capacitance starts to dominate the extrinsic load
formed by wiring and fanout, increasing the gate size no
longer helps reduce delay. It only makes the gate larger in
area.
q
Increase VDD (????) – trading off performance for power.
Increasing VDD above a certain values yields minimal
improvement to delay. Reliability issues – oxide breakdown, hot
carrier effects.
© Digital Integrated Circuits 2nd
Inverter
NMOS/PMOS ratio
5
x 10
Making PMOS width ~ 3 times larger than NMOS
width is to create an inverter with symmetrical VTC
and equal tpHL, tpLH. However, this doesn’t yield
minimum delay.
-11
Widening PMOS improves tpLH by increasing the
charging current, but degrades tpHL by causing
larger parasitic capacitance. Thus, a transistor ratio
must exist to optimize the delay of the inverter.
tpHL
tpLH
t p(sec)
4.5
C L = (Cdp1 + Cdn1 ) + (C gp 2 + C gn2 ) + CW
tp
4
When PMOS is β times larger than NMOS, all
device capacitances scale approximately in same
way; Cpd1~ β Cdn1 and Cgp2~ β Cgn2.
3.5
C L = (1 + β )(C gn1 + Cdn1 ) + CW
3
1
1.5
2
2.5
3
3.5
4
β
β = Wp/Wn
r=
Reqp
Reqn
β opt = r (1 +
© Digital Integrated Circuits 2nd
CW
)
Cdn1 + C gn2
4.5
5
R
0.69
[(1 + β )(Cdn1 + C gn2 ) + CW ](Reqn + eqp )
2
β
r
t p = 0.345[(1 + β )(Cdn1 + C gn 2 ) + CW ]Reqn (1 + )
β
tp =
β opt = r
When wiring is negligible
Smaller devices yield faster designs at expense of
symmetry and noise margin
Inverter
Device Sizing
-11
3.8
The PMOS and NMOS are sized to
achieve equal rise and fall delays.
x 10
(for fixed load)
3.6
3.4
t p = 0.69 ReqCint ( +Cext / Cint ) = t p 0 (1 + Cext / Cint )
tp(sec)
t p = 0.69 Req (Cint + Cext )
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
By sizing up the inverter by S (a sizing
factor to relate to a minimum sized
inverter) – Cint = SCiref and Req=Rref/S.
Cint consists of the diffusion + miller
capacitances.
2.4
2.2
2
2
4
t p = 0.69( Rref / S )(SC iref )(+Cext / SC iref ) = 0.69 Rref Ciref (1 +
6
8
S
10
12
14
Cext
) = t p 0 (1 + Cext / SCiref )
SC iref
(1) Intrinsic inverter delay tp0 is independent of the gate sizing, and is determined by the technology + layout.
(2) Making S large yields high performance gain, eliminating the impact of external loads, and reducing delay of
the intrinsic one – but also yield large silicon area!
Cext/Cint~1.05 (Cint=3fF, Cext=3.15fF). This leads to a max performance gain of 2.05. With S=1 0 it allows us to
get within 10% optimal performance, while larger device sizes only yield ignorable performance gains. By
simulating, max obtainable performance improvement = 1.9 (tp0=19.3psec)
© Digital Integrated Circuits 2nd
Inverter
Impact of Rise Time on Delay
All previous assumptions are rise and fall times = 0.
Only one device was assumed to be (dis)charging.
In realiy, the input signal changes gradually, and
temporarily PMOS and NMOS devices conduct
simultaneously. This affects the current available for
(dis)charging and hence delay.
0.35
tpHL (nsec)
0.3
If a latter gate is indefinitely strong, its output slope is
zero, and the performance of the gate under
examination is unaffected.
0.25
0.2
0.15
0
0.2
0.4
0.6
t rise (nsec)
0.8
1
The main point here is that a gate is never designed
in isolation, and that its performance is affected by
both the fanout and driving strength of the gate(s)
feeding into its inputs.
Note: It is advantageous to keep the signal rise times smaller than or equal the gate propagation
delays. Aside from enhancing performance, it saves on power consumption. Keeping the rise and fall
times of signals small and approximately equal is one of the major challenges in high-performance
design ; slope engineering
© Digital Integrated Circuits 2nd
Inverter