CHK040A-SOA
40W Power Packaged Transistor
GaN HEMT on SiC
Description
The CHK040A-SOA is an unmatched
packaged Gallium Nitride High Electron
Mobility Transistor. It offers general purpose
and broadband solutions for a variety of RF
power applications. It is well suited for multipurpose applications such as radar and
telecommunication
The CHK040A-SOA is developed on a 0.5µm
gate length GaN HEMT process. It requires
an external matching circuitry.
The CHK040A-SOA is available in a ceramicmetal flange power package providing low
parasitic and low thermal resistance.
VDS = 50V, ID_Q = 300mA, Freq=3GHz
Pulsed mode
■ Wide band capability: up to 3.5GHz
■ Pulsed and CW operating modes
■ High power: > 45W
■ High Efficiency: up to 70%
■ DC bias: VDS =50V @ ID_Q =300mA
■ MTTF > 106 hours @ Tj=200°C
■ RoHS Flange Ceramic package
■ ESD-HBM: Class1B (1KV)
■ ESD-MM: ClassB (400V)
Gain (dB), Pout (dBm) & PAE (%)
60
55
3.3
PAE
Pulsed Mode at 3GHz
3
50
2.7
45
Pout
40
2.4
2.1
35
1.8
30
Id
25
1.5
Id (A)
Main Features
1.2
20
0.9
15
Gain
10
0.6
0.3
5
0
0
12 14 16 18 20 22 24 26 28 30 32 34 36 38
Input Power (dBm)
Intrinsic performances of the packaged device
Main Electrical Characteristics
Tcase= +25°C, Pulsed mode, F = 3GHz, VDS=50V, ID_Q=300mA
Symbol
Parameter
Min
16
GSS
Small Signal Gain
45
PSAT
Saturated Output Power
Max Power Added Efficiency
55
PAE
GPAE_MAX Associated Gain at Max PAE
Ref. : DSCHK040ASOA6092 - 01 Apr 16
1/14
Typ
18
55
60
13
Max
-
Unit
dB
W
%
dB
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Recommended DC Operating Ratings
Tcase= +25°C
Symbol
Parameter
VDS
Drain to Source Voltage
VGS_Q
Gate to Source Voltage
ID_Q
Quiescent Drain Current
ID_MAX
Drain Current
Gate Current (forward
mode)
Tj_MAX
Junction temperature
(1)
Limited by dissipated power
IG_MAX
Min
20
Typ
-1.9
0.3
2
0
Max
50
Unit
V
V
A
A
1
(1)
12
mA
200
°C
Conditions
VD=50V, ID_Q=300mA
VD=50V
VD=50V,
Compressed mode
Compressed mode
DC Characteristics
Tcase= +25°C
Symbol
Parameter
Min
Typ
Max Unit
Conditions
VP
Pinch-Off Voltage
-3
-2
-1
V
VD=50V, ID= IDSS /100
(1)
ID_SAT
Saturated Drain Current
8
A
VD=7V, VG=2V
Gate Leakage Current -2.5
IG_leak
mA VD=50V, VG=-7V
(reverse mode)
Drain-Source
VBDS
200
V
VG=-7V, ID=20mA
Break-down Voltage
°C/W
RTH
Thermal Resistance (2)
2.4
(1)
For information, limited by ID_MAX , see on Absolute Maximum Ratings
(2)
CW mode, reference = package back-side
RF Characteristics (CW)
Tcase= +25°C, CW mode, F = 3GHz, VDS=50V, ID_Q=300mA
Symbol
Parameter
GSS
Small Signal Gain
PSAT
Saturated Output Power
Max Power Added Efficiency
PAE
GPAE_MAX Associated Gain at Max PAE
Ref. : DSCHK040ASOA6092 - 01 Apr 16
2/14
Min
15
40
50
Typ
17
50
55
Max
-
Unit
dB
W
%
12
-
dB
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
RF Characteristics (Pulsed)
Tcase= +25°C, Pulse mode (1), F = 3GHz, VDS=50V, ID_Q=300mA
Symbol
Parameter
Min
Typ
Max
Unit
GSS
Small Signal Gain
16
18
dB
PSAT
Saturated Output Power
45
55
W
PAE
Max Power Added Efficiency
55
60
%
GPAE_MAX Associated Gain at Max PAE
13
dB
(1)
Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs
offset between DC and RF pulse.
These values are the intrinsic performance of the packaged device. They are deduced from
measurements and simulations. They are considered in the reference plane defined by the
leads of the package, at the connection interface with the PCB.
The typical performance achievable in more than 25% frequency band around 3GHz was
demonstrated using the reference board 61499547 presented hereafter.
Absolute Maximum Ratings
Tcase= +25°C(1), (2), (3)
Symbol
Parameter
VDS
Drain-Source Voltage
VGS_Q
Gate-Source Voltage
IG_MAX
Maximum Gate Current in forward mode
IG_MIN
Maximum Gate Current in reverse mode
ID_MAX
Maximum Drain Current
PIN
Maximum Input Power (typical)
Tj
Junction Temperature
TSTG
Storage Temperature
TCase
Case Operating Temperature
Rating
60
-10, +2
72
-8
6
39
230
-55 to +150
See note
Unit
V
V
mA
mA
A
dBm
°C
°C
°C
Note
(6)
(4)
(5)
(4)
(1)
Operation of this device above anyone of these parameters may cause permanent
damage.
(2)
Duration < 1s.
(3)
The given values must not be exceeded at the same time even momentarily for any
parameter, since each parameter is independent from each other, otherwise deterioration or
destruction of the device may take place.
(4)
Max junction temperature must be considered
(5)
@3GHz - Linked to and limited by IG_MAX & IG_MIN values
(6)
VGS_Q max limited by ID_MAX and IG_MAX values
Ref. : DSCHK040ASOA6092 - 01 Apr 16
3/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Simulated Source and Load Impedance
VDS = 50V, ID_Q = 300mA
Zload
Zsource
Frequency (MHz)
500
1000
2000
3000
3500
Source
1 + j4.5
1 + j1.9
1.3 - j1.9
1.4 - j4.8
0.8 - j6.7
Load
21.6 + j7
15.3 + j14.3
5 + j7.9
2.8 + j2.3
2.3 + j0.2
These values are given in the reference plane defined by the connection between the
package leads and the PCB. A gap of 200µm is considered between the edge of the
package and the PCB.
Ref. : DSCHK040ASOA6092 - 01 Apr 16
4/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Typical S-parameters
Tcase= +25°C, CW mode, VD=50V, ID_Q=300mA, Phase S(i,j) in °
Freq
(GHz)
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
6.25
6.50
6.75
7.00
7.25
7.50
7.75
8.00
8.25
8.50
8.75
9.00
9.25
9.50
9.75
10.00
Mag
S(1,1)
0.990
0.890
0.900
0.900
0.910
0.920
0.930
0.930
0.940
0.940
0.950
0.950
0.950
0.950
0.950
0.950
0.960
0.950
0.950
0.950
0.950
0.950
0.950
0.950
0.940
0.940
0.930
0.930
0.920
0.920
0.910
0.900
0.890
0.880
0.870
0.850
0.830
0.820
0.800
0.790
0.780
Phase
S(1,1)
0.0
-148.8
-165.1
-171.3
-175.1
-178.1
179.4
177.1
175.0
172.8
170.8
168.7
166.7
164.7
162.6
160.5
158.4
156.2
154.0
151.6
149.2
146.7
144.0
141.2
138.2
135.0
131.5
127.8
123.7
119.3
114.4
108.9
102.7
95.8
87.9
79.0
68.7
57.0
43.8
29.0
12.8
Ref. : DSCHK040ASOA6092 - 01 Apr 16
Mag
S(2,1)
102.980
26.700
13.340
8.590
6.130
4.640
3.650
2.950
2.450
2.060
1.770
1.540
1.360
1.220
1.100
1.000
0.930
0.860
0.810
0.760
0.730
0.700
0.680
0.660
0.650
0.640
0.640
0.640
0.650
0.660
0.680
0.700
0.730
0.760
0.800
0.840
0.890
0.950
1.000
1.050
1.100
Phase
S(2,1)
-180.0
94.9
77.6
65.8
56.0
47.4
39.9
33.1
27.1
21.6
16.6
11.9
7.6
3.6
-0.3
-3.9
-7.5
-10.9
-14.3
-17.6
-20.9
-24.2
-27.6
-31.0
-34.5
-38.1
-41.9
-45.9
-50.1
-54.6
-59.5
-64.7
-70.4
-76.7
-83.6
-91.3
-99.9
-109.5
-120.1
-131.9
-144.9
5/14
Mag
S(1,2)
0.000
0.012
0.012
0.011
0.009
0.008
0.006
0.005
0.005
0.005
0.006
0.007
0.008
0.010
0.012
0.013
0.015
0.017
0.019
0.020
0.022
0.024
0.027
0.029
0.031
0.034
0.037
0.040
0.043
0.047
0.051
0.055
0.061
0.066
0.073
0.080
0.088
0.097
0.106
0.115
0.123
Phase
S(1,2)
180.0
8.7
-4.6
-11.7
-15.6
-16.1
-12.2
-2.2
13.9
31.4
44.7
52.7
57.0
58.9
59.5
59.2
58.3
57.0
55.4
53.6
51.6
49.5
47.3
44.9
42.5
39.9
37.1
34.2
31.1
27.7
24.1
20.1
15.6
10.7
5.1
-1.2
-8.3
-16.4
-25.5
-35.8
-47.4
Mag
S(2,2)
0.530
0.370
0.420
0.500
0.570
0.630
0.690
0.730
0.770
0.800
0.820
0.840
0.860
0.870
0.880
0.890
0.900
0.900
0.910
0.910
0.920
0.920
0.920
0.920
0.920
0.920
0.920
0.920
0.920
0.910
0.910
0.910
0.900
0.900
0.890
0.890
0.880
0.870
0.870
0.860
0.850
Phase
S(2,2)
0.0
-127.8
-138.0
-141.5
-145.0
-148.8
-152.7
-156.5
-160.2
-163.6
-166.8
-169.9
-172.8
-175.5
-178.1
179.3
176.9
174.5
172.1
169.7
167.4
165.0
162.7
160.3
157.8
155.2
152.6
149.9
147.0
144.0
140.7
137.2
133.5
129.4
124.8
119.8
114.1
107.6
100.1
91.4
81.0
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Maximum Gain & Stability Characteristics
Tcase= +25°C, CW mode, VD=50V, ID_Q=300mA
40
4.0
35
Maximum Gain
3.0
25
20
2.0
15
10
K Factor
Max. Gain (dB)
30
1.0
K Factor
5
0
0.0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Frequency (GHz)
Ref. : DSCHK040ASOA6092 - 01 Apr 16
6/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Typical Performance on Demonstration Board (Ref. 61499547)
Calibration and measurements are done on the connector reference accesses of the
demonstration boards.
Tcase = +25°C, CW mode
Measured Id, Pout, Gain & PAE
F = 3GHz, VDS = 50V, ID_Q = 300mA
3.3
CW Mode at 3GHz
50
45
3
2.7
Pout
40
2.4
35
Id
PAE
2.1
30
1.8
25
1.5
20
1.2
15
Id (A)
Gain (dB), Pout (dBm) & PAE (%)
55
0.9
Gain
10
0.6
5
0.3
0
0
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Input Power (dBm)
Measured Gain, Pout & PAE
Pin = 38dBm, VDS = 50V, ID_Q = 300mA
56
19
CW Mode
54
18
17
50
16
Pout
48
15
46
14
PAE
44
13
42
12
40
11
38
Gain (dB)
Pout (dBm) & PAE (%)
52
10
Gain
36
9
34
8
32
7
30
6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
Frequency (GHz)
Ref. : DSCHK040ASOA6092 - 01 Apr 16
7/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Typical Performance on Demonstration Board (Ref. 61499547)
Calibration and measurements are done on the connector reference accesses of the
demonstration boards
Tcase = +25°C, Pulsed mode (1)
Measured Id, Pout, Gain & PAE
F = 3GHz, VDS = 50V, ID_Q = 300mA
3.3
Pulsed Mode at 3GHz
50
3
45
2.7
40
2.4
Pout
Id
35
30
2.1
1.8
PAE
25
1.5
20
1.2
15
Id (A)
Gain (dB), Pout (dBm) & PAE (%)
55
0.9
Gain
10
0.6
5
0.3
0
0
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Input Power (dBm)
Measured Gain, Pout & PAE
Pin = 38dBm, VDS = 50V, ID_Q = 300mA
56
18
PAE
52
17
50
16
48
15
46
14
Pout
44
13
42
12
40
11
38
Gain (dB)
Pout (dBm) & PAE (%)
19
Pulsed Mode
54
10
Gain
36
9
34
8
32
7
30
6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
Frequency (GHz)
(1)
Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs
offset between DC and RF pulse.
Ref. : DSCHK040ASOA6092 - 01 Apr 16
8/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Demonstration Amplifier Low Frequency Equivalent Schematic
(Ref. 61499547)
+
+
Vg
Vd
J2
J3
Demonstration Amplifier / Bill of Materials (Ref. 61499547)
Designator
C1
C2
C3
C4
C5
C6
C7
C8
R1
R2
J1
J2, J3
Q1
-
Type
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Connector
Connector
Packaged Transistor
PCB
Ref. : DSCHK040ASOA6092 - 01 Apr 16
9/14
Value - Description
1.5pF, +/- 0.1pF, 0603
2.7pF, +/- 0.1pF, 0603
8.2pF, +/- 0.25%, 0603
82pF, +/- 5%, 0603
240pF, +/- 5%, 0805
1nF, +/- 5%, 0805
10nF, +/- 5%, 0805
1µF, +/- 10%, 1204
90.9Ω, +/- 1%, 0603
5,1Ω +/- 1%, 0603
CMS 3cts
N
CHK040A-SOA
RO4003, Er=3.55, h=0.508mm
Qty
1
1
3
3
3
3
3
2
1
1
2
2
1
-
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Demonstration Amplifier Circuit (Ref. 61499547)
Ref. : DSCHK040ASOA6092 - 01 Apr 16
10/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Package outline
All dimensions are in mm
Tcase
Tcase
(A)
(A)
(°C)
(°C)
(A)
Tcase locates the reference point used to monitor the device temperature. This point has
been taken at the device / system interface to ease system thermal design.
Chamfered lead indicates the gate access of the packaged transistor.
Ref. : DSCHK040ASOA6092 - 01 Apr 16
11/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Recommended Assembly Procedure
CHK040A-SOA is available has a flange package to be bolt down onto a thermal heat sink
also used as main electrical ground. Use preferably screw M2 and flat washers.
Thermal and electrical resistance at the package to heat sink interface has to be as low as
possible. Thermal electrically conductive grease or conductive thin layer like indium sheets
are recommended between the package and the heat sink.
In case a thermal grease is selected, we recommend to use material offering thermal
conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness
should be about 25µm (1 mil).
Contact interface quality can be improved by cleaning process prior device mounting on the
heat-sink. Such operation will enhance the thermal and electrical contact by oxide removal at
each interface.
Package leads can be soldered on printed circuit board’s traces by using RoHS solder past.
Cavity depth and width to be performed into the heat-sink where the device will be mounted
are important to achieve the best performances. These dimensions have to be optimized in
order to minimize the distance between device and signal traces made on the printed circuit
board (PCB). But they also have to be calculated in order to accommodate device variations
in height. The following drawing gives the relationship between device dimensions (Hpack &
Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed circuitboard configuration (HPCB)
Ref. : DSCHK040ASOA6092 - 01 Apr 16
12/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Notes
Ref. : DSCHK040ASOA6092 - 01 Apr 16
13/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK040A-SOA
40W Power Packaged Transistor
Recommended environmental management
UMS products are compliant with the regulation in particular with the directives RoHS
N°2011/65 and REACh N°1907/2006. More environmental data are available in the
application note AN0019 also available at http://www.ums-gaas.com.
Recommended ESD management
Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD
sensitivity and handling recommendations for the UMS package products.
Qualification domain
The CHK040A-SOA is qualified according to UMS rules, excluding humid environment as it
is in non hermetic package.
Ordering Information
Package:
CHK040A-SOA/XY
Tray: XY = 26
Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors
S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use
as critical components in life support devices or systems without express written approval from United
Monolithic Semiconductors S.A.S.
Ref. : DSCHK040ASOA6092 - 01 Apr 16
14/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34