1. Digital Circuit Design: An Overview
Fig. 1 shows the major IC technologies and logic-circuit families that are currently in use.
The selection of a logic family is based on such factors as logic flexibility, speed of
operation, availability of complex functions, noise immunity, operating temperature
range, power dissipation and cost.
Figure 1.1 Digital IC technologies and logic-circuit families.
CMOS technology is by a large margin the most dominant of all Integrated Circuit (IC)
technologies available for digital circuit design. The advantages of CMOS technology
are:
1) CMOS logic circuits dissipate much less power than bipolar logic circuits and thus
one can pack more CMOS circuits on a chip than is possible with bipolar circuits.
2) The high input impedance of the MOS transistor allows the designer to use charge
storage as a means of temporary storage of information in both logic and memory
circuits. (This technique can not be used in bipolar circuits.)
3) The feature size (i.e. channel length) of a MOS transistor has decreased dramatically
over the years. This permits very tight circuit packing and correspondingly, very high
levels of integration.
Of the various forms of MOS technology, complementary-MOS (CMOS) is the most
widely used is VLSI logic with millions of gates per chip) and memory-circuit design.
Pseudo-NMOS logic circuits dissipate significant static power when compared to
complementary CMOS logic circuits. Pass-transistor logic is used in specific applications
and is frequently used in conjunction with complementary CMOS logic circuits. Dynamic
logic CMOS utilize dynamic techniques to obtain faster circuit operation, while keeping
power dissipation very low and may offer circuit advantages over static logic circuits.
2. CMOS Inverters: Static Characteristics
The logic symbol and truth table of an ideal inverter is shown in Fig. 2.1. Fig. 2.2 shows
the DC Voltage Transfer Characteristic (VTC) of an ideal inverter. The general shape of
the VTC is shown in Fig 2.3, where
VOH:
VOL:
VIL:
VIH:
Maximum output voltage when the output level is a logic “1”
Minimum output voltage when the output level is a logic “0”
Maximum input voltage which can be interpreted as a logic “0”
Minimum input voltage which can be interpreted as logic “1”
Vth:
The inverter threshold voltage is defined when Vin  Vout
Figure 2.1 Logic symbol and truth table of the inverter
Figure 2.2 Voltage Transfer Characteristic (VTV) of an ideal inverter
Figure 2.3 Typical Voltage Transfer Characteristic (VTC) of a realistic inverter
The input low voltage (VIL) and the input high voltage (VIH) are defined when
dVout
 1
dVin
(2.1)
Both of these voltages play significant roles in determining the noise margins of the
inverter. Note that when Vin  V IL and V IH  Vin  VOH the slope dVout / dVin is less than
unity and the output changes slowly with the input. Thus the output is less sensitive to a
noisy input signal.
The ability of an inverter to interpret an input signal within a voltage range as either a
logic “0” or as a logic “1” allows digital circuits to operate within a certain tolerance to
external circuit perturbations. This tolerance to variations in the signal level is especially
valuable in environments in which circuit noise (usually interconnects by capacitive or
inductive coupling or from outside the system) can significantly corrupt the signals.
Noise Immunity and Noise Margins
Consider the circuit shown in Fig. 2.4. The output of the first inverter VOL is being
transmitted to the next inverter. The interconnect (metal or polysilicon) causes the signal
to change to VOL. Similarly, the output of the second inverter VOH is also transmitted
through the interconnect line causing the signal to change to VIH. For the overall circuit to
operate properly the noise margins of the design must be satisfied.
Two noise margins will be defined as: the noise margins for the low signal levels ( NM L
) and the noise margins for the high signal levels ( NM H ) and are defined as
NM L  V IL  VOL
NM H  VOH  V IH
(2.2)
(2.3)
Fig. 2.5 shows a graphical illustration of the noise margins. The Transition Region (also
called the uncertain region) labelled in Fig 2.5 corresponds to the input voltage values
that may not be processed correctly either as a logic “0” input or as a logic “1” input. For
any digital system, the five critical voltage points VOH, VOL, VIL, VIH and Vth fully
determined the DC input-ouput voltage behaviour, the noise margins, and the width and
location of the transition region.
Figure 2.4 Propagation of digital signals under the influence of noise
Figure 2.5 Definitions of noise margins. Shaded area indicate valid low and high levels
for the input and output signals
CMOS Inverter: Circuit Operation
Fig. 2.6 shows a CMOS inverter consisting of an enhance-type nMOS transistor and an
enhance-type pMOS transistor operating in complementary mode. For high input, the
nMOS transistor pulls down the output node, while the pMOS acts as a load, and for low
inputs the pMOS pulls up the output node while th nMOS acts as a load.
CMOS process is more complex than the standard nMOS-only process since both
nMOS and pMOS transisters must be fabricated on the same chip. This increase in
process complexity of CMOS fabrication may be considered as the price being paid for
the improvements achieved in power consumption and noise margins.
Figure 2.6 (a) CMOS inverter circuit (b) Simplified CMOS inverter viewed as two
complementary nonideal switches.
Figure 2.7 Operating regions of the nMOS and pMOS transistors.
The objective is to determine the five critical points of the DC Voltage Transfer
Characteristic (VTC) (i.e. VOH, VOL, VIL, VIH and Vth) as illustrated in Fig. 2.3. Fig. 2.7
shows the operating regions of the nMOS and pMOS transistors.
The substrate of the nMOS transistor is connected to ground, while the substrate of the
pMOS transistor is connected to the voltage supply VDD. Since VSB=0 for both devices,
there will be no substrate-bias effect for either device.
When the input voltage is smaller than the nMOS threshold voltage (i.e. Vin  VT 0,n ), the
nMOS transistor is cut-off. At this point is time, the pMOS transistor is on, operating in
the linear region (also known as the triode or Ohmic region). The load of the inverter at
DC is considered to be open circuit due to the high gate impedance of MOS transistors.
Since the drain currents of both transistors are approximately equal to zero (except for
small leakage currents)
I D ,n  I D , p  0
(2.4)
The drain to source voltage of the pMOS transistor is also equal to zero, and the output
voltage VOH is equal to the power supply voltage:
Vout  VOH  V DD
(2.5)
For the case when the input voltage exceeds (V DD  VT 0, p ) (Note: VT 0, p is negative value
for pMOS transistor), the pMOS transistor is turned off, while the nMOS transistor is
operating in the linear region. The drain-to-source voltage of the nMOS transistor is equal
to zero due to (2.4). Consequently, the output voltage of the circuit is
Vout  VOL  0
(2.6)
The next sections show how to calculate VIL, VIH and Vth for the CMOS inverter.
Calculation of VIL
By definition the slope of the VTC is equal to negative one (i.e. dVout / dVin  1 ) when the
input voltage is Vin  V IL . In this situation, the nMOS transistor operates in saturation
while the pMOS transistor operates in the linear region. Since I D,n  I D, p , the following
current relationship is obtained:
Kn
2
(VGS , n  VT 0, n ) 2 
Kp
2
2(V
GS , p
2
 VT 0 , p )V DS , p  V DS
,p

(2.7)
Using, VGS ,n  Vin , V DS ,n  Vout , VGS , p  (V DD  Vin ) and V DS , p  (V DD  Vout ) , equation (2.7)
can be rewritten as
Kn
2
(Vin  VT 0 , n ) 2 
Kp
2
2(V
in
 V DD  VT 0 , p )(Vout  V DD )  (V out  V DD ) 2

(2.8)
Differentiating (2.8) with respect to Vin ,

dV
dVout
K n (Vin  VT 0 , n )  K p  (V in  V DD  VT 0 , p ) out  (Vout  V DD )  (Vout  V DD )
dVin
dVin





(2.9)
Substituting Vin  V IL and dVout / dVin  1 into (2.9), and solving for V IL yields
V IL 
2Vout  VT 0 , p  V DD  K R VT 0, n
1 K R
(2.10)
where K R is defined as K R  K n / K p . Equation (2.10) is solved together with (2.8) to
obtain the numerical value of Vout and V IL .
Calculation of VIH
When the input voltage is equal to V IH , the nMOS transistor operates in the linear region
and the pMOS transistor operates in saturation. Applying KCL to the output voltage gives
Kn
2
2(V
GS , n

2
 VT 0 , n )VDS , n  V DS
,n 
Kp
2
(VGS , p  VT 0 , p ) 2
(2.11)
Using, VGS ,n  Vin , V DS ,n  Vout , VGS , p  (V DD  Vin ) and V DS , p  (V DD  Vout ) , equation (2.11)
can be rewritten as
Kn
2
2(V
in

2
 VT 0 ,n )V out  Vout

Kp
2
(V in  V DD  VT 0 , p ) 2
(2.12)
Differentiating (2.12) with respect to Vin yields

dV
dVout
K n  (V in  VT 0, n ) out  V out  V out
dVin
dVin


  K p (Vin  V DD  VT 0, p )


(2.13)
Substituting Vin  V IH and dVout / dVin  1 into (2.13), and solving for V IH yields
V IH 
V DD  VT 0, p  K R ( 2V out  VT 0 , n )
1 K R
(2.14)
Again (2.14) is solved together with (2.12) to obtain the numerical value of Vout and V IH .
Calculation of Vth
The inverter threshold voltage is defined as Vth  Vin  Vout . When Vin  Vout both transistors
are expected to be in saturation mode; hence the KCL equations can be written as
Kn
2
(VGS , n  VT 0 , n ) 2 
Kp
2
(VGS , p  VT 0 , p ) 2
(2.15)
Using, VGS ,n  Vin and VGS , p  (V DD  Vin ) , equation (2.15) can be rewritten as
Kn
2
(Vin  VT 0 , n ) 2 
Kp
2
( V in  V DD  V T 0 , p ) 2
(2.16)
Substituting Vin  Vth , and solving for Vth yields
VT 0 ,n 
V th 
1
(V DD  VT 0 , p )
KR

1 


1
KR




(2.17)
Note that when Vin  Vth , the output voltage Vout can be any value between (Vth  VT 0,n ) and
(Vth  VT 0, p ) . This is due to the fact that the VCT segment corresponding to region C in
Fig. 2.7 become completely vertical if the channel length modulation effect is neglected
(i.e.   0 ). If the channel length modulation is not neglected, the VCT in Region C
exhibits a very large slope. By appropriately sizing the MOS transistors, the
transconductance ratio K R  K n / K p can be controlled to set the threshold voltage Vth of
the inverter to a specific value as
Figure 2.8 Variation of the inversion threshold voltage as a function of K R
Figure 2.9 Typical VTC and the power supply current of a CMOS inverter circuit
KR 
Kn
Kp
W
 n C ox 
L

W
 p C ox 
L

W

n 
n
 L


W
p

p
 L


n


p
(2.18)
Fig. 2.8 shows the variation of the threshold voltage Vth as a function of transconductance
ratio K R  K n / K p , for fixed values of V DD , VT 0,n and VT 0, p .
The power supply current as a function of the input voltage is shown in Fig. 2.9. The
current being drawn from the from the power source during the transition reaches its peak
value when Vin  Vth .
Design of CMOS Inverters
The inverter threshold Vth is one of the most important parameters that characterize the
steady-state input-output behaviour of the CMOS inverter. Given the power supply
voltage V DD , the nMOS and pMOS transistor threshold voltages VT 0,n and VT 0, p , and the
desired threshold voltage Vth for the inverter, the corresponding transconductance ratio
K R can be found by reorganizing (2.17) as
KR 
Kn
Kp
 V DD  VT 0 , p  V th


V th  VT 0, n





2
(2.19)
Recall that the switching threshold voltage of an ideal inverter is defined as
Vth ,ideal  V DD / 2 , thus (2.19) is expressed as
KR 
Kn
Kp
 0. 5V DD  VT 0, p

 0 .5V DD  VT 0 , n





2
(2.20)
The operation of the nMOS and pMOS transistors of the CMOS inverter can achieve
symmetric input-output characteristics by setting the threshold voltages as
VT 0  VT 0, n | VT 0, p | . This reduces (2.20) to
K 
KR  n 
1
 K p  symetric

 inverter
(2.21)
Note that K R is defined by selecting the size of the MOS transistors using (2.19).
Assuming that the oxide thickness t ox , and hence, the gate oxide capacitance C ox have the
same value for both nMOS and pMOS transistors. The unity ration of (2.21) for the ideal
symmetric inverter requires that
W 
 
p
230cm 2 / V  s
 L n


W 
n
580cm 2 / V  s
 
 L p
(2.22)
Hence
W 
W 
   2. 5 
 L p
 L n
(2.23)
The numerical values used in (2.22) for the electron and hole mobility are typical values
and that exact  n and  p values will vary with the surface doping concentration of the
substrate. The VTCs of three CMOS inverter circuits with different K R ratios are shown
Fig. 10. It can be seen the threshold voltage Vth shifts to lower values as K R increases.
For a symmetric CMOS inverter with VT 0,n | VT 0, p | and K R  1 , the critical voltage V IL
can be found by solving (2.8) and (2.10) which yields
V IL 
1
(3V DD  2VT 0, n )
8
(2.24)
Similarly by solving (2.12) and (2.14), the critical voltage V IH is found as
V IH 
1
(5V DD  2VT 0,n )
8
(2.25)
Note that the sum of V IL and V IH is always equal to V DD in a symmetric inverter (i.e.
V IL  V IH  V DD ). The noise margins defined by (2.2) and (2.3) are:
NM L  V IL  VOL  V IL  0  V IL
NM H  VOH  V IH  V DD  V IH  V IL
(2.26)
Note the lower and upper noise margins are equal to each other ( NM L  NM H ).
Supply Voltage Scaling on the VTC of CMOS Inverters
The overall power dissipation of any digital circuit is a strong function of the supply
voltage V DD . Reducing or scaling the power supply voltage is one of the most widely
practiced measures for low-power design. This section examines the influence of the
supply voltage scaling upon the Voltage Transfer Characteristic (VTC) of a simple
CMOS inverter.
Neglecting second-order effects such as subthreshold conduction, the CMOS inverter
will continue to operate correctly with a supply voltage which is as low as the following
limit value.
min
V DD
 VT 0,n  | VT 0, p |
(2.27)
Fig 2.10 shows the VTCs of a CMOS inverter, obtained with different supply voltage
levels. The exact slope of the VTC near the limit value of (2.27) is essentially determined
by the subthreshold conduction properties of the nMOS and pMOS transistors, yet it is
clear that the circuit operates as an inverter over a large range of supply voltage levels.
Power and Area Considerations
The CMOS inverter does not draw any significant current from the power source voltage
in both steady state operating points (Vout  VOH and Vout  VOL ); thus the DC power
dissipation of this circuit is almost negligible. The drain current that flows through the
nMOS and pMOS transistors is essentially limited to the reverse leakage current of the
source and drain pn-junctions, and in short-channel MOSFETs, the relatively small
subthreshold current. However, leakage currents can become significant in deep submicron technologies. The low DC power of the CMOS inverter is one of the main
advantages of this configuration, when compared to other configurations such as nMOS
logic circuits. The CMOS inverter do however, conduct significant amount of current
during a switching event (when output changes from low to high or vice versa). The
detailed calculation of this dynamic power dissipation will be examined in next chapter.
Due to the complementary nature of CMOS logic circuits, they tend to occupy more
area when compared to nMOS logic circuits.
Figure 2.10 Voltage Transfer Characteristics (VTCs) of a CMOS inverter, obtained with
different power supply voltage levels.