BUILDING BLOCKS OF A
BASIC MICROPROCESSOR
Part 1
PowerPoint Format of Lecture 3 of Book
1
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Decoder
Tri-state device
Full adder, full subtractor
Arithmetic Logic Unit (ALU)
Memories
Example showing how to write to a memory
Homework assignments
2
• Recall concept of a decoder
• Interpret as a “function decoder”
3
• In many digital systems it is required to connect
multiple output devices onto the same wire or
group of wires
• Problem: What happens when two or more
devices attempt to drive different voltages on the
same wire (or group of wires, i.e., a bus)
– Result: line (or bus) contention, damage to circuit.
4
• For example, consider two devices Device A and Device B
need to send voltages to Device C
• What would happen if A sent +5 V and B sent 0 V at the
same time?
– Line contention: it’s like Device A’s positive terminal power
supply is connected to ground. Not good!
Common Ground
5V
Device A
Device B
Device C
5V
Output Devices
Voltage Source
Input Device
Voltage Sink
5
A SOLUTION: TRI-STATE BUFFER
6
APPLICATION OF TRI-STATE BUFFER
Device A
Device B
Write Control
Active low
tri-state
buffer
Device C
Active high
tri-state
buffer
• Only one device is allowed to output a voltage (0V
or 5V) at one time.
7
Number A
_ _ _ _ x _ _ _
Number B
_ _ _ _ y _ _ _
Carry In
_ _ _ _ Cin _ _ _
Sum
_ _ _ _ S _ _ _
Carry Out
_ _ _ _ Cout _ _ _
Truth Table
Cin
0
Add
1-bit Binary
Number
Wheel
x + y + C in
Arithmetic Sum
1
Cout
S
0
0
0
From a Karnaugh map:
0
1
1
0
0
0
1
1
S= x y z + x yz +x y z +x y z
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
x
y
0
0
0
0
FULL
ADDER
Logical OR
Cout = x y + x z + yz
Cin
x
Full Adder Block Diagram
y
S
FA
Cout
8
Number A
_ _ _ _ x _ _ _
Number B
_ _ _ _ y _ _ _
Borrow In
_ _ _ _ Bin _ _ _
_ _ _ _ D _ _ _
Difference
Borrow Out
_ _ _ _ Bout _ _ _
Truth Table
Bin
0
x - y - Bin
1-bit Binary
Number
Wheel
Arithmetic
Difference
1
Bout
D
0
1
0
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
1
1
0
1
1
0
0
0
0
0
Bout = x y + x z + yz
1
1
1
1
1
Cout = x y + x z + yz
x
y
0
0
0
0
0
Subtract
From a Karnaugh map:
D= S = xyz+ xyz+ xyz+ xyz
Logical OR
Bin
x
Full Subtracter Block Diagram
y
D
FS
Bout
9
3 2 1 0
Number A
1 0 1 1
Ai
Number B
0 0 1 1
Bi
0
Ci
Carry In
Sum
Si
Carry Out
Ci+1
B3
C4
A3
FA
B2
C3
Add
1-bit Binary
Number
Wheel
1
A2
FA
S3
0
B1
C2
S2
A1
B0
C1
FA
S1
A0
FA
S0
0000
1111
1110
1101
0010
0011
4-bit Binary
Number wheel
1100
Add
0001
C0
May be extended to n-bit full adder
i
0100
1011
0101
1010
0110
1001
0111
1000
10
4-BIT ARITHMETIC LOGIC UNIT (ALU)
SIMPLIFIED FUNCTIONAL DESCRIPTION
OUTPUTS
Cout
C
SWITCH (MUX)
B
4 FA
F
4 FS
4 AND
4 OR
…
A
B
TWO 4-BIT NUMBERS
MS3S2S1S0CIN
FUNCTION SELECTOR
INPUTS
11
BITWISE AND and OR CIRCUITS (ALU)
A3
B3
A2
B2
A1
F3
F2
B3
A2
B2
A1
F1
B1
B1
A0
B0
A3
F0
A0
B0
• Other functions such as XOR, NAND, NOR, and NOT are similarly
implemented.
F3
F2
F1
F0
12
ALU FUNCTION TABLE
EXAMPLE 4-BIT
S3
S2
S1
S0
LOGIC
M=1
ARITHMETIC
M=0
0
0
0
0
A’
A
0
0
0
1
B’
B
0
0
1
0
A AND B
A PLUS B
0
0
1
1
A OR B
A MINUS B
0
1
0
0
A NAND B
A+1
0
1
0
1
A
A-1
0
1
1
0
B
B+1
0
1
1
1
A XOR B
B-1
13
OPTIMIZED VERSION
R3
R2
R1
R0
ADDS 1 TO OPERANDS
WHEN ADD/SUB = 1
CONTAINS 4-BIT FA (NO FS), AND LOGIC CIRCTUITS
C3
A3
A2
A1
C0
A0
MOST SIGNIFICANT
CARRY OR BORROW
B3
B2
B1
B0
ADD/SUB
CONTROL
PERFORMS 1S COMPLEMENT OF B WHEN ADD/SUB = 1
A – B = A + 2s(B)
14
• In this course, we do not use the optimized, 2’s
complement ALU.
– The optimized version does not contain a FS circuit.
• We use the non-optimized, basic ALU, which does
contain a FS circuit.
• This means that in this course, the ALU uses a FS
circuit to perform subtraction.
15
• There are three types of memories:
– Flip Flop (FF) (1-bit storage)
– Register (n-bit storage)
– Memory (m-words by n-bits of storage)
16
MEMORY (SEQUENTIAL) CIRCUITS
17
WAYS TO TRIGGER A FLIP FLOP
LATCH
FLIP FLOP
18
REGISTER
•
•
Can be designed as a group of flip flops
Example: 4-bit register, or a 4-bit word
19
WRITING TO A REGISTER
20
WRITING TO A REGISTER
Write
Timing
Diagram
Data Input
D3D2D1D0 Valid
OE (optional)
CLK (external)
CLK (internal)
Q3Q2Q1Q0
Q3Q2Q1Q0 Valid
21
READING FROM A REGISTER
Read
Timing
Diagram
OE
Q3Q2Q1Q0
O3O2O1O0 Valid
• Note: other control designs are possible:
– For example, R/W and OE could be input to a 2-input AND gate, whose output could be
connected to the Enable pins of the tri-state buffers.
22
MEMORY
Example: 8 x 4 Memory
Eight Words, and each word has 4-bits
Address
3-bit
000
001
8 x 4 Memory
8 = 23 words, and each word has 4-bits
Data
4-bit Words
0
0
0
1
0
1
1
0
A0
010
1
0
1
1
A1
011
0
1
0
0
A2
100
0
1
0
1
101
1
0
1
0
110
0
1
0
0
111
1
1
1
0
D0
D1
D2
D3
R/Wn
OE
CS
Block Diagram Representation
23
m x n MEMORY
m x n Memory
m = 2k words, and each word has n-bits
A0
D0
A1
D1
Ak-2
m by n
Memory
.
.
.
Dn-1
Ak-1
OE
CS
24
WRITING TO MEMORY
25
READING FROM MEMORY
26
EXAMPLE: 4X3 MEMORY
Example: 4 x 3 Memory
Four Words, and each word has 3-bits
Address
2-bit
00
01
4 x 3 Memory
4 = 22 words, and each word has 3-bits
Data
3-bit Words
0
0
0
1
0
1
A0
A1
10
1
0
1
11
0
1
0
D0
D1
D2
R/Wn OE CS
Block Diagram Representation
27
BLOCKING AND ENABLING PROPERTY OF
AND GATE
E
Y
X
If E =1, then Y = X (Enable)
If E =0, then Y = 0 (Block)
Example Application: Clock Enable
E
CLK
Y
If E = 1, then Y =
If E = 0, then Y = 0
28
D0
A1
D1
A0
D2
R/Wn
CS
OE
Input data pins and
output data pins are
separated to simplify
the analysis.
29
EXAMPLE
• Goal: Write 0b101 to location 0b10, i.e., write 5 to
location 2.
• End result should be:
D0
A0
A1
D1
101
R/Wn
D2
CS
OE
30
1
0
1
Step 1: Setup data word: 0b101
Data
101
Address
R/Wn
CS
At this point in time, the
voltages (data) are
applied to pins I2-I0.
0
0
‘0’ = 0 V
‘1’ = 5 V
31
1
0
1
1
0
1
1
0
1
Step 1: Setup data word: 0b101
Data
101
Address
1
0
1
R/Wn
CS
1
0
1
At this point in time, the
voltages have flowed to
the inputs of the FFs.
0
0
‘0’ = 0 V
‘1’ = 5 V
32
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
Data
0
1
0
0
0
1
0
R/Wn
0
1
0
0
1
0
0
0
1
0
Step 1: Setup data word: 0b101
101
Address
CS
Also at this point in time,
the 0 V applied to pin CS
has forced 0 V at the CLK
inputs of the FFs.
‘0’ = 0 V
‘1’ = 5 V
33
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
Data
101
Address
10
R/Wn
CS
At this point in time, the
address applied to pins
A1-A0 has flowed to the
Word Select gates.
‘0’ = 0 V
‘1’ = 5 V
34
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
0
Data
101
Address
0
10
R/Wn
CS
1
0
Due to {A1A0} = {10},
Word 2 Select Line is the
only active word select
line.
‘0’ = 0 V
‘1’ = 5 V
35
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
Step 3: Select write mode
0
Data
101
Address
0
10
R/Wn
CS
1
0
1
R/Wn is normally low
(0), so write mode is
selected.
‘0’ = 0 V
‘1’ = 5 V
36
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
0
0
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
Step 3: Select write mode
Step 4: Trigger the circuit by
making CS=1
Data
101
Address
0
1
1
0
1
1
10
R/Wn
CS
At this point in time, the
Write gate at Word 2
becomes ‘1’.
‘0’ = 0 V
‘1’ = 5 V
37
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
Step 3: Select write mode
Step 4: Trigger the circuit by
making CS=1
Data
101
Address
0
1
1
0
1
10
R/Wn
CS
Also at this point in time,
the CLK inputs to the FFs of
Word 2 undergo a position
transition.
‘0’ = 0 V
‘1’ = 5 V
38
0
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
Step 1: Setup data word: 0b101
Step 2: Setup address: 0b10
Step 3: Select write mode
Step 4: Trigger the circuit by
making CS=1
Data
101
0
Address
0
1
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
10
R/Wn
CS
Also at this point in
time, the data (101) is
written into the FFs of
Word 2.
‘0’ = 0 V
‘1’ = 5 V
39
HOMEWORK:
PERFORM A SIMILAR ANALYSIS FOR READ
• Show the incremental steps and timing diagram required to read the
data located at memory location 0b10.
D0
A0
A1
D1
101
R/Wn
D2
CS
OE
40
A BLANK
MEMORY FOR
YOU
41
HOMEWORK:
PROBLEM STATEMENT
• Design a circuit that stores the 5-bit result of the last addition
operation performed by a 4-bit full adder (FA) to an 8 words x 4-bit
memory.
• Use an 8x4 memory that has similar control signals as the 4x3
memory given in the previous slides.
• Store the 5-bit result as follows:
– Step 1: store the MSb of the 5-bit result to Bit-0 of address 000 of the memory.
Ensure that the other bits of address 000 are set to zero.
– Step 2: take the 4-bit output of the 4-bit FA circuit and store it at address 001 of
the memory.
– Use a given clock signal to execute the above steps and write to the memory.
42
HOMEWORK:
PROBLEM STATEMENT PICTORIALLY
CLK
Result
Given
0 0 0 C
F3F2F1F0
C
F3
F2
F1
F0
D0
A0
Your Circuit
D1
A1
D2
A2
D3
ALU
R/Wn
OE
CS
43
HOMEWORK:
YOUR SOLUTION
44