Design and Verification of
Information Flow Secure Systems
PhD Defense
Mohit Tiwari
University of California, Santa Barbara
Design and Verification of
Information Flow Secure Systems
Committee
Tim Sherwood (Chair)
Frederic T Chong
Tevfik Bultan
Ben Hardekopf
Ryan Kastner
UC Santa Barbara
UC Santa Barbara
UC Santa Barbara
UC Santa Barbara
UC San Diego
High Assurance Systems
Passenger Network
Open Network
Flight Control Network
Confidential Data
Enforce policies on final system implementation
High Assurance for All
Sensitive data. Untrusted services.
Confinement Problem [Lampson’73]
Non-Interference
• Non-Interference: a change in a High input can never
be observed or inferred from changes in the Low
output. That is, High data should never leak to Low
• Confidentiality-Integrity Duality: “High” is more
conservative label. Secret or Tainted/Untrusted.
High
X
Low
Low
“system”
Real-world systems need both Confidentiality and Integrity
Example MLS System
Example Satellite Application. [Tzvetan Metodi, Aerospace Corp.]
Interrupt Handlers (Sensitive)
Interrupt Handlers (Non-sensitive)
Kernel and
Diagnostics
Time
Keeping
Crypto
Command
Telemetry
Interface
I/O
Secret
Mission
Secret
Mission
Unclass.
Primary Execution Schedule
Execution Time
Note: Since this is not a real schedule, the processes are not in any sensible execution order
Non-sensitive
Sensitive
Example: Satellite System
Untrusted & Secret
Libraries (e.g. encryption) that operate on Secret data
Untrusted & Unclassified
Diagnostics, Telemetry Interfaces
Trusted & Secret
Custom code on Secret data
Trusted & Unclassified
Kernel, Interrupt Handlers (Unclassified), Time Keeping Programs
But assurance is not cheap
The Price of Assurance
• Evaluation Assurance Levels (EAL 1—7)
– Evaluation of process, not end artifact
• RedHat Linux: EAL 4+
– $30-$40 per LOC
• Integrity RTOS: EAL 6+
– $10,000 per LOC
… and increasing. Many approaches.
Traditional Information Flow Security
Applications
Prog. Language
Compiler/OS
Instruction Set
Microarchitecture
Volpano96, Jif99, Slam98, FlowCaml03
HiStar 06, Flume 07, Laminar 09
Taintcheck 04, LIFT 06, Dytan 07
DIFT 04, Minos 04, LBA 06, Raksha 07
Cache-flush: Osvik et. al. 2006...
BP Scrub: Aciicmez et al. 2007...
Exe Normalize: Kocher 1996…
Cache Rand: Lee et al. 2005...
Functional Units
Logic Gates
Closer look at IF analysis.
Information Flow Analysis
• Information flows through Space
– Registers, Memory, Micro-architectural state etc.
• Information flows through Time
– Observable events such as PC, I/O channels etc.
if (untrusted == 1)
out1 = 1
Memory
outto=account
untrusted
How
for all information
else flows in a system?
out2 = 0
(explicit
flow)
How to construct practical systems that won’t leak?
(implicit flow)
CPU A
CPU B
Outline of this talk
• High Assurance Systems
– Information flow security
• Analysis Technique:
– Gate-Level Information Flow Tracking
• Architecture
– Execution Leases
Analysis: Track all flows
clock
P1
P0
S/W
H/W
state
1001110101111011
0001011001111111
external
inputs
001000101
Separation Kernel
I/O Dev
Mem
Combinational Logic
CPU
external outputs
Secure System
Equivalent State Machine
• Flatten design to a (giant) state machine
• Does every output have desired label?
Analysis: Track all flows
clock
P1
P0
S/W
H/W
state
1001110101111011
0001011001111111
external
inputs
001000101
Separation Kernel
I/O Dev
Mem
CPU
external outputs
Secure System
Equivalent State Machine
• Insight: All flows explicit at the gate level
Analysis: Track all flows
clock
P1
P0
S/W
H/W
state
1001110101111011
0001011001111111
external
inputs
001000101
Separation Kernel
I/O Dev
Mem
CPU
external outputs
Secure System
Equivalent State Machine
• Outputs: Logic function of state and inputs
• Output Labels: Logic func. of state, inputs, and labels
Analysis: Track all flows
clock
P1
P0
S/W
H/W
state
1001110101111011
0001011001111111
external
inputs
001000101
Separation Kernel
I/O Dev
Mem
Combinational Logic
CPU
external outputs
Secure System
Equivalent State Machine
• Does not include physical side-channels
– Power draw, Thermal fingerprint, EM radiation
Timing Channels
Memory
Request A
Bus Arbiter
Request B
CPU B
CPU A
Grant A
Grant B
…Will look at implicit flows in a few slides.
Analysis Technique: GLIFT
a b
at b t
o
ot
AND
Shadow AND
Required: Precise Information Flow
D
reset
Q
010101…
clock
• Conventional OR-ing of labels monotonic
Precise Information Flow: AND Gate
1 1
0
0
a
b
o
0
1
a
b
o
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
Use both inputs and input labels
Analysis Technique: GLIFT
at bt
a b
at bt
o
ot
b
ot
a
Sound Composition of Shadow Logic
s t at
a
s t bt
b
s
a
s
t1
t1
t2
o
ot
t2
b
s
MUX: gatekeeper of trust
a
s
0
s
o
b
a
b
a
b
*
s
1
o
o
All Executions: Track “Unknowns”
• Known bits at security evaluation time
– Software kernel
– Hardware design
• Unknown bits
– External inputs
– User processes
• Verify policy upheld for all unknown bits
– Use abstract interpretation to prove soundness
0 *
a
0
1*
a
*
GLIFT Verification Flow
Digital Design
Abstract Design
labeled inputs
abstract inputs
clock
test inputs
**
01
clock
Augmented Design
1T0T
10**
1011
1. Abstraction
a
**
U U
*state
*
state
state
U U
clock
a
2. Augmentation
L
L
a
output
10**
state
**
input
Specification of
unknown bits
1*
abstract output
L
U
U T
1
*
labeled output
T
Information
flow lattice
Concrete state must be enumerable. E.g. Scheduler loop
Outline of this talk
• High Assurance Systems
– Information flow security
• Analysis Technique:
– Gate-Level Information Flow Tracking
• Architecture
– Execution Leases
Implicit Information Flows
+4
PC
jump target
if (untrusted==1)
out = 1
tmp = 5
is jump?
Instr Mem
Reg
File
through
decode
R2
R1
Conditional execution taints critical state (PC)
Untrusted Code and Conditionals
state becomes
• Problem:
Lease theCritical
CPU toCPU
programs
for fixed untrusted
time with bounded
memory access
Memory
Lease
= Space-Time
Sandbox
Stack
of Nested Leases
Time
Execution Lease Architecture
timer expired?
Lease Unit
restore PC
0
PC
Timer
0
+4
1
jump target
1
PC
Memory
old value
Instr Mem
Predicates
Data Memory
R2
Reg File
through
decode
R1
high
low
Execution Lease Architecture
timer expired?
Lease Unit
restore PC
0
PC
Timer
0
+4
1
jump target
1
PC
Memory
old value
Instr Mem
Predicates
Data Memory
R2
Reg File
through
decode
R1
high
low
Execution Lease Architecture
timer expired?
Lease Unit
Restore PC
0
+4
1
jump target
1
PC
Timer
0
PC
Memory
old value
Instr Mem
Predicates
Data Memory
R2
Reg File
through
decode
high
low
R1
Registers become untainted with trusted loads
Designing for GLIFT- 1. Trusted Reset
timer exprired?
Restore PC
0
PC
Timer
0
+4
1
jump target
1
Lease
Unit
PC
Range
old value
Instr Mem
Predicates
Data Memory
R2
Reg File
through
decode
R1
high
low
Designing for GLIFT: 2. Isolation
Store value
Mem Bound Start
0b10
…
Address
Comparators
WL
EN
>=
ADDR
0b00
Tainted Store Addr
<=
0b11
…
Mem Bound End
Decoder
BL
BL
Designing for GLIFT: 2. Isolation
Store value
0b1*
Mem Bound Range
Address
Bit-Mask
…
WL
EN
Address
0b10
0b00
Tainted Store Addr
…
Decoder
BL
BL
Designing for GLIFT: 3. Critical State
timer exprired?
Restore PC
0
PC
Timer
0
+4
1
jump target
1
Lease
Unit
PC
old value
Instr Mem
Predicates
Reg
File
through
decode
R2
R1
high
low
Data
Memory
Range
Designing for GLIFT: 3. Critical State
• Stack of Nested Timers
timer exprired?
Restore PC
• Timer values: bad
Lease
Unit
Timer
• Stack pointer: good
• Huge effect on software
• Arbitrary timer values => no encoding overhead
• Save and restore timers => multi-level schedulers
PC
Range