新聞
SPTS Technologies announces the Omega® Rapier XE system for
300mm wafer silicon etch processing
SPTS Technologies announces the Omega® Rapier XE system for 300mm
wafer silicon etch processing
SPTS Technologies, a supplier of advanced wafer processing solutions for the
global semiconductor industry and related markets, announced the launch of its
Rapier XE system for 300mm wafer silicon etching. The new module offers
significant advantages over competing systems as well as improved etch rate over the
1st generation Rapier in applications where “blanket” etching or removing a large
exposed area of silicon is required, such as via reveal processing.
In 3D-IC applications, via reveal processing occurs after the through silicon vias
(TSVs) are formed, to prepare the vias for redistribution metallization. After
completion of front-side wafer processing, the wafer is temporarily bonded, face
down, onto a carrier wafer. The active silicon is then ground typically to within 5-10
μm of the TSV nodes. The silicon is then dry etched in a process that ‘reveals’ the
vias to a step height typically in the range 2-5µm. To maximize yield, it is critical that
all vias are revealed to a uniform height, which can be extremely challenging if the
incoming wafer thickness varies across a wafer or from one wafer to the next. In the
1st generation Rapier and now the new Rapier XE system, issues of wafer-to-wafer
silicon thickness variation is overcome with the use of the ReVia™ endpoint system.
Source: i-MicroNews