Fakulti:
Nama Matapelajaran :
Kod Matapelajaran :
FAKULTI KEJURUTERAAN ELEKTRIK
Semakan
Tarikh Keluaran
Pindaan Terakhir
No. Prosedur
:1
: 2003
: 2003
: PK-UTM-FKE-(0)-10
SEL/W 4722
FAKULTI KEJURUTERAAN ELEKTRIK
UNIVERSITI TEKNOLOGI MALAYSIA
KAMPUS SKUDAI
JOHOR
VLSI CAD LABORATORY
Design of a 4-bit counter
Disediakan oleh
Nama
Tandatangan
Cop
:
: Dr. Nasir Shaikh Husin
:
:
Disahkan oleh
Nama
Tandatangan
Cop
:
:
:
:
Tarikh
: Sep. 2012
Tarikh
:
Project Introduction:
VLSI design involves drawing of transistor layout. Knowledge on how to design transistor layout is
very crucial for VLSI designers. In this project, you are required to design and layout a 4-bit counter.
You are required to use Cadence EDA software in this project.
Project tasks:
Design a 4-bit counter. Specifications are as follows:
• counter counts only nine digits, then repeats the sequence
• you are not allowed to count consecutive numbers, for example 0 to 8, or 8 to 0, or 2 to 10 and so on
• you must choose a unique sequence – sequence not chosen by any other group
• you can use any flip-flop – with or without clear, preset, etc is up to you
• you can choose any logic style
Draw either state diagram or ASM chart. Design gate level circuit and verify its operation through
Quartus II. Identify logic gates and flip-flop that you have to use. Draw layout of these components.
Choose transistor sizes to conform to Silterra 0.18 µm fabrication process. Make sure your layout is
free from any design rule violations and the layout represents the circuit schematic correctly.
Characterize your flip-flop by measuring its tclk→Q delay. Finally, connect the components to produce
your counter. Then, extract your layout, including parasitic capacitances and simulate the circuit to
verify correct operation.
Tasks that you must do:
• Design counter at gate level and verify its correct operation using Quartus II.
• Draw the circuit schematics for the components. Specify your transistor dimension.
• Simulate the components and verify their correct functionality.
• Create layout for the components. You must follow Silterra design rules.
• Perform a Design Rules Check (DRC) on each layout.
• Perform a Layout Versus Schematic (LVS) on each layout.
• Extract each layout and simulate the netlist to verify correct functionality.
• For flip-flop, also measure the tclk→Q delay.
• Extract layout of your counter and verify that it counts correctly.
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