C1104 Exam SUGGESTED Solutions
Confidence Factor: 10
Answer:
Generally OR-ing any two dis-similar maxterms will result in a final answer of 1.
This is because with two maxterms Mi and Mj, i j, then there will be some variable
v which exists as v in Mi and v’ in Mj, and combining Mi + Mj will give us v + v’ = 1.
E.g. M2 + M4 in 3 bit binary will give us (a + b’ + c) + (a’ + b + c), giving us:
a+a’ + b’+b + c + c
=1+1+c
=1
Likewise AND-ing any two dis-similar minterms will result in a final answer of “0”.
Confidence Factor: 10
Answer:
Taking the n’s complement of any base n involves just taking 100n – mn.
So taking the 7’s complement of a base 7 number:
1007 – 537 = 147
Confidence Factor: 8
m56 = abcd’e’f’
Those that differ by one literal:
a’bcd’e’f’, ab’cd’e’f’, abc’d’e’f’, abcde’f’, abcd’ef’, abcd’e’f. Convert these to
minterms (m56 etc.) to get your answer.
Confidence Factor: 10
Time taken = Tcontroller + Tseek + Trotlat + Txfer
Find Trotlat first:
10000 RPM = 166.67 RPS
Time for 1 full rotation = 5.9 ms
Trotlat = ½ x time for full rotation = ½ x 5.9 = 2.95 ms
Txfer = 8KB / 20MBPS
= 8192/(20 x 10^6)
= 0.41 ms
Total time = 2ms + 10ms + 5.9 ms + 0.41 ms = 18.31 ms.
Note that you can use 8000/(20x10^6) also for simplicity. The relative error is
192/8192 = 2.34%.
Confidence Factor: 9
Answer:
d) Txmit = Toverhead + Txfer
= 460 s + (400*8)/(10x10^6)
= 780 s
Since overheads are significant, larger packet sizes are preferable.
Confidence Factor: 6
e) Need to transmit 4000 bits/s
Packet size of 400 bytes = 3200 bits.
Need to split 4000 bit/s to 2 packets.
Each packet will take 460 s overhead and 780 s transmission (note that second
packet will be padded if there is insufficient data from the sample). Thus
transmission time is 780 s x 2 = 1560 s.
Packet sizes have little effect here.
Confidence Factor: 10
Answer:
i) Amdahl’s Law, not covered.
ii)
R type has 3 register operands each with 5 bits, giving 15 operand bits
I type has 2 register operand of 5 bits each, 16 bits immediate operand,
giving 26 bits.
J type has 26 bits address operand.
So R-type has fewest operand bits.
iii) MIPS uses instruction format I to encode conditional branch instructions.
iv) Not covered. 2 instructions (lui, ori) are needed.
v) Each array element is 4 bytes, so the actual address is 1000 + 15 x 4 = 1060.
vi) This is not covered, but the value in the immediate field represents the number of
instructions to jump over. Between the address of the beq (1000), and the target
address (2000), there will be (2000 – 1000)/4 = 250 instructions (each instruction
takes 4 bytes).
vii) Not covered. You can get more range by trading off accuracy.
Confidence Factor: 10
(1) M1 & C1:
CPI = 0.3 x 1 + 0.2 x 2 + 0.4 x 2 + 0.1 x 4 = 0.3 + 0.4 + 0.8 + 0.4 = 1.9
(2) M2 & C2:
CPI = 0.5 x 2 + 0.2 x 1 + 0.1 x 3 + 0.2 x 5 = 1.0 + 0.2 + 0.3 + 1.0 = 2.5
(3) M1 & C2:
CPI = 0.5 x 1 + 0.2 x 2 + 0.1 x 2 + 0.2 x 4 = 0.5 + 0.4 + 0.2 + 0.8 = 1.9
Confidence Factor: 10
TM1 = 1/(400 x 10^6) = 2.5 ns
TM2 = 1/(200 x 10^6) = 5 ns
TC1M1 = 1200 x 1.9 x 2.5 = 5700 ns
TM2C2 = 1600 x 2.5 x 5 = 20000 ns
TM1C2 = 1600 x 1.9 x 2.5 = 7600 ns
CPI of M2 & C1:
CPI = 0.3 x 1 + 0.2 x 2 + 0.4 x 2 + 0.1 x 4 = 0.3 + 0.4 + 0.8 + 0.4 = 1.9
TM2C1 = 1.9 x 1200 x 5 = 11,400 ns
Fastest is C1 on M1.
Confidence Factor: 10
(b)
We are finding minterms, and hence can concern ourselves only with combinations
of x,y and z that produce a 1.
We can derive the following equation;
F
= x’y’ + z’(x’y + xy)
= x’y’ + x’yz’ + xyz’
= x’y’(z + z’) + x’yz’ + xyz’
= x’y’z + x’y’z’ + x’yz’ + xyz’
= m0 + m1 + m2 + m6
Otherwise just try various values of x,y,z and see which ones produce a ‘1’.
(c)
By inspection we can derive:
H = x’y’z’ + xyz’ = m0 + m6
Or use various values of x,y,z and see which ones give a ‘1’.
Confidence Factor: 10
The mistake will be exposed when a=0 and c=1 or vice versa, with b being either 0
or 1. So the possible wrong inputs are:
(cba) = (001), (011), (100), (110)
(001) is o/p 1 which is unconnected. 011 is o/p 3 which is unconnected. 100 is o/p 4
which is unconnected, 110 is o/p 6 which is connected. Correctly connected, 110 is
supposed to be (011) (he reversed the a and c), which is not part of our function.
Hence his mistake will appear when (cba) = (110).
(c)
Confidence Factor: 2
Hint is that the capacity misses for the full-associate cache is 0, meaning that the
number of accesses < number of cache blocks.
Conflict misses for fully associative cache: 0
- FA caches do not suffer from conflict misses because different addresses
will go to different blocks, as long as there are free blocks available.
Capacity Misses for Direct Mapped Cache: 0
-
Misses in DM cache are independent of capacity.
Conflict Misses for DM Cache: C1 – X
-
Aside from the compulsory misses, all other misses are conflict.
(d)
Confidence Factor: 6
For VM:
-
Disk space is cheap. Trivial to set aside huge amounts of disk space for
VM.
-
Having huge VM will allow us to write more and more complex programs
because you will still be able to fit many of these programs into the VM
even if each program were larger than the main memory. So even if we
have 64 GB of main memory, having 256GB of VM will allow us to have
many more big complicated programs running than if we were to use the
64 GB of main memory only.
-
VM supports memory protection between users (theoretically can be
done with main memory, but much harder since main memory is purely
hardware. Memory protection in VM is often done in software since VM
is partly software partly hardware).
Against VM:
-
VM is slow, impacts performance of the memory hierarchy.
-
VM support can be complicated, slowing down the OS.
-
Complicated to build hierarchies with VM (what if a cache miss also
results in a page fault? What if a cache miss results in a TLB miss results
in a page fault? etc.)
(a)
Confidence factor: 10
To find the speedup, suppose that there are n+1 instructions to be executed.
The first instruction will pass thru IF, RR ALU, DA, RW, taking 5 cycles to
complete. Subsequent instructions will effectively take only 1 cycle to
complete since while the first instruction was at RR, the second would be in
IF. When the first is in ALU, the second would be in RR and the third in IF.
So effectively the first instruction would take 5 cycles, subsequent
instructions would take 1 cycle.
Total number of cycles taken to execute n+1 instructions is then: 5+n
Average CPI = (5+n)/(n+1)
As ninf, (5+n)/(n+1)  1
Hence in an ideal pipeline average CPI is 1.
In a non-pipelined CPU, average CPI is 5. Hence speedup = 5/1 = 5x.
(b)
Confidence Factor: 10
The pipeline cycle time is always equal to the time of the slowest stage. This is
because even if one stage is faster than the next stage, it would have to wait
for the next stage to complete processing its instruction before the current
stage can hand over its instruction to the next stage. Likewise if the next
stage is faster than the current stage, the next stage would still have to wait
for the current stage to finish with its instruction before the next stage can
proceed.
In our example the RR stage can complete in 1ns, but has to wait for the
ALU to complete processing the previous instruction before RR can pass its
instruction on to ALU.
So the cycle time is 4 ns.
Confidence Factor: 8
Data hazard between i1 and i2. Data hazard between i3 and i2. Control
hazard between i3 and i4.