725G45 Exam Datorarkitektur och operativsystem

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Linköping University
24th
October 2013
725G45 Exam
Datorarkitektur och operativsystem
Jour : Arian Maghazeh (07 66 34 89 68)
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Admitted materials
o Dictionary between your native language and English
o Calculators or any type other electronic devices are NOT
allowed
General instructions
o You may answer in Swedish or in English.
o Write clearly, unreadable text will be ignored
o The exam is for 28 points. Your score from the exam will be
added to your score from the mid-term to give your total score.
o At least 19 points in the total score are necessary for passing
this course.
Page 1 of 4
Question 1. (4 points)
Consider the performance equation :
CPU time = Instruction Count x Clock Cycle Per Instruction x Clock Cycle Time
(IC)
(CPI)
(CT)
What can a programmer (as opposed to a hardware architect) influence out of IC,
CPI and CT in order to influence performance? You must explain why.
Question 2. (3 points)
Categorize each of the following 3 instructions into either R-type or I-type
instruction format:
sub, addi, sw
Question 3. (3 points)
What is a system call? Give an example. Is it the same as an interrupt?
Question 4. (2 points)
How does virtual memory ensure that two different processes would not write into
each other’s address space?
Question 5. (2 points)
Who gets the control when there is a page-fault (with regards to virtual memory –
is it the operating system or is it the hardware? Why?
Page 2 of 4
Question 6. (3 points)
The instruction cache has a miss rate of 4%, data cache miss rate of 10%.
The CPI = 1.0 for a processor with a perfect cache with no miss. 20% of
instructions are loads and stores, and the miss penalty = 12 cycles.
What is CPI of the processor with the imperfect cache? Show the contribution to
miss penalty from instruction cache and the data cache.
Question 7. (4 points)
For the MIPS datapath below, several lines are marked with ‘X’. For each one
describe in words the negative consequence of cutting this line.
Page 3 of 4
Question 8. (4 points)
Given the MIPS assembly language instructions in the following two cases, write
the corresponding C/Java language statement for both of them. Write only the
arithmetic statement and not the variable declarations.
For both cases, also give the end value of the register f if f, g, h, i have the
values 1, 2, 3, and 4.
(a) addi f, f, 4
(b) add f, g, h
add f, i, f
Question 9. (3 points)
Suppose we have two different I/O systems A and B. A has data transfer rate:
5KB/s and has access delay: 5 sec. While B has data transfer rate: 3 KB/s and
has access delay: 4 sec. Now we have a 3M I/O request, taking performance into
consideration, which I/O system will you use? What about for a 3KB request?
Access delay in an I/O system means the delay required in initializing the I/O
system. During the initialization, no data is transferred. After the initialization, the
data is transferred with the given data transfer rate.
Page 4 of 4
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