IA-32 Architecture
Computer Organization and Assembly Languages
Yung-Yu Chuang
2005/09/29
with slides by Kip Irvine and Keith Van Rhein
Virtual machines
Abstractions for computers
High-Level Language
Level 5
Assembly Language
Level 4
Operating System
Level 3
Instruction Set
Architecture
Level 2
Microarchitecture
Level 1
Digital Logic
Level 0
All possible 2-input Boolean functions
S
Truth tables
X
• Example: (Y  S)  (X  S)
mux
Z
Y
Two-input multiplexer
4-multiplexer
x0
x1
x2
4MUX
x3
s0
s1
z
4-multiplexer
x0
x0
x1
x1
x2
4MUX
x3
z
2MUX
x2
x3
s0
2MUX
2MUX
s1
s0
s1
z
Comparator
x>y
CMP
x=y
x<y
x
x
y
y
x>y x=y x<y
8-bit comparator
xn>yn
xn=yn
x>y
CMP
xn<yn
x=y
x<y
x
y
1-bit half adder
x
c
ADD
y
x
y
s
s
c
1-bit full adder
x
y
ADD
Cout
s
x
Cin
y
Cin Cout s
8-bit adder
Registers and counters
EN(RD)
EN(RD)
IN
IN
REG
OUT
SET
INC
z0
s0
s1
SET
COUNTER
z1
DEC
z2
z3
OUT
Memory
8K 8-bit memory
Microcomputer concept
Basic microcomputer design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of
execution steps
• ALU performs arithmetic and logic operations
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
clock
control bus
address bus
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
Basic microcomputer design
• The memory storage unit holds instructions and
data for a running program
• A bus is a group of wires that transfer data from
one part to another (data, address, control)
data bus
registers
Central Processor Unit
(CPU)
ALU
CU
clock
control bus
address bus
Memory Storage
Unit
I/O
Device
#1
I/O
Device
#2
Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events
one cycle
1
0
• Basic unit of time, 1GHz→clock cycle=1ns
• A instruction could take multiple cycles to
complete, e.g. multiply in 8088 takes 50 cycles
Instruction execution cycle
program counter
instruction queue
PC
I-1
memory
op1
op2
program
I-2 I-3 I-4
fetch
read
registers
registers
write
decode
write
I-1
flags
ALU
execute
(output)
instruction
register
• Fetch
• Decode
• Fetch
operands
• Execute
• Store output
A simple microcomputer
DATA BUS
ACC
IR
B
MEMORY
I/O
PORT
I/O
DEVICE
DECODE
PC
ALU
I/O
DEVICE
FLAG
CONTROL
AND
SEQUENCING
ADDRESS BUS
CONTROL BUS
CLOCK
Instruction set
OPCODE
0
1
2
3
4
5
6
7
8
9
MNEMONIC
NOP
LDA
STA
ADD
SUB
IN
OUT
JMP
JN
HLT
OPCODE
4
OPCODE
A
B
C
D
OPERAND
12
MNEMONIC
CMP
JG
JE
JL
Control bus
• A series of control signals to control all
components such as registers and ALU
• Control signal for load ACC:
SETACC=1, others=0
Control and sequencing unit
from decoder
PCRD
MEMRD
μPC
SETACC
MEMORY
…
CLOCK
Control and sequencing unit
PCRD MEMRD MEMWT IRSET
fetch
decode
exec
0000
1
0
0
0
0001
0
1
0
0
0002
0
0
0
1
0003
4-bit IR RD
0004
DECODER RD, μPC SET
0005
fetch
decode
000B
….
0….
Decoder
4-bit opcode
0
1
5
B
μcode