EECS 40 Spring 2003 Lecture 22
S. Ross
CMOS LOGIC
Inside the CMOS inverter, no ID current flows through
transistors when input is logic 1 or logic 0, because
• the NMOS transistor is cutoff for logic 0 (0 V) input
• the PMOS transistor is cutoff for logic 1 (VDD) input
• current through the “turned on” transistor has nowhere to
go if next stage consists of transistor gates
VDD
VDD
S
D
VIN
S
VOUT1
D
D
D
S
S
VOUT2
EECS 40 Spring 2003 Lecture 22
S. Ross
VIN = 0 V
VIN = VDD
• NMOS transistor cutoff
(since VGS(N) = VIN = 0 V)
“acts as open circuit”
• PMOS transistor “on”
(VGS(P) = VIN – VDD = -VDD)
but ID(P) = 0 A => VDS(P) = 0 V
• PMOS transistor cutoff
(VGS(P) = VIN – VDD = 0 V)
“acts as open circuit”
• NMOS transistor “on”
(VGS(N) = VIN = VDD)
but ID(N) = 0 A => VDS(N) = 0 V
ID(N) (= -ID(P))
ID(N) (= -ID(P))
X
VOUT
VDD
X
VOUT
VDD
EECS 40 Spring 2003 Lecture 22
S. Ross
EASY MODEL FOR LOGIC ANALYSIS
There is a simpler model for the behavior of transistors in a CMOS
logic circuit, which applies when the input to the logic circuit is
fully logic 0 or fully logic 1.
VGS = 0 V
D
G
S
Each transistor
will be in one of
these two
situations!
VGS = VDD (for NMOS)
VGS = -VDD (for PMOS)
D
G
S
We can use the model to quickly determine the logical
operation of a CMOS circuit (but we cannot use it to find circuit
currents or voltages that will occur for mid-range input voltages).
EECS 40 Spring 2003 Lecture 22
S. Ross
REVISIT CMOS INVERTER WITH SIMPLE LOGIC MODEL
Fill in the switch positions below…
VDD
VIN
=0V
VDD
VOUT
VIN
= VDD
VOUT
EECS 40 Spring 2003 Lecture 22
S. Ross
VDD
CMOS NAND
S
A
PMOS1
S
PMOS2
F
B
NMOS1
S
NMOS2
S
EECS 40 Spring 2003 Lecture 22
S. Ross
Verify the logical operation of the CMOS NAND circuit:
VDD
A
= 0V
B
= 0V
S
VDD
S
F
S
S
A
= 0V
B
= VDD
S
S
F
S
S
EECS 40 Spring 2003 Lecture 22
S. Ross
Verify the logical operation of the CMOS NAND circuit:
VDD
A
= VDD
B
= 0V
S
VDD
S
S
F
S
S
A
= VDD
B
= VDD
S
F
S
S
EECS 40 Spring 2003 Lecture 22
S. Ross
CMOS NOR
VDD
A
S
PMOS1
B
S
PMOS2
F
NMOS1
NMOS2
S
S
EECS 40 Spring 2003 Lecture 22
S. Ross
Verify the logical operation of the CMOS NOR circuit:
VDD
S
A
= 0V
B
= 0V
S
F
S
S
VDD
S
A
= 0V
B
= VDD
S
F
S
S
EECS 40 Spring 2003 Lecture 22
S. Ross
Verify the logical operation of the CMOS NOR circuit:
VDD
S
A
= VDD
B
= 0V
S
F
S
S
VDD
S
A
= VDD
B
= VDD
S
F
S
S
EECS 40 Spring 2003 Lecture 22
S. Ross
PULL-UP AND PULL-DOWN DEVICES
In our logic circuits, the NMOS transistor sources are connected
to ground, and the PMOS sources are connected to VDD.
Notice that when NMOS transistors are “on” (when VGSN = VDD)
VDSN is shorted by switch, helping connect output to ground.
The NMOS transistor functions as a pull-down device;
when active, it brings the output to 0 V.
When PMOS transistors are “on” (when VGSP = -VDD)
VDSP is shorted by switch, helping connect output to VDD.
The PMOS transistor functions as a pull-up device;
when active, it brings the output to VDD.
EECS 40 Spring 2003 Lecture 22
S. Ross
LIMITATIONS OF SWITCH MODEL
Preview of next class:
VDD
A
S
S
PMOS1
PMOS2
In reality, the pull-up devices
must have some VDS voltage
and current flow to bring the
output high since natural
capacitance must be charged.
F
B
NMOS1
S
NMOS2
S
Similarly, the pull-down
devices must have some
VDS voltage and current
flow to bring the output to
ground since natural
capacitance must be
discharged.
This is GATE DELAY.
EECS 40 Spring 2003 Lecture 22
S. Ross
LIMITATIONS OF SWITCH MODEL
Suppose one needed to fully analyze the circuit for
intermediate input voltages.
VDD
A
= VDD
S
S
PMOS1
PMOS2
Requires many equations,
many unknowns.
F
B
= VTH(N) + e
NMOS1
S
NMOS2
S
But, we can at least guess
the modes.
EECS 40 Spring 2003 Lecture 22
S. Ross
VDD
A
= VDD
B
= VTH(N) + e
S
S
PMOS1
PMOS2
Assume VDD around 5 V,
VTH(N) around 1 V, VTH(P)
around -1 V, e around 0.5 V.
NMOS1
S
NMOS2
S
•
•
•
•
PMOS1 cutoff
NMOS1 barely on (VDS(N2) ≥ 0) => saturation
NMOS2 fully on, but NMOS1 limits ID to small value => triode
PMOS2 on, but NMOS1 and PMOS1 make ID small => triode