Ultra Low Resistance Ohmic Contacts to InGaAs/InP Uttam Singisetti*, A.M. Crook, E. Lind, J.D. Zimmerman, M. A. Wistey, M.J.W. Rodwell, and A.C. Gossard ECE and Materials Departments University of California, Santa Barbara, CA S.R Bank ECE Department, University of Texas, Austin, TX 2007 Device Research Conference South Bend, Indiana *uttam@ece.ucsb.edu 2007 DRC Outline • Motivation • Previous Work • Approach • Results • Conclusion 2007 DRC Device bandwidth scaling laws 1 kT kT base collector C je Cbc Rex Cbc RcollCbc 2f qI E qI E f max Goal: Double transistor bandwidth Increased Capacitance Re x c A f 8 Rbb Ccb eff Reduce transit delay Reduce RC delay Lateral Scaling Vertical Scaling Keep R constant Reduce c c has to scale as inverse square of lateral scaling *M.J.W. Rodwell, IEEE Trans. Electron. Dev., 2001 2007 DRC Device bandwidth scaling roadmap – THz transistor Emitter Resistance key to THz transistor Emitter resistance effectively contributes > 50 % in bipolar logic gate delay* Contact resistance serious barrier to THz technology 2 m 2 contact resistivity required for simultaneous THz ft and fmax *M.J.W. Rodwell, IEEE Trans. Electron. Dev., 2001 2007 DRC Device bandwidth scaling-FETs Source contact resistance must scale to the inverse square of device scaling Source resistance reduces gm and Id A 22 nm III-V MOSFET with 5 mA/m Id L S/D 15 m source resistance will reduce Id by 10% 50 nm Lg sidewall metal gate T ox source contact N+ regrowth gate dielectric drain contact N+ regrowth quantum well barrier With 50 nm contact width this will require c of 1 m2 undoped substrate P + substrate Tw undoped substrate Low source resistance means better NF in FETs* f NFmin 1 g mi ( Rs Rg Ri ) f *T Takahashi ,IPRM 07 2007 DRC Conventional Contacts • Conventional contacts – complex metallization and annealing schemes – Surface oxides, contaminants – Fermi level pinning – metal-semiconductor reaction improves resistance 5 - m2 ( 5 10 8 - m2 ) obtained on InGaAs, used on the latest HBT results Further improvement difficult using this technique Au Pt Reacted region InGaAs S.E. Mohney,PSU M.Urteaga, Teledyne Pt/Au Contact after 4hr 260C Anneal 2007 DRC In-situ ErAs-InGaAs Contacts • Epitaxial ErAs-InGaAs contact – Epitaxially formed, no surface defects, no fermi level pinning – In-situ, no surface oxides – thermodynamically stable – ErAs/InAs fermi level should be above conduction band 1J.D. Zimmerman et al., J. Vac. Sci. Technol. B, 2005 InAlAs/InGaAs Approximate Schottky barrier potential III Er As D. O. Klenov, Appl. Phys. Lett., 2005 S.R. Bank, NAMBE , 2006 2007 DRC In-situ and ex-situ Contacts • In-situ Mo Contact – In-situ deposition no oxide at metal-semiconductor interface – Fermi level pins inside conduction band of InAs in-situ 40 nm in-situ Mo 7.5 nm in-situ ErAs in-situ 40 nm in-situ Mo 5 nm InAs, 3.5x1019/cm3 N-type 5 nm InAs, 3.5x1019/cm3 N-type 95 nm In0.53Ga0.47As, 3.5x1019/cm3 N-type 95 nm In0.53Ga0.47As, 3.5x1019/cm3 N-type 100 nm In0.52Al0.48As, undoped 100 nm In0.52Al0.48As, undoped Fe-doped InP substrate Fe-doped InP substrate in-situ ErAs In-situ ErAs/InAs in-situ Mo In-situ Mo/InAs • Ex-situ contacts – InGaAs surface oxidized by UV Ozone treatment – Strong NH4OH treatment before contact metal deposition 500 nm ex-situ TiW in-situ ex-situ 95 nm In0.53Ga0.47As, 3.5x1019/cm3 N-type 100 nm In0.52Al0.48As, undoped Fe-doped InP substrate * S.Bhargava, Applied Physics Letters, 1997 ex-situ TiW Ex-situ TiW/InGaAs 2007 DRC MBE growth and TLM fabrication • MBE Growth – InGaAs:Si grown at 450 C – 3.5 E 19 active Si measured by Hall – ErAs grown at 450 C, 0.2 ML/s – Mo deposited in a electron beam evaporator connected to MBE under UHV – Mo cap on ErAs to prevent oxidation – Layer thickness chosen so as to satisfy 1-D condition in TLM • Lt L Lt/L >> 1 TLM Fabrication – Samples processed into TLM structures by photolithography and liftoff – Mo and TiW dry etched in SF6/Ar with Ni as etch mask, isolated by wet etch – Separate probe pads from contacts to minimize parasitic metal resistance Vsense Isource Isource Vsense (a) 2007 DRC Contact Resistance • 15-18 Ohm sheet resistance for all three contacts ErAs/InAs c( m ) Lt (nm) 1.5 300 Mo/InAs 0.5 175 TiW/InGaAs 0.7 190 Contact 2 1 m 1 10 cm 2 8 Resistance ( 20 3.5 Mo/InAs 15 TiW/InGaAs 10 3 Resistance () • Resistance measured by 4155 C parameter analyzer • Pad spacing verified by SEM image • Smallest gap, contact resistance 60 % of total resistance 4 2.5 5 0 0 5 10 15 20 25 30 Pad Spacing (m) ErAs/InAs 2 1.5 Isource 1 2 RC 0.5 0 Vsense Vsense 0 1 2 C RS W Isource 2 3 4 Pad (a) Spacing (m) Isource Vsense Vsense Isource 5 6 2 2007 DRC Ex-situ Contacts • Ex-situ contact depends on the concentration of NH4OH* c ( m2) 10 1 0.1 0 5 10 NH4OH Normality 15 * A.M. Crook, submitted to APL 2007 DRC Thermal Stability • Contacts annealed under N2 flow at different temperatures • Contacts stays Ohmic after anneal • In-situ Mo/InAs, ex-situ TiW/InGaAs contact resistivity < 1 -m2 after anneal • ErAs/InAs contact resistivity increases with anneal • The increase could be due to lateral oxidation of ErAs 2 Specific Contact Resistivity (m ) 100 10 ErAs/InAs As Deposited TiW/InGaAs 1 Mo/InAs 0.1 0 100 200 300 400 500 Temperature (C) 2007 DRC Thermal Stability • SIMS depth profiling shows that Mo and TiW act as diffusion barrier to Ti and Au Ni Intensity (arb. units) Ti In Mo Ga Au 0 50 100 150 200 250 Etching Time (sec) 300 350 400 SIMS profile of contacts annealed at 400 C 2007 DRC Error Analysis • 1-D Approximation Lt • Large Lt/L, • Overlap resistance • Wide contact width reduces overlap resistance. • 1-D case, Overlap resistance overestimates extracted c 2D/ 1D • 1-D case overestimates c c c .000256*contact/((V1-.032)*(V1-.032)) L 1.0 0.6 0.4 0.0 0.0 0.5 *H.Ueng, IEEE TED,2001 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Lt/L 156.25*(V1-.032) (a) W = 26 um Isource • Resistance, minimized by using 4155C parameter analyzer • dc/c* is 60 % at 1 -m2 , 75 % at 0.5 -m2 Isource Vsense 0.2 • Errors • Pad spacing, minimized by SEM inspection Vsense Isource 0.8 Pad Spacing Vsense (b) Vsense Isource 2007 DRC Integration into Device Processing • HBT emitter contact* Ti/W or Mo Ti/W Ti/W InGaAs/InP emitter InGaAs Base InP Collector Sub-Collector SI substrate InGaAs Base InP Collector Sub-Collector SI substrate Dry etch Emitter metal Dry + Wet etch Emitter InGaAs/InP emitter InGaAs Base InP Collector Sub-Collector SI substrate Blanket metal depostion *E.Lind, Late News,DRC 2007 • Source Contact in FETs r well barrier (starting material) r well barrier nonselective regrowth r well barrier planarize r well barrier etch r well barrier strip resist 2007 DRC Conclusion • Ultra Low Ohmic contacts to InGaAs/InP with c < 1 -m2 • Contacts realized by both in-situ and ex-situ • In-situ Mo/InAs and ex-situ TiW/InGaAs c < 1 -m2 even after 500 C anneal • In-situ ErAs/InAs contacts c =1.5 -m2, increases gradually with anneal This work was supported by Office of Naval Research (ONR) Ultra Low Resistance Contacts program and a grant by Swedish Research Council 2007 DRC