High Current Density and High Power Density
Operation of Ultra High Speed InP DHBTs
Mattias Dahlström1, Zach Griffith,
Young-Min Kim2, Mark J.W. Rodwell
Department of ECE
University of California, Santa Barbara, USA
(1) Now with IBM Microelectronics, Essex Junction, VT
(2) Now with Sandia National Labs, NM
mattias@ece.ucsb.edu 805-893-8044, 805-893-3262 fax
Overview
• Fast devices and circuits need high current!
– Current limited by
• Kirk current threshold
• Device heating
– Thermal resistance  Device heating
• Design of low thermal resistance HBT
• High Current Devices with state of the art
RF performance
The need for high current density
35
Scaling laws:
1
nk T
  b   c  B C je  Cbc   Rex  Rc Cbc 
2f 
qI c
t
H
20
= 459 GHz
Je=8 mA/mm2
21
15
10
A
jbe
2
= 0.6 x 7 um
I = 35 mA
5
c
2
J = 8.3 mA/um , V = 0.35 V
0
c
cb
10
11
10
Frequency (Hz)
0
0
-10
-20
dBm
Output Power (dBm)
Digital circuit
Key performance parameters:
Minimize capacitance
charging times!
 Increase current density
max
25
10
 C je 
Rex
Rbb

Vlogic ,
,
,




I

V
I

V
I
logic
c
logic
c
 c 
f
U
1
nk T
  b   c  B AeCi , je  Ac Ci ,bc   Rex  Rc Cbc
2f 
qAe J c
 Ccb 

Vlogic ,
 Ic 
...and  f .
f = 370 GHz
30
Gains (dB)
Single HBT:
f
MAG/MSG
-20
10
-40
-60
-30
-80
-40
59.34 59.36 59.38 59.40 59.42
GHz
Je=6.9 mA/mm2
-50
divide by 2
-60
-70
-80
50
12
55
60
65
70
75
frequency (GHz)
Output spectrum @ 59.35 GHz, fclk=118.70 GHz
Thermal conductivity of common materials
100
at 300 K
Si (168)
80 InP
 (W/Km)
InP
InAs
InGaAs
InAlAs
InGaP
GaAs
Si
SiN
SiO
polyimid
60
GaAs
40
InAs
20
InGaP
InAlAs
InGaAs
SiN
SiO polyimid
0
Material
Ternaries lattice matched to InP
HBT: Where is the heat generated?
Vbe0.5= 0.95 V,
Vce =0 1.3 V
-0.5
InGaAs
E
E (eV)
InGaAs
-1
c
-1.5
-2
InGaAlAs
InP
InP
Base
E
Emitter
InGaAs
v
-2.5
Collector
-3
50
100
150
200
250
300
350
Position (A)
Power generation: JE x VCE=6 x 1.5 V=9 mW/mm2
In the intrinsic collector
HBT: heat transport
Thermal resistance of materials in collector and subcollector critical
Main heat transport is through the subcollector to the substrate
Up to 30 % heat transport up through the emitter contact
How to design a low thermal resistance HBT
A five step process
Identify high thermal resistance
materials 
change them low thermal resistance
materials
Very simple!
SHBT: InGaAs collector
Design of low thermal resistance HBT:
Initial design: InGaAs collector
SHBT: InGaAs collector, InP emitter
Design of low thermal resistance HBT:
Emitter: InAlAsInP
DHBT: InGaAs/InP collector
Design of low thermal resistance HBT:
InGaAs collector  InP collector with InGaAlAs grade
DHBT: InGaAs/InP collector, InGaAs/InP subcollector
Design of low thermal resistance HBT:
InGaAs subcollector InGaAs/InP composite subcollector
DHBT: InGaAs/InP collector, thin InGaAs/InP subcollector
Design of low thermal resistance HBT:
Thick InGaAs in subcollector thin InGaAs in subcollector
Metamorphic-DHBT: InGaAs/InP collector, InGaAs/InP subcollector
Young-Min Kim
Design of low thermal resistance Metamorphic HBT:
InAlAs,InAlP, InGaAs buffersInP buffer
Experimental Measurement of Temperature Rise
dVBE dT dP
VBE fixedIc 
VCE   JA  IC  VCE
dT dP dVCE
dVBE
1
VBE
1
 JA 
fixedIc 

fixedIc 
dVCE
IC   VCE
IC  
0.014
0.012
c
I (A)
0.01
Temperature rise can be
calculated by measuring IC,
VCE and VBE
Meta run 11 (BCB)
E05B05
c
0.008
I
Vce  1.5V
Vce  1.3V
0.006
0.004
0.002
0.91
No thermal instability as long as slope<∞
each VBE gives a unique IC
0.92
0.93
0.94
0.95
V (V)
be
0.96
VBE
0.97
0.98
Thermoelectric feedback coefficient
(data from W. Liu)
W. Liu: “Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors”
, IEEE Transactions on Electron Devices, Vol 42 No6, June 1995
W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities
of InP-Based Heterojunction Bipolar Transistors”, IEEE Transactions on
Electron Devices, Vol 43 No3, March 1996
0.0022
0.002
 (V/K)
0.0018
0.0016
0.0014
0.0012
0.001
0.0008
Thermoelectric feedback coefficient from Liu et al.
0.0006
0.001
0.01
0.1
2
J (mA/mm )
1
10
e
Thermoelectric feedback coefficient for AlGaAs/GaAs HBTs 4 % smaller
Not a large influence from material or structure variations
High f DHBT Layer Structure and Band Diagram
InGaAs 3E19 Si 400 Å
Vbe = 0.75 V, Vce = 1.3 V
Emitter
InP 3E19 Si 800 Å
InP 8E17 Si 100 Å
InP 3E17 Si 300 Å
InGaAs 8E19  5E19 C 300 Å
Setback 3E16 Si 200 Å
Base
Collector
Grade 3E16 Si 240 Å
InP 3E18 Si 30 Å
InP 3E16 Si 1030 Å
InP 1.5E19 Si 500 Å
InGaAs 2E19 Si 125 Å
InP 3E19 Si 3000 Å
SI-InP substrate
Compared to previous UCSB mesa HBT results:
• Thinner InP collector—decrease c
• Collector doping increased—increase JKirk
• Thinner InGaAs in subcollector—remove heat
• Thicker InP subcollector—decrease Rc,sheet
30
Thermal resistance results: lattice matched
20
3
25
25 25
nmnm
InGaAs,
polymimide
Rth
InGaAs,
polymimide
12.5
nmnm
InGaAs,
polymimide
Rth
12.5
InGaAs,
polymimide
12.5
nmnm
InGaAs,
BCB
Rthnew
12.5
InGaAs,
BCB
3.5
15
2.5
2
10
1.5
5
1
0.5
0
0
10
15
20
25
2
Base-Collector Area (mm )
30
Measured thermal resistances for lattice matched HBTs.
Ic= 5 mA, Vce=1.5 V, P=7.5 mW
12.5 nm InGaAs
Device
Buffer
(mm)
Tc (nm)
Tsc InGaAs
(nm)
Tsc InP
(nm)
JA
K/mW
DHBT-M1
-
200
25
125
2.5
DHBT-19b
-
150
12.5
300
1.8
DHBT-23
-
150
12.5
300
1.4
50 nm InGaAs 25 nm InGaAs: large
improvement
Temperature rise (K)
25 nm InGaAs
Thermal resistance (K/mW)
4
Thermal resistance results: metamorphic
100
80
InAlP
buffer,
25 nm
InGaAs
Rth
InAlP
buffer,
25 nm
InGaAs
InPInP
buffer,
25
nm
InGaAs
Rth
buffer, 25 nm InGaAs
InPInP
buffer,
12.5
nmnm
InGaAs
Rth
buffer,
12.5
InGaAs
12
60
10
8
40
6
20
4
2
0
0
Temperature rise (K)
50 nm InGaAs
InAlP buffer
Thermal resistance (K/mW)
14
5
10
15
20
25
2
Base-Collector Area (mm )
30
35
Measured thermal resistances for metamorphic HBTs. Ic=
5 mA, Vce=1.5 V, P=7.5 mW
25 nm InGaAs
InP buffer
Device
Buffer (mm)
Tc (nm)
Tsc InGaAs
(nm)
Tsc InP
(nm)
JA
K/mW
M-HBT-1
InAlP 1.5
200
50
125
7.6
M-HBT-2
InP 1.5
200
50
125
3.3
M-HBT-11
InP 1.5
200
25
300
3.1
InAlP InP buffer: large improvement
50 nm InGaAs 25 nm InGaAs: small
improvement
Device and circuit results
Zach Griffith
2
V =0V
jbe
0.00
cb
14
I
b step
10
8
6
-0.10
-0.15
4
-0.20
2
-0.25
0
0
-10
-20
-20
-40
-60
-30
-80
-40
59.34 59.36 59.38 59.40 59.42
GHz
-50
divide by 2
-60
-70
-80
0
0
50
100
time (ps)
0
0.5
1
V
1.5
2
(V)
ce
Transistor operation
at 13 mA/mm2
150 nm InGaAs/InP collector
35
MAG/MSG
f = 370 GHz
t
30
f
U
max
25
Gains (dB)
Output Power (dBm)
Output Signal (V)
-0.05
e
2
J (mA/mm )
12
= 0.4 mA
dBm
A = 0.5 x 7 mm
= 459 GHz
H
20
21
15
10
A
jbe
55
60
65
70
frequency (GHz)
28 transistor static frequency divider
@ fclk=118.7 GHz shown
To be reported, 150 GHz static
divider using same Type 1 DHBT
structure—chirped superlattice
2
c
2
J = 8.3 mA/um , V = 0.35 V
0
50
= 0.6 x 7 um
I = 35 mA
5
150
c
cb
10
10
11
10
Frequency (Hz)
370 GHz ft at Jc>8 mA/mm2
10
12
Continuous operation at high current
densities greater than peak rf
performance (Je = 8 mA/mm2)
75
Our Mesa DHBTs have Safe Operating Area
Extending beyond High-Speed Logic Bias Conditions
Vcb = 0 V
A = 0.5 x 7 mm
I
b step
jbe
= 0.4 mA
12
2
12
10
peak (f , f

) bias
max
8
8
6
~6.8 V low-current
BVCEO
2
2
0
0
0
0.5
1
1.5
0
2
10
device failure
18 mW/um 2
8
design limit 10 mW/um
No RF drift
after 3-hr
ECL
burn-in
max
bias points
0
1
5
6
7
2
this has little bearing on circuit
design
these HBTs can be biased
....at ECL voltages
...while carrying the high current
densities needed for high speed
8 mm emitter metal length,
~0.6 mm junction width
0
4
Safe operating area is > 10 mW/um2
4
2
3
Low-current breakdown is > 6 Volts
biased without
failure (DC-IV)
6
2
ce
ce
12
1
V (V)
V (V)
(mA/um 2)
Ib step = 0.4 mA
10
4
4
J
0.5 um X 0.7 um emitter junction
A0.5
=0.6 x 7 mm2
jbe um base contact width
e
6
e
J (mA/mm2)
14
2
J (mA/mm )
14
2
3
V (V)
ce
4
5
6
8
Conclusions
• DHBT design with InP subcollector
 very low thermal resistance
•Metamorphic DHBT with InP buffer
 low thermal resistance
•DHBT operation at Jc>13 mA/mm2
•Optimal device and circuit performance at Jc up to 8 mA/mm2
•HBT I-V operating area allows static frequency dividers
operating at speeds over 150 GHz
Backup slides
HBT
Why is thermal management important?
•
As J increases so does the power
density. This will lead to an
increase in the temperature.
TC
JKirk
Le
Å
mAμm-2
μm
3000
1.0
81
2000
2.3
34
1500
4.1
19
1000
9.8
8.6


V=2V
80mA
For VCE=1V  PD=10.6mWμm-3
For VCE=1V  PD=98mWμm-3!!
Thermal Modeling of HBT (1)
• 3D Finite Element using Ansys 5.7
• K (Thermal conductivity) depends temperature
• K depends on doping
 300 
kT  k300 

 T 
n
• For GaAs heavily doped GaAs 65% less than undoped GaAs
• Unknown for InP or InGaAs use GaAs dependency
Material
K300
n
K300(exp)
Refs
InP
0.68
1.42
0.68-0.877
1
InGaAs
0.048
1.375
0.048-0.061
2
Au
3.17
-

Large uncertainty
in values
3
J.C.Brice in “Properties of Indium phosphide” eds S Adachi and J.Brice pubs INSPEC London p20-21
S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p34-39
“CRC Materials science and engineering handbook”, 2nd edition ,eds J.F Shackelford,A.Alexander, and J.S Park, pubs CRC press, Boca Raton, p270
Validation of Model
Ian Harrison
40
Caused by
Low K
of InGaAs
Max T in
Collector
Temperature Rise (K)
35
center
Edge
30
25
20
15
10
5
SC
ES
C
B
E
E Metal
0
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Distance from substrate (mm)
Ave Tj (Base-Emitter) =26.20°C
Measured Tj=26°C
Good agreement.
Advice
Limit InGaAs
Increase size of emitter arm
Analysis of 40,80,160 Gbit/s devices
Ian Harrison
•
To obtain speed inprovements require to scale other device
.
parameters
Speed
(Gbit/s)
40
80
160
Collector Thickness
(Å)
3000
2000
1000
Base Sheet resistance
()
750
700
700
Base contact resistance
(-mm2)
150
20
10
Base Thickness
(Å)
400
300
250
Base Mesa width
( mm)
3
1.6
0.4
Current Density
(mA/mm2)
1
2.3
9.8
Emitter. Junction Width
( mm)
1
0.8
0.2
Emitter Parasitic resistivity
(-mm2)
50
20
5
Emitter Length
( mm)
6
3.3
3.2
Predicted MS-DFF
(GHz)
62
125
237
Ft
(GHz)
170
260
500
Fmax
(GHz)
170
440
1000
Tj
(K)
7.5
14
28
TMax
(K)
10
20
49
TMax (No Etch Stop layer)
(K)
7.5
13
21
Device parameters after Rodwell et al


V=0.3V
6mA
Reduction of
parasitic CBC
Conservative
1.5x bit rate
When not switching
values will double
Mesa DHBT with 0.6 mm emitter width, 0.5 mm base contact
width
Z. Griffith, M Dahlström
How we measure thermal resistance
Layout improvement: Emitter heat sinking
Improved emitter heatsinking
Emitter interconnect metal  2 μm to 7 μm
~30 % of heat out through emitter Negligible increase in Cbe