Loran-C Receiver
ECEN 4610 Capstone CDR
Team Deathstar:
Christopher Birschbach
Matthew Hayman
Matthew Anderson
Christina Corner
Erin Mowbray
October 5, 2004
Agenda
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

Budget
System Diagram
Subsystem Functionality
– Hardware/Schematics
– Parts List
– Software Design


Progress since PDR
Future Goals and
Deadlines
– Milestone 1
– Milestone 2
– Expo
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
Division of Labor
Questions/Comments
Budget
Item
Description
Estimated Price
Processor
$100.00
LCD Display
$75.00
Additional memory
$50.00
A to D converter
$50.00
Antenna Assembly
$100.00
Receiver Enclosure
$100.00
Printed Circuit Board
$200.00
FPGA
Xilinx FPGA Evaluation Kit
$250.00
Filters
3 Butterworth (8th order)
$75.00
RS-232 Interface
Support Electronics
$25.00
Resistors, Caps, switches, sockets, cables
Power Supply
$150.00
$100.00
Student Designed User Manual
Weighted Paper, Binding, Printing Costs
$150.00
Final Project Display
Printed Poster for Engineering Expo
$100.00
Loran C User Handbook
Misc.
$25.00
(Ink Cartridges, Repair parts, reference manuals)
$200.00
TOTAL:
$1,750.00
Block Diagram
Processing Unit
FPGA
Processor
Antenna/Receiver
Analog Signal
A/D
Converter
Zero
Crossing
State
Machine
Counter
RAM
ALU
RS-232
PC
Outline of Approach

The system will consist of the following
subsystems:
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–
–
–
–
–
–
–
Antenna Receiver
Analog-to-digital converter
Motorola 68HC11 processor
Memory
FPGA
Serial Interface
PC
Power
Antenna/Receiver


AM Antenna
8th Order Butterworth Filter (MAX274B)
(This portion of the project will continue when the filters from Maxim arrive.)
Signal Processing Unit
Part List
Parts List
Part Number
Motorola Processor
68HC11
Flash
AT29C256
Bi-directional drivers
74HC245
Latch
74HC373
Schmitt trigger inverter
74HC14
Xilinix FPGA
XCS10
FPGA EPROM
XC18V256
RAM
HM62256
3.3V regulator
78M33
5V regulator
7805
A/D Converter
AD7828
RS-232 Adapter
MAX233
TTL AND gate
74LS08
8 MHz clock
CO6050
Processor Schematic
FPGA Design



Chip select
State machine
Counter
FPGA Schematic
FPGA – Chip Select
Software Design

FPGA:
– Input

Digital Loran-C signal
– Output


Counter Data
Processor:
– Input

Counter Data
– Output


PC:
Time delays
– Input

Time delays
– Output

Latitudinal and Longitudinal coordinates
Software Design

Initial Test Code
Software Design
Progress since PDR
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


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Schematic Design
Initial Wire wrapped
board completed
Basic Processor
Functionality
Basic FPGA
Functionality
Basic RAM
Functionality
Project Timeline
Future Deadlines



Milestone 1 – 10/26
Milestone 2 – 11/16
Open-Lab Expo – 12/9
Milestone 1


Date: October 26th
Parts completed:
– Completed Wiring on Vector Board
– Antenna/Filtering –Clean signal
– Sampling by A/D converter completed
– Order first PCB
Milestone 2


Date: November 16th
Parts Completed:
– Functioning PCB
– State machine on FPGA working
– Communication between the Processing
Unit and Antenna/Receiver.
Capstone Expo

Working Loran-C Receiver
– Functionality between all 3
Subsystems:
Antenna/Receiver,
Processing Unit, & PC
– Working Serial
Interface
Extra Features

These will be added if time permits at
the end of the semester.
– Portable Power Supply
– LCD Display
Division of Labor
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Matt A
–
–
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Power
Memory interface
Microprocessor Programming
–
–
–
PC programming
Microprocessor programming
User’s Manual
–
–
–
Antenna/Filtering
Verilog Design
User’s Manual
–
–
–
–
Antenna/Filtering
PCB
Microprocessor Programming
PC programming
–
–
–
Verilog Design
User’s Manual
PC interface
Chris B
Christy C
Matt H
Erin M
Questions/Comments