Lecture #35
OUTLINE
The MOS Capacitor: Final comments
The MOSFET:
• Structure and operation
Reading: Chapter 17.1
Spring 2007
EE130 Lecture 35, Slide 1
Bias-Temperature Stress Measurement
Used to determine mobile charge density in MOS dielectric (units: C/cm2)
Na+ located at
lower SiO2 interface
 reduces VFB
VFB
Na+ located at
upper SiO2 interface
 no effect on VFB
Positive oxide charge shifts the flatband voltage in the negative direction:
VFB
QF
1
 MS 

Cox  SiO2
QIT (S )
0 xox ( x)dx  Cox
xo
QM  Cox VFB
Spring 2007
EE130 Lecture 35, Slide 2
Clarification: Effect of Interface Traps
(c)
(b)
(a)
“Donor-like” traps are
charge-neutral when
filled, positively charged
when empty
(a)
Positive oxide charge
causes C-V curve to
shift toward left
(more shift as VG
decreases)
(b)
Traps cause “sloppy” C-V and also
greatly degrade mobility in channel
QIT (S )
VG  
Cox
Spring 2007
EE130 Lecture 35, Slide 3
(c)
Invention of the Field-Effect Transistor
In 1935, a British patent was issued to Oskar Heil.
A working MOSFET was not demonstrated until 1955.
Spring 2007
EE130 Lecture 35, Slide 4
Modern Field Effect Transistor (FET)
• An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying
electrode), to modulate the conductance of the
semiconductor
 Modulate drift current flowing between 2 contacts
(“source” and “drain”) by varying the voltage on the
“gate” electrode
Spring 2007
EE130 Lecture 35, Slide 5
The Bulk-Si MOSFET
GATE LENGTH, Lg
Metal-Oxide-Semiconductor
Field-Effect Transistor:
OXIDE THICKNESS, Tox
Gate
Desired characteristics:
• High ON current
• Low OFF current
Source
Drain
Substrate
M. Bohr, Intel Developer
Forum, September 2004
JUNCTION DEPTH, Xj
• “N-channel” & “P-channel” MOSFETs
operate in a complementary manner
“CMOS” = Complementary MOS
Spring 2007
EE130 Lecture 35, Slide 6
CURRENT
• Current flowing between the SOURCE and DRAIN is
controlled by the voltage on the GATE electrode
VT
|GATE VOLTAGE|
N-channel vs. P-channel
NMOS
PMOS
N+ poly-Si
P+ poly-Si
N+
N+
P+
P-type Si
P+
n-type Si
• For current to flow, VGS > VT
• For current to flow, VGS < VT
• Enhancement mode: VT > 0
• Enhancement mode: VT < 0
• Depletion mode: VT < 0
• Depletion mode: VT > 0
– Transistor is ON when VG=0V
Spring 2007
– Transistor is ON when VG=0V
EE130 Lecture 35, Slide 7
Enhancement Mode vs. Depletion Mode
Enhancement Mode
Conduction between source
and drain regions is enhanced
by applying a gate voltage
Spring 2007
Depletion Mode
A gate voltage must be applied
to deplete the channel region
in order to turn off the transistor
EE130 Lecture 35, Slide 8
CMOS Devices and Circuits
CIRCUIT SYMBOLS
N-channel
MOSFET
P-channel
MOSFET
G
G
CMOS INVERTER CIRCUIT
VOUT
VDD
S
INVERTER
LOGIC SYMBOL
VDD
D
S
D
S
D
VIN
D
GND
VOUT
S
0
VDD
VIN
• When VG = VDD , the NMOSFET is on and the PMOSFET is off.
• When VG = 0, the PMOSFET is on and the NMOSFET is off.
Spring 2007
EE130 Lecture 35, Slide 9
“Pull-Down” and “Pull-Up” Devices
•
In CMOS logic gates, NMOSFETs are used to connect the output to
GND, whereas PMOSFETs are used to connect the output to VDD.
– An NMOSFET functions as a pull-down device when it is turned
on (gate voltage = VDD)
– A PMOSFET functions as a pull-up device when it is turned on
(gate voltage = GND)
VDD
A1
input signals A2
AN
A1
A2
AN
Spring 2007
Pull-up
network
PMOSFETs only
F(A1, A2, …, AN)
Pull-down
network
EE130 Lecture 35, Slide 10
NMOSFETs only
CMOS NAND Gate
VDD
A
A B
0 0
0 1
1 0
1 1
B
F
A
B
Spring 2007
EE130 Lecture 35, Slide 11
F
1
1
1
0
CMOS NOR Gate
VDD
A B
0 0
0 1
1 0
1 1
A
B
F
A
B
Spring 2007
EE130 Lecture 35, Slide 12
F
1
0
0
0
CMOS Pass Gate
A
Y
X
A
Spring 2007
EE130 Lecture 35, Slide 13
Y = X if A