Lecture #39
OUTLINE
The MOSFET:
• Sub-threshold leakage current
• Gate-length scaling
Spring 2007
EE130 Lecture 39, Slide 1
Sub-Threshold Leakage Current
• We had previously assumed
that there is no channel current
when VGS < VT. This is incorrect.
• If fS > fF, there is some
inversion charge at the surface,
which gives rise to sub-threshold
current flowing between the
source and drain:
2
I DS  eff Coxe
Spring 2007
 kT 
W
(m  1)  e q (VG VT ) / mkT (1  e qVDS / kT )
L
 q 
EE130 Lecture 39, Slide 2
Sub-Threshold Slope S
1
 d (log 10 I DS ) 

S  
dVGS


kT
Cdm

ln (10)(1 
)
q
Coxe
Spring 2007
EE130 Lecture 39, Slide 3
How to minimize S?
Spring 2007
EE130 Lecture 39, Slide 4
MOSFET Scaling
• MOSFETs have scaled in size over time
– 1970’s: ~ 10 m
– Today: ~50 nm
• Reasons:
– Speed
– Density
Spring 2007
EE130 Lecture 39, Slide 5
Benefit of Transistor Scaling
– IDS  as L  (decreased effective “R”)
– Gate area  as L  (decreased load “C”)
– Therefore, RC  (implies faster switch)
Spring 2007
EE130 Lecture 39, Slide 6
Circuit Example – CMOS Inverter
Vd d
(a)
V1
...........
V2
V3
C
............
C
V2
Vd d
2 d
(b)
V3
 d : propagatio n delay
V1
0
Spring 2007
t
EE130 Lecture 39, Slide 7
1
 d  ( pull  down delay  pull  up delay )
2
CVdd
pull  up delay 
2 I dsatP
pull  down delay 
CVdd
2 I dsatN
CVdd
1
1
d 
(

)
4 I dsatN I dsatP
RN and RP 
Spring 2007
d is reduced by increasing IDsat
Vdd
Vdd

2 I on 2 I dsat (| Vg | Vdd )
EE130 Lecture 39, Slide 8
Constant-Field Scaling
• Voltages and MOSFET dimensions are scaled by the
same factor k>1, so that the electric field remains
unchanged
Spring 2007
EE130 Lecture 39, Slide 9
Constant-Field Scaling (cont.)
• Circuit speed
improves by k
• Power dissipation
per function
is reduced by k2
Spring 2007
EE130 Lecture 39, Slide 10
VT Design Trade-Off
• Low VT is desirable for high ON current:
IDsat  (VDD - VT)
1<<2
• But high VT is needed for low OFF current:
log IDS
Low VT
VT cannot be scaled
aggressively!
High VT
IOFF,low VT
IOFF,high VT
0
Spring 2007
VGS
EE130 Lecture 39, Slide 11
• Since VT cannot be scaled down aggressively, the
power-supply voltage (VDD) has not been scaled
down in proportion to the MOSFET channel length
Spring 2007
EE130 Lecture 39, Slide 12
Generalized Scaling
• Electric field intensity increases by a factor a>1
• Nbody must be scaled up by a to control short-channel effects
• Reliability and
power density
are issues
Spring 2007
EE130 Lecture 39, Slide 13
CMOS Scaling and the Power Crisis
1000
1E+03
Tox (C )
Power (W/cm2)
100
10
classic scaling
1
Vdd (V)
Vt (V)
Active Power Density
1E+02
1E+01
1E+00
1E-01
1E-02
1E-03
Passive Power Density
1E-04
0.1
0.01
0.1
1
1E-05
0.01
Gate Length, Lgate (um )
0.1
Gate Length (μm)
Lg/VDD/VT trends  increases in:
• Active Power Density (VDD2)
~1.3X/generation
• Passive Power Density (VDD) ~3X/generation
• Gate Leakage Power Density >4X/generation
Spring IBM,
2007
Source: B. Meyerson,
Semico Conf., January 2004 EE130 Lecture 39, Slide 14
1