Week 14a
Propagation delay of logic gates
CMOS (complementary MOS) logic gates
Pull-down and pull-up
The basic CMOS inverter
Current flow and power dissipation in CMOS circuits
Equation for power dissipated in N logic circuits
clocked at frequency f
EE42/100, Spring 2006
Week 14a, Prof. White
1
WHAT IS THE ORIGIN OF GATE DELAY?
Logic gates are electronic circuits that process electrical signals
Most common signal for logic variable: voltage
Specific voltage ranges correspond to “0” or “1”
Volts
3
Range  “1”
Thus delay in voltage rise or fall
(because of delay in charging
internal capacitances) will translate
to a delay in signal timing
2
“Gray area” . . . not allowed
1
Range  “0”
0
Note that the specific voltage range for 0 or 1 depends on “logic
family,” and in general decreases with succeeding logic generations
EE42/100, Spring 2006
Week 14a, Prof. White
2
INVERTER VOLTAGE WAVEFORMS (TIME FUNCTIONS)
Inverter input is vIN(t), output is vOUT(t)
Inverter inside a large system
v IN ( t )
v OUT ( t )
Vin(t)
t
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GATE DELAY (PROPAGATION DELAY)
Define t as the delay required for the output voltage to reach 50% of its final
value. In this example we will use 3V logic, so halfway point is 1.5V.
Inverters are designed so that the gate delay is symmetrical (rise and fall)
Vin(t)
1.5
t
Vout(t)
Approximation
1.5
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tD
tWeek
tDWhite
D
14a, Prof.
t
4
EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED
Computer architects would like each system clock cycle to have
between 20 and 50 gate delays … use 35 for calculations
Implication: if clock frequency = 500 MHz
clock period = (5108 s1)1
Period = 2  10 9s = 2 ns (nanoseconds)
Gate delay must be tD = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds)
How fast is this? Speed of light: c = 3  108 m/s
Distance traveled in 57 ps is:
c X tD = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cm
EE42/100, Spring 2006
Week 14a, Prof. White
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WHAT DETERMINES GATE DELAY?
v OUT ( t )
v IN ( t )
The delay is mostly simply the charging of the capacitors at internal nodes.
Logic gates consist of just “CMOS” transistor circuits (CMOS =
complementary metal-oxide-semiconductor = NMOS and PMOS FETs together).
Let’s recall the FET
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Modern Field Effect Transistor (FET)
• An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying
“gate” electrode), to modulate the conductance of the
semiconductor
 Modulate drift current flowing between 2 contacts
(“source” and “drain”) by varying the voltage on the
“gate” electrode
N-channel metal-oxidesemiconductor field-effect
transistor (NMOSFET)
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Pull-Down and Pull-Up Devices
•
In CMOS logic gates, NMOSFETs are used to connect
the output to GND, whereas PMOSFETs are used to
connect the output to VDD.
– An NMOSFET functions as a pull-down device when it
is turned on (gate voltage = VDD)
– A PMOSFET functions as a pull-up device when it is
turned on (gate voltage = GND)
VDD
A1
input signals A2
AN
A1
A2
AN
EE42/100, Spring 2006
Pull-up
network
PMOSFETs only
F(A1, A2, …, AN)
Pull-down
network
Week 14a, Prof. White
NMOSFETs only
8
Controlled Switch Model
G
Input
+
- -
RN +
Output
+-
Type N controlled switch”
means switch is closed if
input is high. (VG > VS)
RP +
Output
+-
Type P controlled switch”
means switch is closed if
input is low. (VG < VS)
S
G
Input
+
- -
S
Now lets combine these switches to make an inverter.
EE42/100, Spring 2006
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9
The CMOS Inverter: Current Flow during Switching
N: sat
P: sat
VOUT
N: off
P: lin
V DD
VDD
S
G
i
VOUT
A
D
G
C
N: sat
P: lin
D
V IN
i
B
D
E
N: lin
P: sat
S
N: lin
P: off
0
0
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Week 14a, Prof. White
VDD
VIN
10
CMOS Inverter Power Dissipation due to DirectPath Current
VDD
DD
V
VDD-VT
vIN:
S
G
D
i
vIN
0
Ipeak
vOUT
D
G
S
VT
i:
0
tsc
time
Note: once the CMOS circuit reaches a steady state there’s no more current flow
and hence no more power dissipation!
Energy consumed per switching period:
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Edp  t scVDD I peak
11
Controlled Switch Model of Inverter
VDD = 2V
SP is closed if
VIN < VDD
-
SP
+
RP
VIN
+
RN
Input
VOUT
+
+SN is closed if Output
VIN > VSS
SN
-
VSS = 0V
So if VIN is 2V then SN is closed and SP is open. Hence VOUT is zero.
But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V.
EE42/100, Spring 2006
Week 14a, Prof. White
12
Controlled Switch Model of Inverter
VDD = 2V
VIN =2V
+
RN
- SS = 0V
V
VOUT
-
IF VIN is 2V then SN is
closed and SP is open.
Hence VOUT is zero (but
driven through resistance
RN).
VDD = 2V
VIN =0V
RP
+
VOUT
- SS = 0V
V
EE42/100, Spring 2006
-
But if VIN is 0V then SP
is closed and SN is
open. Hence VOUT is
2V (but driven through
resistance RP).
Week 14a, Prof. White
13
Controlled Switch Model of Inverter – load
capacitor charging and discharging takes time
VDD = 2V
VIN =2V
+
RN
- SS = 0V
V
VOUT
-
IF there is a capacitance at
the output node (there
always is) then VOUT
responds to a change in VIN
with our usual exponential
form.
VOUT
VDD = 2V
VIN =0V
VIN jumps from
2V to 0V
RP
+
VOUT
- SS = 0V
V
EE42/100, Spring 2006
Week 14a, Prof. White
VIN jumps from
0V to 2V
t
14
Calculating the Propagation Delay
Model the MOSFET in the ON state as a resistive switch:
Case 1: Vout changing from High to Low
(input signal changed from Low to High)
 NMOSFET(s) connect Vout to GND
VDD
tpHL= 0.69RnCL
Pull-up network is modeled as an open switch
vIN = VDD
Pull-down network is modeled as a resistor
Rn
+
CL
vOUT

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Calculating the Propagation Delay (cont’d)
Case 2: Vout changing from Low to High
(input signal changed from High to Low)
 PMOSFET(s) connect Vout to VDD
VDD
tpLH = 0.69RpCL
Pull-up network is modeled as a resistor
Rp
vIN = 0 V
Pull-down network is modeled as an open switch
+
CL
vOUT

EE42/100, Spring 2006
Week 14a, Prof. White
16
Output Capacitance of a Logic Gate
• The output capacitance of a logic gate is
comprised of several components:
• pn-junction and gate-drain capacitance
– both NMOS and PMOS transistors
• capacitance of connecting wires
“extrinsic
capacitance” • input capacitances of the fan-out gates
“intrinsic
capacitance”
EE42/100, Spring 2006
Week 14a, Prof. White
17
Reminder: Fan-Out
• Typically, the output of a logic gate is connected
to the input(s) of one or more logic gates
• The fan-out is the number of gates that are
connected to the output of the driving gate:
1
2
driving gate
N
•
•
•
fan-out =N
• Fanout leads to increased capacitive load on the
driving gate, and therefore more propagation delay
– The input capacitances of the driven gates sum, and must be
charged through the equivalent resistance of the driver
EE42/100, Spring 2006
Week 14a, Prof. White
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Minimizing Propagation Delay
•
A fast gate is built by
1. Keeping the output capacitance CL small
– Minimize the area of drain pn junctions.
– Lay out devices to minimize interconnect
capacitance.
– Avoid large fan-out.
2. Decreasing the equivalent resistance of
the transistors
– Decrease L (gate length source to drain)
– Increase W (other dimension of gate)
… but this increases pn junction area and hence CL
3. Increasing VDD
→ trade-off with power consumption & reliability
EE42/100, Spring 2006
Week 14a, Prof. White
19
MOSFET
• NMOS: N-channel Metal
Oxide Semiconductor
W
• L = channel length
• W = channel width
GATE
L
“Metal” (heavily
doped poly-Si)
DRAIN
SOURCE
• A GATE electrode is placed above (electrically insulated
from) the silicon surface, and is used to control the
resistance between the SOURCE and DRAIN regions
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Week 14a, Prof. White
20
Transistor Sizing for Performance
VDD
G
S
D
VOUT
VIN
D
G
S
EE42/100, Spring 2006
• Widening the transistors
reduces resistance – current
paths in parallel -- but
increases gate capacitance
• In order to have the on-state
resistance of the PMOS
transistor match that of the
NMOS transistor (e.g. to
achieve a symmetric voltage
transfer curve), its W/L ratio
must be larger by a factor of
~3 (because holes move
about 3 times slower than
electrons in a given electric
field).
Week 14a, Prof. White
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Other CMOS logic examples
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22
VDD
A
CMOS NAND Gate
A B
0 0
0 1
1 0
1 1
B
F
1
1
1
0
F
A
B
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VDD
CMOS NOR Gate
A B
0 0
0 1
1 0
1 1
A
F
1
0
0
0
B
F
B
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A
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Static Random-Access Memory (SRAM)
with CMOS Circuit in each cell
Row Address Decoder
Word Line
Figure 0.1
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Bit Line
Column Drivers and
Sense Amplifiers
Column Address
Decoder/Selector
Bit Line
+Vdd
SRAM circuit diagram and cell schematic
Week 14a, Prof. White
25
Power consumption in CMOS circuits
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26
ENERGY AND POWER IN CHARGING/DISCHARGING
CAPACITORS – A REVIEW
CASE 1R
t=0
Capacitor initially uncharged
Charging
i

(Q=CVDD at end)
V
C
DD

RD
Switch moves @ t=0
Power out of "battery"
P  i( t ) VDD
Power into C
PC  i( t )VC ( t )
Power into R
PR  i( t )2 R
Energy out of "battery"
Energy into C
Energy into R (heat)

E   iV DD dt  QVDD
0
 CVDD 2
EE42/100, Spring 2006
E

C
  iV dt
C
0
1
 CV 2
2 DD
Week 14a, Prof. White
This must be difference
of E and EC, i.e. 1 CV 2
2
DD
27
ENERGY AND POWER IN CHARGING
R
t=0

VDD

C
RD
Capacitor initially uncharged
(Q=CVDD at end)
Switch moves @ t=0
Energy out of "battery"
 CVDD
2
Energy into C
1
 CV 2
2 DD
Energy into R (heat)
1
CV 2
2 DD
In charging a capacitor from a fixed voltage source VDD half the
energy from the source is delivered to the capacitor, and half is
lost to the charging resistance, independent of the value of R.
EE42/100, Spring 2006
Week 14a, Prof. White
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ENERGY AND POWER IN CHARGING/DISCHARGING
CAPACITORS
CASE 2R
t=0
Capacitor initially charged
discharging

(Q=CVDD) and discharges.
V
C
DD

RD
i
Switch moves @ t=0
=0
Power out of C
PC  i( t )VC ( t )
Power into RD
PR  i( t )2 R
Energy out of battery
Energy out of C
Energy into RD (heat)
Power out of battery
=0
Power in/out of R
=0
EE42/100, Spring 2006
E

C
  iV dt
C
0
1
 CV 2
2 DD
Week 14a, Prof. White
This must be energy
initially in C, i.e.
1
CV 2
2 DD
29
ENERGY IN DISCHARGING CAPACITORS
R
t=0

VDD

C
RD
Capacitor initially charged
(Q=CVDD) and discharges.
Switch moves @ t=0
Energy out of C
1
 CV 2
2 DD
Energy into RD (heat)
1
CV 2
2 DD
When a capacitor is discharged into a resistor the energy
originally stored in the capacitor (1/2 CVDD2) is dissipated as heat
in the resistor
EE42/100, Spring 2006
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•
CMOS Power Consumption
The total power consumed by a CMOS circuit
is comprised of several components:
1. Dynamic power consumption due to charging
and discharging capacitances*:
2
2
Pdyn  CLVDD
f 01  CEFFVDD
f
f01 = frequency of 01 transitions (“switching activity”)
f = clock rate (maximum possible event rate)
Effective capacitance CEFF = average capacitance
charged every clock cycle
* This is typically by far the dominant component!
Other components of power dissipation are direct current flow during part of
the CMOS switching cycle and leakage in the transistor junctions.
EE42/100, Spring 2006
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31
POWER DISSIPATION in DIGITAL CIRCUITS
Each node transition (i.e. charging or discharging) results in a loss of
(1/2)(C)(VDD2) How many transitions occur per second? Well if the
node is pulsed up then down at a frequency f (like a clock frequency)
then we have 2f dissipation events.
A system of N nodes being pulsed at a frequency f to a signal voltage
VDD will dissipate energy equal to (N) (2f )(½CVDD2) each second
Therefore the average power dissipation is (N) (f )(CVDD2)
EE42/100, Spring 2006
Week 14a, Prof. White
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LOGIC POWER DISSIPATION EXAMPLE
Power = (Number of gates) x (Energy per cycle) x (frequency)
P = (N) (CVDD2) (f )
N = 107; VDD = 2 V; node capacitance = 10 fF; f = 109 s-1 (1GHz)
P = 400 W! -- a toaster!
Pretty high but realistic
What to do? (N increases, f increases, hmm)
1) Lower VDD
2) Turn off the clock to the inactive nodes
Clever architecture and design!
Let’s define a as the fraction of nodes that are clocked
(active). Then we have a new formula for power.
EE42/100, Spring 2006
Week 14a, Prof. White
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LOGIC POWER DISSIPATION with power mitigation
Power = (Energy per transition) x (Number of gates) x (frequency) x
fraction of gates that are active (a).
P = a N CVDD2 f
In the last 5 years VDD has been lowered from 5V to about 1.5V. It
cannot go very much lower. But with clever design, we can
make a as low as 1 or 10%. That is we do not clock those parts
of the chip where there is no computation being made at the
moment.
Thus the 400W example becomes 4 to 40W, a manageable range
(4W with heat sink, 40W with heat sink plus fan on the chip).
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Week 14a, Prof. White
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Low-Power Design Techniques
1. Reduce VDD
→ quadratic effect on Pdyn
Example: Reducing VDD from 2.5 V to 1.25 V
reduces power dissipation by factor of 4
– Lower bound is set by VT: VDD should be >2VT
2. Reduce load capacitance
→ Use minimum-sized transistors whenever possible
3. Reduce the switching activity
– involves design considerations at the architecture
level (beyond the scope of this class!)
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Week 14a, Prof. White
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