Lecture #25 Timing issues
10/29/2004
EE 42 fall 2004 lecture 25
1
Topics
Today:
• Gate delays
• Timing diagrams
• Glitches
Reading: Handout
10/29/2004
EE 42 fall 2004 lecture 25
2
Alternative reading
Schwarz and Oldham
Electrical Engineering, an Introduction
Second edition
Saunders College publishing
Available used in campus bookstores
Recommended Chapters:
1-5Circuits
13,15transistors
11Digitial circuits
12Digital systems
10/29/2004
EE 42 fall 2004 lecture 25
3
Transistor Inverter Example
It may be simpler to just think of PMOS and NMOS transistors instead
of a general 3 terminal pull-up or pull-down devices or networks.
VDD
VDD
Pull-Up
Network
VIN-U
IOUT
Pull-Down
Network
VIN-D
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VIN-U
Output
IOUT
VOUT
VIN-D
EE 42 fall 2004 lecture 25
p-type MOS
Transistor
(PMOS)
Output
n-type MOS
Transistor
(NMOS)
VOUT
4
Complementary Networks
• If inputs A and B are connected to parallel NMOS, A
and B must be connected to series PMOS.
• The reverse is also true.
• Determining the logic function from CMOS circuit is
not hard:
– Look at the NMOS half. It will tell you when the output is
logic zero.
– Parallel transistors: “like or”
– Series transistors: “like and”
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EE 42 fall 2004 lecture 25
5
Resistance and Capacitance
VGS > VTH(n)
gate
- +
metal
n-type
+ + +
_
_
metal
oxide insulator
ee_ e _e_ e _
_
drain
metal
n-type
+ + +
_
_
p-type
h
h
h
h
h
h
h
h
h
h
metal
•
•
•
The separation of charge by the oxide insulator creates a natural
capacitance in the transistor from gate to source.
The silicon through which ID flows has a natural resistance.
There are other sources of capacitance and resistance too.
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EE 42 fall 2004 lecture 25
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Gate Delay
VDD
VDD
S
D
VIN
e
VOUT1
S
D
D
VOUT2
D
e
S
S
• Suppose VIN abruptly changed from logic 0 to logic 1.
• VOUT1 may not change quickly, since is attached to the gates of the next
inverter.
• These gates must collect/discharge electrons to change voltage.
• Each gate attached to the output contributes a capacitance.
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EE 42 fall 2004 lecture 25
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Gate Delay—The Full Picture
VDD
VDD
S
D
VIN
e
VOUT1
D
D
VOUT2
D
e
S
S
•
•
•
S
Where will these electrons come from/go to?
No charges can pass through the cutoff transistor.
Charges will go through the pull-down/pull-up transistors to
ground. These transistors contribute resistance.
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EE 42 fall 2004 lecture 25
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Computing Gate Delay
VDD
VDD
S
D
VIN
S
VOUT1
D
S
D
VOUT2
D
tp = (ln 2)RC
S
1. Determine the capacitance of each gate attached to the output. These combine in
parallel. Higher fan-out = more capacitance.
2. Determine which transistors are pulling-up or pulling-down the output. Each
contributes a resistance, and may need to be combined in series and/or parallel.
3. The C from 1) and R from 2) are the RC for the VOUT1 transition.
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Example
•
Suppose we have the following circuit:
Logic 0 = 0 V
A
Logic 1 = 1 V
B
NMOS resistance
Rn = 1 kW
•
If A and B both transition from
logic 1 to logic 0 at t = 0,
find the voltage at the NAND
output, VOUT(t), for t ≥ 0.
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EE 42 fall 2004 lecture 25
PMOS resistance
Rp = 2 kW
Gate capacitance
CG = 50 pF
10
VOUT(t) = 0 + (1-0) e-t/(2 kW 200 pF) V
Answer
-t/(400 ns)
VOUT(t) = e
•
•
•
V
A and B both transition from 0 to 1. Since VOUT comes out of a NAND of
A with B, VOUT transitions from 1 to 0.
VOUT(0) = 1 V
VOUT,f = 0 V
Since the output is transitioning from 1 to 0, it is being pulled down. Both
NMOS transistors in the NAND were previously cutoff, but are now
active. The NMOS in the NAND are in series, so the resistances add:
R = 2 RN = 2 kW
The output in question feeds into 2 logic gate inputs (one inverter, one
NOR). Each CMOS input is attached to two transistors. Thus we have 2
x 2 = 4 gate capacitances to charge. All capacitances are in parallel, so
they add:
C = 4 CG = 200 pF
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EE 42 fall 2004 lecture 25
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Case #1: VIN = VDD = 5V
The Output is Pulled-Down
VDD
VIN-U
IOUT
VIN = VDD = 5V
VIN-D
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p-type MOS
Transistor
(PMOS)
Output
The PMOS transistor is
OFF when VIN > VDD-VTU
The NMOS transistor is
ON when VIN > VTD
VIN = 5
100
n-type MOS
IOUT(mA)
Transistor
VOUT
60
(NMOS)
EE 42 fall 2004 lecture 25
2
0
0
V3OUT(V) 125
Case #2: VIN = 0
The Output is Pulled-Up
100
IOUT(mA)
60
VDD
VIN-U
IOUT
p-type MOS
Transistor
(PMOS)
Output
2
0
VIN = 0
VIN-D
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n-type MOS
Transistor
(NMOS)
VOUT
EE 42 fall 2004 lecture 25
0
VIN=1V
VOUT3(V)
5
The PMOS transistor is
ON when VIN < VDD-VTU
The NMOS transistor is
OFF when VIN < VTD
13
EFFECT OF GATE DELAY
Cascade of Logic Gates
A
B
D
C
Inputs have different delays, but we
ascribe a single worst-case delay 
to every gate
How many “gate delays for shortest path?
ANSWER : 2
How many gate delays for longest path?
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EE 42 fall 2004 lecture 25
ANSWER : 3
14
Timing diagrams
• To show the time at which logic signals
change, a timing diagram is used. For
combinatorial logic, the diagram will just
show gate delays and glitches
• AND gate:
A
B
A•B
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EE 42 fall 2004 lecture 25
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TIMING DIAGRAMS
Show transitions of variables vs time
A
B
Glitching: temporary
switching to an
Logic state incorrect value
D
1
0
C
Note B becomes valid one gate
delay after B switches
__
t
0 B

t
 2
t

t
 2 3
t
__
Note that ( B C )becomes valid two
gate delays after B&C switch, because
the invert function takes one delay and
the NAND function a second.
( B C )
( A  B)
D
No change at t = 3
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A, B, C
EE 42 fall 2004 lecture 25
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Inverter Propagation Delay
Discharge (pull-down)
VDD
VDD
VOUT
VOUT
VIN =
Vdd
COUT = 50fF
VIN =
Vdd
RD
COUT = 50fF
Dt = 0.69RDCOUT = 0.69(10kW)(50fF) = 345 ps
Discharge (pull-up)
Dt = 0.69RUCOUT = 0.69(10kW)(50fF) = 345 ps
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EE 42 fall 2004 lecture 25
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NMOS and
PMOS use the
same set of
input signals
CMOS Logic Gate
VDD
PMOS only in pull-up
PMOS conduct when input is low
A
B
PMOS do not conduct when
A +(BC)
C
VOUT
NMOS only in pull-down
B
A
NMOS conduct when input is high.
NMOS conduct for A + (BC)
C
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Logic is Complementary and
produces F = A + (BC)
EE 42 fall 2004 lecture 25
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CMOS Logic Gate: Example Inputs
VDD
A=0
B=0
C=0
PMOS all conduct
A
Output is High
B
C
VOUT
B
= VDD
NMOS do not conduct
A
C
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Logic is Complementary and
produces F = 1
EE 42 fall 2004 lecture 25
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CMOS Logic Gate: Example Inputs
VDD
A=0
B=1
C=1
PMOS A conducts; B and C Open
A
Output is High
B
C
VOUT
B
=0
NMOS B and C conduct; A open
A
C
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Logic is Complementary and
produces F = 0
EE 42 fall 2004 lecture 25
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Switched Equivalent Resistance
Network V
VDD
DD
RU
A
A
RU
RU
B
C
VOUT
C
B
Switches
close when
input is low.
VOUT
RD
B
A
RD
B
A
RD
C
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Switches
close when
input is high.
C
EE 42 fall 2004 lecture 25
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Logic Gate Propagation Delay: Initial
State
VDD
The initial state depends on the old (previous) inputs.
RU
A
RU
RU
C
B
VOUT
RD
RD
The equivalent resistance of the pull-down or pullup network for the transient phase depends on the
new (present) input state.
B
A
RD
Example: A=0, B=0, C=0 for a long
time.
These inputs provided a path to VDD
for a long time and the capacitor has
precharged up to VDD = 5V.
COUT = 50 fF
C
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EE 42 fall 2004 lecture 25
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Logic Gate Propagation Delay: Transient
VDD
At t=0, B and C switch from low to
high (VDD) and A remains low.
RU
A
RU
RU
And opens a path from VOUT to GND
C
B
VOUT
RD
RD
COUT discharges through the pull-down
resistance of gates B and C in series.
B
A
RD
C
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This breaks the path from VOUT to VDD
COUT = 50 fF
Dt = 0.69(RDB+RDC)COUT
= 0.69(20kW)(50fF) = 690 ps
The propagation delay is
two times longer than that
for the inverter!
EE 42 fall 2004 lecture 25
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Logic Gate: Worst Case Scenarios
VDD
What combination of previous and
present logic inputs will make the
Pull-Up the fastest?
RU
A
RU
RU
C
B
VOUT
RD
RD
B
A
RD
C
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What combination of previous and
present logic inputs will make the
Pull-Up the slowest?
What combination of previous and
present logic inputs will make the
Pull-Down the fastest?
COUT = 50 fF
What combination of previous and
present logic inputs will make the
Pull-Down the slowest?
EE 42 fall 2004 lecture 25
Fastest
overall?
Slowest
overall?
24
Logic
Gate
Cascade
To avoid large resistance due to many gates in series, logic functions with 4 or
more inputs are usually made from cascading two or more 2-4 input blocks.
VDD
VDD
A1
B2 = VOUT 1
The four independent
input are A1, B1, A2
and C2.
A2
B1
VOUT 1 B2
C2
VOUT 2
B2
A1
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B1
A2
50 fF
C2
EE 42 fall 2004 lecture 25
A2 high discharges
gate 2 without even
waiting for the
output of gate 1.
50 fF
C2 high and A2 low
makes gate 2 wait
25
for Gate 1 output