65550
Video Capture Port
Application Note
Revision 1.1
February 1996
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Copyright Notice
Copyright 1995-96 Chips and Technologies, Inc. ALL RIGHTS RESERVED.
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Revision History
Revision History
Revision Date
0.1
5/26/95
1.0
5/26/95
1.1
2/7/96
Revision 1.1
2/8/96
By
EC/st
ST
LC
Comment
Draft - Internal Review
Officical Release
Removed confidential markings.
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Preliminary
65550
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Table of Contents
Table of Contents
65550 Video Capture Port ......................................................................................................... 1
Introduction ...................................................................................................................... 1
Signals .............................................................................................................................. 1
AC Timing .................................................................................................................................. 2
Registers Description ................................................................................................................. 3
Schematic Example .................................................................................................................... 5
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Application Note
65550
Video Capture Port
65550 Video Capture Port
Introduction
The 65550 provides a flexible interface that can be configured as a VAFC interface, Video Port or as a memory
interface to an external frame buffer for STN-DD panel enhancement. Focusing on the Video Port option, the
65550’s PC video interface is a uni-direction digital video input port that accepts 16-bit YUV data, two
synchronizing signals HREF and VREF, and a pixel rate clock VCLK. Taking the digital video data from this
video port, 65550 can perform video functions such as color space conversion, scaling, zooming, interpolation
and video playback on a 24-bit TFT panel.
The YUV data input to the 65550 video capture port can be in RGB-15, RGB-16 or YUV 4:2:2 format. In YUV
4:2:2 format, eight data bits are allocated for Y (luminance) and eight data bits for UV (chrominance).
Signals
Y
(8 signals)
Luminance data channel
C(U/V):
(8 signals)
Chrominance data channel
HREF:
Horizontal blanking signal
VREF:
Vertical sync signal
VCLK:
Pixel clock for data and HREF and VREF
All pixel and timing data are aligned to the rising edge of VCLK.
65550 Pin Assignments for Video Port interface
Pin #
98
99
100
107
109
110
111
112
113
114
115
116
117
118
120
121
122
104
103
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Name
CA8
HREF
OEC#
MCD1
MCD2
MCD3
MCD4
MCD5
MCD6
MCD7
MCD8
MCD9
MCD10
MCD11
MCD13
MCD14
MCD15
CASCL#
CASCH#
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Video port Name
VREF
HREF
VCLK
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
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Type
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AC Timing
t1
VCLK
YUV and
H/VREF
t2
t3
65550 Video Capture Port AC Specification
Symbol
Parameter
Min
Units
t1
VCLK period
62.5
nS
t2
YUV & H/VREF setup
10
nS
t3
YUV & H/VREF hold
2
nS
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Application Note
Registers Description
MRX: Index register
IO address: 3D2h
All following registers are data registers with IO address ‘3D3h’
MR nn: where ‘nn’ is the Index value in hex
MR02: Acquisition control 1: R/W
0 Interlace
0 Non-interlace (default)
1 Interlace
1 Reserved
2
3
4
5
6
7
Data Format
0 YUV (default)
1 RGB
RGB Format (RGB only)
0 RGB15 (default)
1 RGB16
Hsync Polarity
0 Active low (default)
1 Active high
Vsync Polarity
0 Active low (default)
1 Active high
Field Detect Polarity
0 Normal (default)
1 Inverted
Field Detect Method
0 Trailing edge of V (default)
1 Leading edge of V
MR03: Acquisition control 2: R/W
0 Grab start/stop control
0 Stop (default)
1 Start
1 Continuous/Single
0 Continuous (default)
1 Single
2 Frame/Field Grab
0 Frame (default)
1 Field
3 Field
0 Field 0 (default)
1 Field 1
4 X Scale Enable
0 Full screen (default)
1 Scaled on H
5 Y Scale Enable
0 Full Screen (default)
1 Scale on V
7-6 V Scaling Method
00 Normal (default)
01 Reserved
10 Reserved
11 Reserved
MR04: Acquisition Control 3
0 X Capture Direction
0 L to R (default)
1 R to L
1 Y Capture Direction
0 Top to bottom (default)
1 Bottom to top
2 Horizontal Filter Enable
0 No filter (default)
1 Filter pixels with horizontal filter
3 Reserved
4 Double buffer enable
0 Disable (default)
1 Enable
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Application Note
5
6
7
Double Buffer Pointer
0 Pointer 1
1 Pointer 2
Reserved
Capture Counter Enable
0 Capture single or continuous (default)
1 Capture every ‘n’ field/frame as set in capture_frame-count
MR06: Acquisition Window pointer 1L
7-0
MR11: Acquisition Window X Right MSB
10-8 (3 bits)
MR07: Acquisition Window pointer 1M
15-8
MR12: Acquisition Window Y Top LSB
7-0
MR08: Acquisition Window pointer 1H
18-16 (3 bits)
MR13: Acquisition Window Y Top MSB
10-8 (3 bits)
MR09: Acquisition Window pointer 2L
7-0
MR14: Acquisition Window Y Bottom LSB
7-0
MR0A: Acquisition Window po inter 2M
15-8
MR15: Acquisition Window Y Bottom MSB
10-8 (3 bits)
MR0B: Acquisition Window pointer 2H
18-16 (3 bits)
MR16: Acquisition Horizontal Scale
7-0
MR0C: Acquisition Window Width
7-0 (pixel_width/4: mem-quad
words, scaled if enabled)
MR17: Acquisition Vertical Scale
7-0
MR0E: Acquisition Window X Left LSB
7-0
MR18: Acquisition Capture Framecount
7-0
MR0F: Acquisition Window X Left MSB
10-8 (3 bits)
MR10: Acquisition Window X Right LSB
7-0
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Application Note
Schematic Example
In 65550, the higher 8 bits of panel interface (P16-P23) pins share the same voltage pin (pin 108-MVCCC) with
the video capture port. The example ZV port system schematic shows the 65550 video capture port operating at
3.3V. This is OK as long as a 16-bit panel is used or if a 18/24bit-3.3V panel is used. In other words, if we are
using a panel that has more than 16 data bits and the panel interface is 5V, then the video capture port must also
be 5V.
Note: PCMCIA ZV port could operate at either 5V or 3.3V.
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Chips and Technologies, Inc.
2950 Zanker Road
San Jose, California 95134
Phone: 408-434-0600
FAX: 408-894-2080
Title: 65550 Video Capture Port Specification
Application Note
Publication No.: AN90.1
Stock No.: 020090-001
Revision No.: 1.1
Date: 2/8/96