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11.1 Shift-Add Multiplication
Figure 11.1 Multiplication of 4-bit numbers in dot notation.
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Example
shift-add multiplication: Works
basically like you do "long-hand"
multiplication except that you (1)
add partial products together as
you get them, and (2) shift running
total to the right after it is
recalculated.
This eliminates need to add digits
of the partial product to nothing. It
also ensures same column of digits
are always added. Digits shifted to
the right of these columns are
simply carried down.
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• Recurrence equation describing above process
z ( j 1)  ( z ( j )  y j x 2 k )2 1
with z (0)  0 and z (k)  z
add
Shift right
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Shift-add example: 10100011
Figure 11.2 Step-by-step multiplication examples for 4-digit unsigned binary and decimal numbers.
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Signed integer multiplication
• Signed-magnitude numbers can be multiplied by using the
shift-add algorithm discussed above, and deriving the sign
of the products as XOR of the two input sign bits.
• In the last multiplication step, we must subtract, rather than
add, the partial product yk-1x.
e.g., x  (1011)2’s-compl = -8x +2x+x = -5x
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Example: Two’s-complement multiplication
Figure 11.3 Step-by-step multiplication examples for 4-digit 2’s-complement numbers.
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11.2 Hardware Multipliers
Figure 11.4 Hardware multiplier based on the shift-add algorithm.
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Figure 11.5 Shifting incorporated in the connections to the partial product register rather than as a separate phase.
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Fast hardware multiplication
• Full-tree multiplier
• Array muplier
HA: half adder, FA: full adder, MA: modified full
adder
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Figure 11.6 Schematic diagrams for full-tree and partial-tree multipliers.
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Figure 11.7 Array multiplier for 4-bit unsigned operands.
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8-bit array multiplier (unsiged)
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Figure 11.9 Division of an 8-bit number by a 4-bit number in dot notation.
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• Recurrence equation describing above process
z ( j )  2 z ( j 1)  y k  j x 2 k
with z (0)  z and z (k)  2 k s
shift
subtract
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Unsigned operands, z: 2k-bit, x: k-bit
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Figure 11.10 Step-by-step division examples for 8/4-digit unsigned binary integers and decimal fractional numbers.
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Unsigned operands, z: k-bit, x: k-bit
Figure 11.11 Step-by-step division examples for 4/4-digit unsigned binary integers and fractional numbers.
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Dividing signed number:
(1) Convert operands to into unsigned values, perform
unsigned division
(2) At then end, adjust signs for y (quotient) and s (remainder)
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11.5 Hardware Dividers
k cycle for 2k/k division
Figure 11.12 Hardware divider based on the shift-subtract algorithm
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Figure 11.13 Shifting incorporated in the connections to the partial remainder register rather than as a separate phase.
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Figure 11.14 Array divider for 8/4-bit unsigned integers.
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Array Divider (unsigned)
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Conditional Subtractor
• q=0
– co = majority ( r, d, ci ) ;
– s=r
// identity
• q=1
– co = majority ( r, d, ci ) ;
– s = r XOR d XOR ci // subtraction
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11.6Programmed Division
Figure 11.15 Register usage for programmed division superimposed on the block diagram for a hardware divider.
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