psASIC Timing Generator
Fukun Tang
psASIC Design Review July 1-2 2009
University of Chicago
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Diagram of 40Gs/s Sampling Chip
PD: Phase Detector
Timing Generator with 2 DLLs interleaved
PD
CP: Charge Pump
LF: Loop Filter
LF
CP
CC: Coarse Counter
CLOCK
(80MHz)
CU: Control Unit
CC
φ250
φ1
Coarse_Data
IN(1:32)
clr
Sampling Cells
CTRL_bus
Vth
CU
Freeze
Ex_trig
Rd250
ADC1
ADC250
C250
C1
Rd001
ADC_Data
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Requirements of Timing Generator
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80MHz input clock.
125 sampling control signals
50ps delay time per cell.
Delay tuning range of delay >10% for DLL in next
version.
50% duty-cycle (If we can)
True differential (If we can)
1.2V Voltage
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Principle of Timing Generator
Input Clock: 80MHz (T=12.5ns)
Output clock phases: 125/Cycle
Time delay per phase: 50ps
Voltage controlled time delay
φ1
φ125
Clock
(80MHz)
VCp
VCn
50ps
Not scaled timing diagram
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Track-and-Hold Timing & Sampling Bandwidth
Switches of half a switch-chain are
sequentially on for tracking, the rest of
switches are sequentially off for holding.
Analog input pulse: Tr=Tf=Tw=100ps
φ1
φ2
Rt
φ125
φ2
φ1
0250
track
φ125
hold
φ1-φ125
In
Rt
Cin
Rs
Out
Sampled Pulse
Cs
Analog Bandwidth is determined
by a simplified 2-pole system
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Current Starved Single-ended Voltage-Controlled Delay Cell
Driver/buffer
To sampling switch
To next delay cell
A Single Delay Cell
VCDL stage
Restoration stage
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VCDL Simulation Results (125 Cells)
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Phase Outputs from cell-116 to cell-124
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Cell Layout
Single delay cell
4 of 125 cells
1.2mm x 15 microns
8 x 15 microns
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Voltage-Delay (V-D) Chart
Delay with post layout is 30% longer
than schematic simulation !!!
10Gsps:
12.5ns@550mV
Delay time
Post Layout Simulation
13.9Gsps:
9ns@800mV
Schematic Simulation
Control Voltage
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Discussion of Sampling Window
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Sampling window and input bandwidth.
Minimum sampling window and sampling time
constant
Sampling window control logic
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Sampling Window and Analog Input Bandwidth
Die
Rt
Package pin
Analog bandwidth can be modeled as a simplified 2-pole system
In
Rt
Cin
Rs
Out
Cs
Cs
Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all
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Minimum Sampling Window and Sampling Time Constant
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Ron
Sampling time constant (RonCs)
Switch on-resistance (Ron)
Minimum sampling window:
(Tw_min)= 2.2RonCs
Δt
Δt
If Ron = 4k, C = 40f. RonCs = 160ps
Tw_min = 2.2RonCs = 352ps Æ 7 sampling steps (50ps each)
Assuming 2Tw_min used, then Tw should be set at lest 14 sampling
steps (700ps).
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Window Control Logic
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NAND gate:
A sample 14-input and gate can be used to set sampling window.
---disadvantage: Two many stages of circuitry to make AND14, each tap have to drive
14 loads
φn
Φn+14
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(2) dff:
-- disadvantage: too much layout area used.
φn
Φn+14
φn
CK
Φn+14
R
Tw
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Summary
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Schematic and post layout simulations have been
done.
Post layout simulation showed a sampling rate of
10Gsps to 14Gsps can be achieved without
interleaving.
Same VCDL cell has been used for 2-GHz voltage
controlled ring oscillator (see Emilien’s talk).
125-cell schematic and layout blocks are available
for top-level design.
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Thank you for your review
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Backup Slides
Why Not Differential VCDL?
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Schematic and Layout of Replica Diff. Delay Cell
A Single Replica Differential Delay Cell
Restoration
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Dummy Load
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Schematic Simulation for 125 Cells
Delay time
V-D Chart
20Gsps:
50pS
Controlled Voltage
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Post Layout Simulation (Never Work!)
DL1
DLn
DL2
DL125
50ps
Fail
Fail
Unequaled parasitic capacitance in layout causes delay difference in positive
and negative nodes of each cell. If accumulated delay difference is greater
than 50ps in a chain of 125 cells, the delay chain went to malfunction. There is
no way to tune the layout for such tight matching!
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Backup Slide-2
Input Analog Bandwidth, Sampling Time Constant and Minimum Sampling Window
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Modeling of Input Bus and Sampling Cells With Sampling
Window of 3.25ns (64 cells)
Cin
64 cells in tracking, (3.2ns sampling window).
R64=4k/64 = 62 ohm
C64 = 4k * 40f = 2.5pF
Cin = 2pF
Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all
Terminator = 50 ohms
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Modeling of Input Bus and Sampling Cells
With Sampling Window of 640ps (13 cells)
Cin
13 cells in tracking (640ps sampling window).
R64 = 4k/13 = 300 ohm
C64 = 13 * 40f = 0.5pF
Cin = 2pF
Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all
Terminator = 50 ohms
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Comparison of Simulation Results
Input Step Current
640ps window
3.2ns window
Sampling Cell Step Response
508ps
765ps
Input Bus Step Response
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From Step Response Simulations:
Sampling cell with 640ps sampling window, it has a rise
time (10%-90%) of 508ps, equivalent to an analog
bandwidth of 689MHz.
Sampling with 3.2ns sampling window, it has a rise time
of 765ps, equivalent to an analog bandwidth of 457MHz.
We need simulate our circuits to evaluate our design for
input analog bandwidth…
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