Technologies for
LHC Upgrades
An Example: The GBT Link
A. Marchioro
CERN, Div. PH
1211 Geneva 23, Switzerland
A.Marchioro - CERN/PH
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Overview
‹ How
can modern technologies improve
particle physics detectors (without
exploding their costs)
‹ The
GBT: A new general purpose
optical link ASIC for Trigger, Timing,
Data and Slow Control
A.Marchioro - CERN/PH
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CMS Tracker
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Areas for improvements
‹ Performance
–
Functionality
– Precision
– Reduce overall detector (passive) materials
‹ Key technologies
» Microelectronics
» Optoelectronics [not discussed here]
‹ Fabrication
and assembly cycles [not
discussed here]
‹ Cost (reduction) [not discussed here]
A.Marchioro - CERN/PH
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New SLHC Tracker wish list
Sustain 10 x more
hits/unit area
Higher detector
segmentation, i.e. more
channels
Higher power,
more cooling,
more materials
More (local or long-haul)
interconnectivity
Higher bandwidth
More cabling,
higher power,
more cooling,
more materials
Less (how much?)
mass /unit volume
Prompt triggering
capability on tracks
A.Marchioro - CERN/PH
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CMOS Technology Roadmap
SLHC
Starts here
There is no doubt that industry will be well ahead
of the requirements from HEP, even considering a
Luminosity upgrade of 10x
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From ITRS 2005
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Technologies used in ISSCC2006/7 papers
Percentage of papers
Trends 2006/2007
30.0%
25.0%
20.0%
2006
2007
15.0%
10.0%
5.0%
0.0%
>
0.8
0.5 0.35 0.25 0.18 0.13
90
65
< 65 Bip
Technology
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Example of 130 nm potential
Scale is the same
12 bit microprocessor core
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IO cell
8
How many more generations?
‹
“The end of the planar FET
is close, but perhaps one or
two generations can be
added if newer transistors
can be made, for example
the ‘FINFET’”
G. Moore, 2003
A.Marchioro - CERN/PH
Notice dimension of spacer
compared to device
9
Performance? Yes, but at a cost…
Source: Infineon
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Performance
‹ Depends
on:
– Investment in technologies, tools and
people
– Sharing of expensive tools
– Organization of engineering groups with
sizes above critical mass
– Ability of creating minimal volumes to
make investment affordable
– Re-use parts already existing (purchase
IPs instead of usual ‘NIH’ strategy)
A.Marchioro - CERN/PH
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Improving: Performance
‹ Improving
performance can be
achieved by following industry’s
trend, as a example, the efficiency of
AD converters has been improving
regularly over the last years
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Improvements in AD conversion
Power
FM =
Freq * 2 ^ ENOB
NS
In
fin
e
Sa o n
m
su
ng
NS
IT
+
M
So
ny
M
CS
D
U
ilip
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IT
+
2006
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at
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CB
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In D
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on D
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ct
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N
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St SI
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Br fo rd
oa
dc
om
Te
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In
fin
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n
hi
pi
de
a
.M
U
ni
v
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CS
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Ta
iw
an
in
ne
so
ta
5.00E-12
4.50E-12
4.00E-12
3.50E-12
3.00E-12
2.50E-12
2.00E-12
1.50E-12
1.00E-12
5.00E-13
0.00E+00
U
J/op
Powe r Efficie ncy - ISSCC 2004 & 2006
ENOB assumed = N_bits - 1
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Manufacturer
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Improvements in ADC
‹
For Tracker
–
–
–
–
–
‹
Assuming FM for ADC of: 2.5e-13 J/op
fsample = 40 MHz
Nbit = 6 (with ENOB = 5)
128 channels/chip
Total Conversion Power: 40 mW
» to be compared to today’s total FE chip power of ~320 mW
For Calorimeter
–
–
–
–
Assuming FM for ADC of: 2.5e-13 J/op
fsample = 40 MHz
14 bit converter
Conversion: 82 mW
» To be compared with 125 mW today for a 12 bit device
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Data links (1)
25 Gb/s CDR in 90 nm CMOS
paper from IBM 2006
‹
Needs local Xtal reference
‹
Range 8-28 Gb/s
‹
Power: 172 mW @ 1.1 V
Eye diagram at ½ rate
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Data links (2)
‹ Preview
–
–
–
–
summary of 2007 ISSCC
4 papers @ < 10 Gbit/s
4 papers @ 10 Gbit/s
4 papers @ 16-20-33 Gbit/sec
2 papers @ 40 Gbit/s
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Some brief results on 130nm CMOS
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Core 130nm NMOS transistors, enclosed layout
NMOS ELT min/0.12
1.00E-03
1.00E-04
1.00E-05
1.00E-06
Pre-rad
Id (A)
G
1.00E-07
3Mrad
1.00E-08
136Mrad
2d HT ann
1.00E-09
1.00E-10
1.00E-11
1.00E-12
-0.2
0.3
0.8
1.3
Vg (V)
PMOS ELT min/012
D
1.E-03
S
1.E-04
1.E-05
Id (A)
1.E-06
1.E-07
pre-rad
3 Mrd
40 Mrd
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
-0.2
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0.3
0.8
Vg (V)
1.3
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Core 130nm NMOS transistors, linear layout
Effect on the leakage current
1.E-05
– Peak in leakage @ TID of 1-5Mrad
– Peaking dependent on dose rate
and temperature, difficult to
estimate in real environment
– Good recovery, strong indications
that ELT is not needed for regular
digital
0.16/0.12
0.32/0.12
0.48/0.12
0.8/0.12
2/0.12
10/1
10/10
ELT
1.E-06
Ileak (A)
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E+05
pre-rad
1.E+06
1.E+07
1.E+08
TID (rad)
1.E-05
1.E-05
1.E-06
1.E-06
1.E-07
1.E-07
Ileak (A)
Ileak (A)
‹
1.E-08
N_10_013
1.E-09
N_10_012
N_088_012
N_053_012
N_024_013
N_018_013
1.E-10
N_028_012
1.E-10
N_014_013
1.E-11
1.E+04
1.E+05
A.Marchioro
- CERN/PH
pre-rad
1.E+06
1.E+07
TID (rd)
1.E+08
1.E+09
annealing
N_10_10
1.E-08
1.E-09
N_04_013
Foundry B
N_016_012
1.E+09
Foundry A
1.E-11
1.E+04
pre-rad
1.E+05
1.E+06
1.E+07
TID (rd)
1.E+08
annealing
1.E+09
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Foundry C
Heavy Ion irradiation results
– Cross-section 15-30 times
larger in LHC environment
/bit)
2
Cross-section (cm
1.E-08
1.E-09
Vdd=1.5V
Vdd=1.25V
Weibull
1.E-10
0
5
10
15
20
25
30
35
40
45
50
2
LET (Mev/cm mg)
1.E-07
/bit)
‹
1.E-07
2
‹
Test at Vdd=1.5 and 1.25
V, results very similar
Sensitivity to very low
LET values (threshold
below 1.6 MeV/cm2mg)
Comparison with 0.25μm
memory (rad-tol design!!):
Cross-section (cm
‹
1.E-08
0.13um SRAM @ 1.5V
1.E-09
Weibull 0.13SRAM
0.25um SRAM
Weibull 0.25SRAM
1.E-10
0
5
10
15
20
25
30
35
40
45
2
LET (MeV/cm mg)
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Common SLHC infrastructure ASIC:
the GBT
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From 3 links to one
Separate detector links
TTC
ECS
Global trigger
Global TTC
Trigger
processor
TTC driver
ECS
Global ECS
ECS interface
Local
trigger
extraction
Trigger links
TTC link
TTC and ECS
distribution
ECS link
detector
TTC
ECS
Hybrid
DAQ interface
Readout links
Global DAQ
Link interface chip
Fully combined detector links
Global TTC
Global ECS
Global DAQ
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Combined:
TTC driver
ECS interface
DAQ interface
detector
Combined links
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GBT general architecture
Timing & Trigger
Timing & Trigger
DAQ Path
Slow Control
A.Marchioro - CERN/PH
DAQ Path
Multi-purpose
Link speed: ~ 4 Gbit/s
Bidirectional
64 bit data/bunch crossing
8 bit of trigger /bunch crossing
SLHC clock synchronous
Fully SEU robust
Two fibers/link
Slow Control
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Timing distribution
Timing & Trigger
DAQ Path
Slow Control
‹
‹
‹
‹
‹
‹
Timing & Trigger
DAQ Path
Slow Control
Unidirectional
Multiple outputs from same GBT with separate
fine skew control
40 MHz (or 20) with 50 ps steps
Jitter < 10 ps
Trigger mask: 8 bit/BC
Fully programmable Bunch Emulator with 8 outputs
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Data Path
Timing & Trigger
DAQ Path
Slow Control
‹
‹
‹
‹
Timing & Trigger
DAQ Path
Slow Control
Fully bi-directional
64 bit @ 40 MHz
Fully error corrected up to 16 errors/frame (i.e. can survive
after severe photodiode degradation)
Simple parallel protocol or sophisticated “standard bus”
– Some amount of fan-in capability under evaluation
‹
Priority selectable for data/slow control traffic
A.Marchioro - CERN/PH
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Slow control
Timing & Trigger
DAQ Path
Slow Control
‹
‹
Timing & Trigger
DAQ Path
Slow Control
Bi-directional (but not physically symmetric!)
Implements most commonly used protocols on
terminal side: I2C, JTAG, SPI, simple parallel etc.
– Master side has industrial standard bus
‹
Option: Implement slave side on separate ASIC
and keep GBT fully symmetric
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TTC vs. GBT
Trig
‘B’
1
HDR
Trig
4
8
1
DATA
FEC
64
32
User
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GBT Internal Block diagram
Block 1:
• Pin - receiver
A.Marchioro
CERN/PH
• Laser driver
Block 2:
• SerDes
• CDR
• CODEC
Block 3:
• TTC functions
• Standard bus
•…
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Common building blocks
‹ Project
–
–
–
–
–
–
supported by CERN-PH
Common CMOS technology for all
GBT
Voltage regulators (chips and blocks)
Switching regulators
Analog blocks (…)
Please suggest
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