International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
Design and Simulation of Start Frame Delimiter
& Buffer of Ethernet MAC Receiver
Sandeep Kalundrekar 1 , Amit Singh Rajput2
1,2
EC-ITM, Gwalior(M.P.)
Abstract
The paper aims to provide suitable RTL design for MAC Receiver. Here the receiver supplies receive data to the host system from
the receive data stream. It detects the preamble and SFD, checks the length field, and executes CRC check. Status information on
each received packet, such as the number of received bytes and occurrence of errors, is written to a register after reception has
been completed.
What is Ethernet?
Ethernet is the most widely used local area network (LAN) technology. The original and most popular version of Ethernet
supports a data transmission rate of 10 Mb/s. Newer versions of Ethernet called "Fast Ethernet" and "Gigabit Ethernet"
support data rates of 100 Mb/s and 1 Gb/s (1000 Mb/s). Ethernet devices compete for access to the network using a
protocol called Carrier Sense Multiple Access with Collision Detection (CSMA/CD)
System Diagram
Here we are using data sheets of 82595 TX-Ethernet Controller provided by Intel and µPD98431 10/100 Mbps Ethernet
Controller by NEC corporation for specification.
Receiver Processing Algorithm
Figure 1: Receiver Algorithm
IEEE 802.3 Frame Format
The frame format of IEEE802.2 is shown below
Figure 2: MAC Frame IEEE 802.2
Volume 2, Issue 11, November 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
Block Diagram
Figure 3: Internal Block Diagram of Ethernet MAC Receiver
The Receiver Subsystem
1. SFD Detector: This component helps in the detection of the start of the packet.
2. Buffer: This is the buffer that forms the entry point of data into the receiver. This may or may not pass on the data
to the memory based on the state of the receiver.
3. Address Matching Logic: This component verifies whether the data coming in is actually of concern or not. It
compares the destination address of frame with host destination address.
4. FCS Checker: This component does the error checking by computing the CRC and then checking it with the
trailer of the frame.
5. Controller: This is component that forms the glue between all the other component
Work
In this paper we are giving simulation Buffer & SFD.
Buffer
Signal
Type
Description
rx_data[3:0]
In
Data (nibble)transferred from MII
data [3:0]
Out
Data (nibble)transferred from buffer to FIFO
data_sa 3:0]
Out
Data (nibble)transferred from buffer to SFD detector and AML
data_enable
In
Clock
In
Enable signal from rx state machine to open the buffer and lets data[3:0]
delivered to FIFO
Clock signals from MII
reset_n
In
Active low signals that initializes the receive MAC function
Table 1: Signal Descriptions of Buffer
Description
The function of this module to do data de capsulation. This module continues gives data to SFD detector and AML. And
pass rx_data to the FIFO when darta_enable is high. It means it hold packet data .i.e. when data_enable is high then only
it can pass data to FIFO.
Flow Chart
Volume 2, Issue 11, November 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
start
no
yes
rseet_n=0
data_sa=rx_data
data_temp=data_sa
data_sa=0000
yes
data_temp=0000
data_enable=1
no
data=zzzz
data=data_temp
stop
Figure 3: Flow Chart of Buffer
Start Frame Delimiter
Signal
Type
Description
sfd_start_detect
In
A single clock signals gives instruction to SFD detector to begin to
detect the SFD
data_sa[3:0]
In
Data (nibble) transferred from MII
sfd_detected
out
This signal indicates that SFD has detected.
Clock
In
Clock signals from MII
reset_n
In
Active low signals that initializes the receive MAC function
Table 2: Signal Descriptions of SFD
Description
SFD_Detector has the data flowing in through the data_sa. When the module receives a sfd_start_detect signal, it starts
detecting SFD bits in the preamble, when it detects the SFD, it enables the sfd_detected signal.the sfd_start_check signal
come from controller State Machine that launched after rx_dv asserted This module is control by controller ,when ever
MII sense carrier on cable it give rx_data_valid signal to controller, now controller know that some frame is coming ,and
now it has to receive it. We can say that when rx_data is coming SFD_start_detect signal will high and will be high until
SFD_detected equal to one, after that it will become zero.
Flow Chart
start
no
sfd_start_detect=0
yes
rseet_n=0
yes
sfd_detected=0
no
no
data_sa=1011
yes
sfd_detected=1
stop
Figure 4: Flow Chart of Start Frame Delimiter
Volume 2, Issue 11, November 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
Functional Simulation Results
For Buffer
Figure 5: Simulation Result of Buffer
When data_enable signal comes from controller
Figure 6: Simulation Result of Buffer When rx_error Come in Controller
Figure 7: Simulation Result of Buffer When rx_data_valid Low
For SFD Detector
Figure 8 : Simulation Result of SFD
Functional simulation result of Integration of SFD and Controller when sfd is detected. The sfd show the start of frame.
Volume 2, Issue 11, November 2013
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org, editorijaiem@gmail.com
Volume 2, Issue 11, November 2013
ISSN 2319 - 4847
Figure 9: Simulation Result of SFD
References
[1] http://developer.intel.com/design/network/datashts/28163001.pdf
[2] ftp.adelaide.edu.au/pub/rocksoft/crc_v3.txt
[3] ftp://rtfm.mit.edu/pub/faqs/LANs/ethernet-faq
[4] http://www.get2chip.com/index.asp
[5] 10/100 Mbps Ethernet LAN controller hardware reference manual, Intel, 1998.
[6] Ethernet Controller Cirrus-Logic μPD98431
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