2012 International Conference on Solid-State and Integrated Circuit (ICSIC 2012)
IPCSIT vol. 32 (2012) © (2012) IACSIT Press, Singapore
Low Power Adders for MAC Unit Using Dual Supply Voltage in DSP
Processor
1
2
B. Sathiyabama1, Dr.S.Malarkkan2
Research Scholar, Sathyabama University, Chennai- 600119, India.
Principal, Manakula Vinayagar Institute of Technology, Puduchery, India.
Abstract. A new efficient power optimized adders are proposed for the Multiplier Accumulator
unit (MAC) in DSP applications. Deploying multiple supply voltages (multi- VDD) is a utile
technique for reducing the power consumption without sacrificing the speed in integrated circuits.
This technique is used for adder design. To transfer the signal among the circuits operating at
different voltage levels, specialized voltage interface circuits are required. In this paper three
optimized level converters are designed and simulated in different voltages 0.4 to 1.5 (VddL) and
2.5 (VddH) in first phase, then 4-bit ripple carry adders are designed using these level converters in
the second phase. Our technique is simulated using HSPICE with MOSFET level 3 model at
180 nm technology and is aimed at achieving optimized power consumption on Adder design.
Keywords: Dynamic power, Low power CMOS circuits, MAC unit, Power Delay Product
1. Introduction
In real-life embedded devices like mobile phone, notebook computers are made use of RISC processor
and DSP. Mostly the digital processing requires high speed and low power multiplier accumulator (MAC)
unit. The multiplication and addition are the important operations in this unit. Specifically, speed and power
efficient implementations of adders are a very challenging problem. With the increase in complexity of VLSI
systems and limited amount of power available in certain scenarios like cell phones and digital cameras,
minimizing power consumption has clearly become a priority.
Lowering power consumption not only increases reliability but also leads to savings in package costs as
the result of reduced heat dissipation. The main contributor to overall power dissipation in CMOS VLSI
circuits is dynamic power consumption which accounts for up to 80% of the total power [1]. Dynamic power
dissipation results from charging and discharging of the wire and transistor capacitive loads. The dynamic
power dissipation of a CMOS circuit can be described by [2].
P= . CL. V2DD fCLK , where is the switching activity; CL, the total load capacitance; VDD, the supply
voltage and fCLK is the operating clock frequency. Consequently power reduction can be achieved by
decreasing one of the factors of the formula. The most popular choice is to lower VDD because of its quadratic
relationship with power. An effective method for reducing the power consumption is scaling the supply
voltage. Dynamic, short-circuit, and leakage components of power consumption are simultaneously reduced
with the scaling of the supply voltage in a CMOS circuit. If supply voltage is reduced, it degrades the circuit
speed. The multi-VDD circuit technique exploits the delay differences among the different signal propagation
paths within an integrated circuit (IC) [3-4].
67
Three dynamic power management methods are important in submicron technology; they are operand
isolation, operand pre-computation and multiple supply voltage (Multi-VDD). A system which uses more
than one power- supply voltage is known as Multi-VDD system [4,5]. The supply voltages of the gate on the
noncritical delay paths are selectively lowered while a higher supply voltage is maintained on the critical
delay paths so as to satisfy a target clock frequency in a multi-VDD circuit. Similarly, in systems-on-chips
(SoCs), different circuits operating at different supply voltages exist. Low-to-high level shifters are required
to convert signals from low-VDD to high-VDD .Utilization of level shifters low-to-high, ensures proper
calculation of transition times and switching. Figure 1.shows the level shifter using dual supply and single
between two different domains.
Fig.1.a.Two power- supply voltages
b. Single power-supply voltages
.
In this paper, low power adders are designed based on dual supply voltage technique is proposed. Three
different level converters are simulated and new adders are designed with these level converters. The
performances are analyzed and compared. This paper is organized as follows. Section II presents a brief
description of the level converters and their performance. Section III gives the full adder and its performance.
Section IV presents the simulation and discussion for the dual supply Vdd technique for the adders. Section
V concludes with conclusion and summary.
2. Level Converters
Level converters are required whenever a module at lower supply voltage has to drive a gate at the
higher voltage. In such a case, the PMOS transistor in the driven gate is never turned off, resulting in static
current and reduced output swing [5,6]. The problems can be prevented by applying level conversion at these
interfaces. Low-to-high level shifters are required to convert signals from low-VDD to high-VDD and
prevent short circuit current in the device at high VDD due to partial turn-off of the PMOS transistors.
A multi-VDD approach is presented in [6] whereby gates off the critical path are allowed to operate at
low VDD (VddL) and gates on the critical path operate at high VDD (VddH). This methodology allows a
significant power reduction without compromising the performance of the circuit. Figure 2.a. shows a basic
asynchronous converter based on positive feedback [6, 7] which is used in adder design. The effect of level
converters on the overall performance of the adder is minimal since the conversions are required only at the
transitions from lower to higher supply voltage units.
Fig.2: a. Standard level converter, Design I, b: Level converter, Design II,
68
c: Level converter, Design III.
The standard feedback-based level converter is shown in Fig.2.a [6], M1 and M2 experience a low gate
overdrive voltage (VddL-Vth) during the operation of the circuit. M1 and M2 need to be sized larger to
produce more current when compared with M3 and M4, respectively, for functionality. The circuit operates
as follows. When the input is at 0 V M2 is turned off, Node1 is charged to VddL and M1 is turned on. Node3
is discharged to 0 V turning M4 on. Node2 is charged to VddH turning M3 off. The output is pulled down to
0 V. When the input transitions to VddL, M2 is turned on. Node1 is discharged, turning M1 is off. Node2 is
discharged, turning M3 on.Node3 is charged up to VddH turning M4 off. The output transitions to VddH. A
feedback loop, isolated from the input, controls the operation of M3 and M4 during both transitions of the
output.
Due to the transitory contention between the pull-up and the pull-down networks and the large size of the
nMOS transistors (M1 and M2), however, LC consumes significant short-circuit and dynamic switching
power. To maintain functionality with the lower values of VddL, the sizes of M1 and M2 need to be further
increased in order compensate for the gate overdrive degradation. The load seen by the previous stage (driver
circuit) is therefore increased, thereby further degrading the speed and increasing the power consumption [7].
To overcome the drawback, level converter-Design II is designed which is shown in the Fig .2.b.The circuit
operation is similar to Design I. since it requires more no of transistor, Design III is proposed as shown in
Fig.2.c.This level converter employs a multi-Vth CMOS technology so as to eliminate the static DC current.
These optimized level converters are utilized in Adder design.
3. Adders
The basic building block of the MAC unit is the one-bit full-adder [8] and it is one of the speed limiting
elements. Hence optimization of the adder both in terms of speed and power consumption should be
considered. The output function of the adder can be described by the following Boolean expression
(1)
Where H = A B is the half adder. This implementation saves the resource by sharing the repetitive
XOR gate and less voltage swing. Fig. 4.a. shows the transistor schematics of the low power full adder unit
based on the low power XOR and XNOR cells with transistor sizing [8-10]. Figure 2.b shows the layout
view for low-power full Adder circuit,
Fig 4: a. Transistor schematics of the proposed 1bit full adder, b. Layout view of the full Adder
The proposed 4- bit ripple carry adder is designed using optimized low power full adder and level
converter. The level converters are connected to the carry of the adder module .The level converters and
69
adders at the end of the chain have more switching activity than the ones at the start of the chain. This is
because the carry bit from the previous stage keeps rippling through the next stages. So, stage 4 will have
more ripple than stage 3, which in turn will have more ripple than the previous stages. The width of the
transistor is altered from 2.0 to 0.5µm to obtain the optimized adder using sizing algorithm. Thus it is good
to have smaller-sized transistors at the end of the chain to minimize energy consumption.
5. Simulation and Comparison
The level converters and adders are simulated and performances are analyzed for different operating
voltage levels using the HSPICE parameters of a 180-nm digital CMOS technology. The proper Simulation
Setup for characterizing the level converters is used for testing and optimization .The simulation is carried
out in two phases. In first phase, the level converters are simulated with optimization (HPICE optimizer) for
the supply voltages with VddH = 2.5 V and VddL = 1.5 V, 1.0 V, 0.5 V, 0.4 operating temperature at 70˚C.
Table I summarize the performance of the level converters at different VddL = 1.5, 1.0, 0.5, 0.4 and
VddH = 2.5 at 70˚C.
Table 1 Performance of the level converters and at VddL = 1.5, 1.0, 0.5, 0.4 and VddH = 2.5 at 70 ˚C
Level
converter
Design-I
Design-II
Design-III
a. Design I
VddL
VddH
Power(w)
Delay(s)
1.5
1.0
0.5
0.4
1.5
1.0
0.5
0.4
1.5
1.0
0.5
0.4
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
4.5E-7
7.5E-7
1.5E-8
7.2E-11
1.0E-7
1.2E-7
6.4E-8
2.0E-9
2.04E-7
5.11E-8
5.8E-9
2.8E-11
1.19E-9
1.19E-9
1.19E-9
1.19E-9
1.92E-9
1.92E-9
1.92E-9
1.92E-9
2.0E-9
2.0E-9
2.0E-9
2.0E-9
b. Design II
c. Design III
Fig.6: Input and output waveform of the level converter at VddL = 0.5 V, VddH = 2.5 V
The Table II gives the comparison of power and delay performance of the level converters and at lower
voltage VddL =0.5 and higher voltage VddH=2.5. Figure 6 shows the input and output waveform of the level
converter Design I. In the second phase the 4-bit ripple carry adders are simulated without and with the level
converter for the supply voltages with VddH = 2.5 V and VddL = 0.5 V operating temperature at 70˚C using
HSPICE software in 0.18µm technology. Table III shows the performance of 4-bit ripple carry adder at
VddH = 2.5V and VddL = 0.5V.The Figure 7 shows input (3inputs) and output waveforms of the 4-bit ripple
carry adders with level converter design III at VddL = 0.5, VddH = 2.5.Adder with Design III consumes less
power compared with other design. The power performance of 4 –bit ripple carry adders with different level
converter is shown in Fig.8.
70
Table 2 Power and delay performance of the level converters and at VddL = 0.5 V and VddH = 2.5 V.
Level
converter
Design-I
Peak
power(w)
3.06E-8
Average
Power(w)
1.5E-8
Delay(s)
Design-II
1.06E-8
6.40E-8
1.92E-9
Design-III
1.1E-9
5.8E-9
2.0E-9
1.19E-9
Table 3 Performance of 4-bit ripple carry adder at VddH=2.5V and VddL=0.5V
Module
Adder without level converter
Adder with design I
Adder with design II
Adder with design III
Average Power (w)
6.8045E-05
1.2116E-05
1.3711E-05
6.0312E-06
Fig. 7: Input and output waveform of the adder
with Design III at VddL=0.5V, VddH=2.5V
Fig.8: Power performance of 4 bit ripple carry adders
5. Conclusion
In this paper, low power 4-bit ripple carry adders are proposed using dual voltage technique for the MAC
unit. The design was carried out in two phases. In first phase three different level converter circuits are
designed with transistor sizing and its performances are analyzed and compared, in second phase low power
4- bit ripple carry adders are designed using one bit low power adder and these three level converter Design.
Optimized 4-bit adder is designed with different level of voltages (VddH=2.5V and VddL=1.5, 1.0, 0.5.0.4V)
which is used for MAC unit of DSP processor. The multi-voltage technique is introduced for minimizing
power in adders. Adder with Design III consumes less power compared with other designs. All designs are
simulated using HSPICE in CMOS 180 nm technology process. The proposed dual supply voltage (multi
Vdd technique) adders have better power efficiency(more than 50%) when compared ordinary 4- bit adder
with area tradeoff.
6. References
[1] D. Soudris, C. Piguet and C. Goutis (eds), Designing CMOS Circuits for Low Power, Kluwer academic publishers.
[2] J. Rabaey, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice-Hall, 2003.
[3] Pedram, Power Minimization in IC Design, ACM Transactions on Design Automation of Electronic Systems, Vol.
1, No. 1, pp. 3-56, January 1996.
[4] D. E. Lackey et al., “Managing power and performance for system-on-chip designs using voltage islands,” in
Proc. IEEE/ACM Int. Conf. Comput.Aided Des., Nov. 2002.
[5] Cary Chin, Hybrid Techniques Reduce Dynamic Power Consumption, Synopsys, Inc.2010
[6] Usami and M. Igarashi, Low-Power Design Methodology and Applications utilizing Dual Supply
Voltages, IEEE , 2000.
[7] S. H. Kulkarni and D. Sylvester, High performance level conversion for dual VDD design,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 926–936, Sep. 2004.
[8] Shamas and M. Bayomi A novel high performance CMOS 1-bit full adder cell, IEEE trans. Circuits and
71
systems, vol. 47, pp 478-481, May 2000.
[9] C. Wey, C.H. Huang and H.C. Chow, A New Low-Voltage CMOS 1-Bit Full Adder for High Performance
Applications, IEEE, pp. 21- 24, 2002.
[10] Nikoubin, T., Pouri, S., Bahrebar, P., and Navi, N., A New Transistor Sizing Algorithm for Balanced
XOR/XNOR Circuits, 12th International CSI Computer Conference, CSICC 2007,
72