PRIYADHARSHINI S

• To reduce power consumption in a 32-bit adder circuit by reducing the voltage of operation
• To study the effect of voltage reduction on the delay of the circuit
• To identify an optimal voltage of operation at which the power-delay product is low
• To design a level converter to make the circuit compatible with other circuits
2

• ModelSim: To verify the functionality of the circuit
• Leonardo Spectrum: To synthesize the verilog gate level netlist
• MATLAB: To synthesize the netlist compatible with
PowerSim
• Design Architect: To obtain the transistor level design of gates
• LTSpice: To evaluate the delays of individual gates
• PowerSim: To assess the performance of the circuit at different voltages
3

4
ModelSim
(functional verification)
VHDL behavioral file
(adder.vhd)
Outputs Gate-wise simulation in LTSPICE
Leonardo
Spectrum
Delay file (.randlf)
Powersim
(executable file from .cpp files)
Technology file
45nm
Verilog gate level netlist – 180nm
(adder.v)
Input vectors file
(generated by randomgen.cpp)
MATLAB conversion code
Rutgers Mode compatible netlist
(adder.myrutmod)
PowerSim Tutorial – Manish Kulkarni http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html

• I = K (V
GS
•
R α 1/I
- V
T
) 2 / 2
•
Resistance increases as voltage reduces
•
Time constant = RC
•
Delay increases as voltage decreases
0V
5

• Dynamic Power = αCV 2
• Dynamic Power reduces with voltage reduction
6
Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold
Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State
Circuits, Aug 1997, Volume 32, Issue 8 http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.h
tml - Lecture 4 Power Dissipation of CMOS circuits

• Dynamic power α V 2 f
• Power = kV 2 /T
• At a voltage of 1.1 V (normal operation)
▫ Dynamic power = 232.72 µW
▫ T = 650 ps
▫ => k = 0.125 p mho
• Power = 0.125 V 2 /T pW
7

• Delay = K V/ (V – V
• At 1.1 V, Delay = 625 ps th
) α
• At 1.0 V, Delay= 640 ps
▫ K = 420 ps
▫ α = 0.73
• Delay = 420 V/ (V – V th
) 0.73
Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage
Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997,
Volume 32, Issue 8
8

9
DYNAMIC POWER in adder circuit(µW)
1.1 V
1.0 V
0.9 V
0.8 V
0.7 V
0.6 V
0.5 V
0.4 V
From
Simulation
232.72
200.61
142.47
89.86
51.45
27.11
11.27
3.94
Calculated value
232.72
192.33
135.02
84.22
47.12
25.00
10.42
3.64
% decrease in power
-
13.56
38.38
60.86
77.26
87.66
94.43
97.56
250
200
150
100
50
0
0 0,2 0,4 0,6
Voltage (v) ->
0,8
Simulated Calculated
1 1,2

10
1.1 V
1.0 V
0.9 V
0.8 V
0.7 V
0.6 V
0.5 V
0.4 V
From
Simulation
625
640
727
932
1263
1775
2728
5110
Calculated value
625
640
665
706
784
955.48
1616
-
% increase in delay
-
2.4
16.32
49.12
102.11
184
336.48
717.6
6000
5000
4000
3000
2000
1000
0
0 0,2 0,4 0,6
Voltage (v) ->
0,8
Simulated Calculated
1 1,2

VDD_H VDD_L
HIGH TO
LOW
CONVERTER
VDD_L
ADDER
CIRCUIT
VDD_L VDD_H
LOW TO
HIGH
CONVERTER
11

12
1.1 V
Can turn off PMOS and can turn on NMOS
0.5V
0.5V
1.1 V
Will not turn off PMOS
V
GS
< V th for PMOS to be turned on
V thp
= -0.43 V

13

14
Level Converter for CMOS 3V to from 5V United States Patent [19] Masaki et al.
Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997

1.1 V 1.0 V 0.9 V 0.8 V 0.7 V 0.6 V 0.5 V 0.4 V
Average power (µW) 467.9
404.5
288.38
183.2
106.4
57.7
26.1
11.4
Power per converter
(nW)
58.5
52.5
48.8
47 46 45 44
Total power (µW) 467.9
406.42
290.11
184.77
107.95
59.26
27.54
12.86
%decrease in power 13.15
38.01
60.52
76.93
87.34
94.12
97.25
Adder delay (ps)
Converter delay (ps)
Total Delay (ps)
%increase in delay
Power-Delay product
(pWs)
625
-
625
-
0.29
640
75
715
11.72
0.29
727
97
824
28.75
0.23
932
125
1057
65.16
0.19
1263
172
1435
124.22
0.15
1775
260
2035
217.97
0.12
2728
658
3386
429.06
0.09
5110
3494
8604
1244.38
0.11
15
Number of gates in adder =128 Approximate increase in area = 25.78%

Power-delay product
0,15
0,1
0,05
0
0
0,35
0,3
0,25
0,2
0,2 0,4 0,6
Voltage (v) ->
0,8 1 1,2
16

• The adder circuit can be operated at 0.5V in order to minimize power
• Parameters other than power-delay product should be considered to decide on the operating voltage
17

• Evaluating performance of circuit with a few chains of gates operating at low voltages
• Lowering power by introducing low-threshold transistors in non-critical paths
18

• Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage
Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug
1997, Volume 32, Issue 8
• Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low-
Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, Volume
27, No.4, April 1992
• Masaki et al., Level Converter for CMOS 3V to from 5V, United States
Patent [19] Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997
• Kiat-Seng Yeo, Kaushik Roy, Low-Voltage, Low-Power VLSI Subsystems,
McGraw Hill
• Class lectures
19

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