Video RAMs, or VRAMs, are a variety of two-port dynamic RAM. They are designed to work well in graphics and video applications. The main port allows random access to any cell of the RAM. The other port consists of shift registers that
are controlled by an independent clock. In the HP S1010A, the random port runs in
the video input clock domain, and the serial port runs in the flat panel clock domain.
A data transfer operation loads the shift registers with data from the RAM array.
The shift registers can be treated as two semi-independent halves, so that one half
can be loaded without interfering with the data being shifted out of the other half.
This provides more flexibility, since a data transfer operation (called a split data
transfer in this case) can happen at any time while the other half is active, and
transfers can be arranged so that there will be no interruption in the data flow out
of the shift registers. The VRAM provides a signal called qsf to indicate which half
of the shift register is active. When the data in the active half of the shift register is
exhausted, qsf toggles, and the other half becomes active. This signals the HP
S1010A’s control logic that it’s time to get ready for another split data transfer.
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