" ! % $#"
Two benchmark circuits are used for objectively evaluating ASIC supplier
performance claims. The method applies first-order equations relating
capacitive discharge currents and transistor saturation current to arrive at
a technology constant. The method has been used to survey 14 ASIC
suppliers with over 76 different technologies. Results are shown for 48
CMOS technologies.
% " "& % *' +446' 0( &'5'3.+/+/) 7#-+& 1'3(03.#/%' (03 4611-+=
'34 +4 #-8#:4 1#3#.06/5 +/ 5*' .+/&4 0( &'4+)/'34 *004+/)
# 4611-+'3 $#4'& 0/ #))3'44+7' 1'3(03.#/%' %-#+.4 %06-&
-'#& 50 &+4#453064 3'46-54 / 5*' 05*'3 *#/& %*004+/) #
4611-+'3 8+5* %0/4'37#5+7' 1'3(03.#/%' %-#+.4 3'46-54 +/
*+)*'3 %0454 5*#/ /'%'44#3: $'%#64' 0( 46$015+.#- 1'3(03=
.#/%' #/& #3'# 65+-+;#5+0/
/' 8#: 50 %0.1#3' 4611-+'3 5'%*/0-0): 1'3(03.#/%'
+4 5*306)* $'/%*.#3, %+3%6+54 *' 53#&+5+0/#- 4+.1-+45+%
=+/165 NAND )#5' +/53+/4+% &'-#: 03 '7'/ (#/065 &'-#: *#4
)+7'/ 8#: 50 .03' %0.1-'5' $'/%*.#3, %+3%6+54 65 8*+%*
$'/%*.#3, %+3%6+5 %07'34 5*' 3#/)' 0( &'4+)/ 1044+$+-+5+'4
*06-& +5 4%#-' 8+5* 5'%*/0-0): 1#3#.'5'34 46%* #4 53#/4+4503
&3+7' .'5#- 8+3' -'/)5* 03 %#1#%+5#/%' "*#5 #$065 +/5'3=
%0//'%5 .'5#- 3'4+45#/%' "*#5 #3' #113013+#5' +/5'3(#%'4 50
5*' 3'#- 803-& 03 ':0/& &'4+)/ %0/4+&'3#5+0/4
8*#5 %0/&+5+0/4 8'3' 64'& 50 )'/'3#5' 1'3(03.#/%' #/&
&'-#: /6.$'34 "*#5 70-5#)' 5'.1'3#563' +/165 4-'8 5+.'
#/& 130%'44 %0/&+5+0/4 8'3' 64'& $: 5*' 4611-+'3 63
+/7'45+)#5+0/ #&&3'44'4 5*'4' +446'4
(5'3 %0/5#%5+/) 4'7'3#- &+7+4+0/4 8' '/&'& 61 64+/)
580 $'/%*.#3, %+3%6+54 5*#5 *#7' $''/ #306/& +/ 7#3+064
(03.4 4+/%' #/& 8'3' .045 3'%'/5-: 16$-+4*'& +/ "' 4637':'& 5'%*/0-0)+'4 (30. 7#3+064 4611-+'34 50
%0.1#3' $'/%*.#3, %+3%6+5 1'3(03.#/%' %-#+.4 +/%' 5*'
$'/%*.#3, 4+.6-#5+0/4 )+7' 500 .6%* -#5+56&' 50 461=
1-+'34 8' 64'& 41'%+(+% &'7+%' 5'%*/0-0): &'5#+-4 50 %0.=
1#3' #/& '7#-6#5' 5*' #%%63#%: 0( 4611-+'3 %-#+.4 "' 0$=
4'37'& $05* #))3'44+7' #/& %0/4'37#5+7' 1'3(03.#/%' %-#+.4
)+7'/ 5*' 6/&'3-:+/) 5'%*/0-0): *' 130%'44 8' &'4%3+$'
#-40 #--084 &'4+)/'34 50 (0%64 0/ #3'#4 8*'3' # 4611-+'3
*#4 46$015+.#- &'4+)/4
! " " !
*' $'/%*.#3, %+3%6+54 #3' 4*08/ +/ +) *' (+345 %+3%6+5
'/%*.#3, +) # 4*084 # %0.1-'5' 1#5* (30. +/165
1#& 50 065165 1#& *'3' +4 # 46$45#/5+#- 065165 1#& -0#& 0(
1 8*+%* .03' %-04'-: 3'13'4'/54 3'#-=803-& #11-+%#5+0/4
/ +/5'3/#- 1#5* %0/5#+/4 7#3+064 5:1+%#- -0)+% )#5'4 8+5*
(#/065 #/& 8+3' -'/)5* 41'%+(+%#5+0/4 *' 4'%0/& %+3%6+5
'/%*.#3, +) $ +/%-6&'4 580 (-+1=(-014 #/& #
6)645 '8-'55=#%,#3& 063/#-
=+/165 NOR )#5' '/%*.#3, &0'4 /05 +/%-6&' +/5'3(#%'4
50 5*' 3'#- 803-& #/& +4 3'-#5+7'-: 4+.1-' +/ %0.1#3+40/ 50
'/%*.#3, 0 # -#3)'3 '95'/5 '/%*.#3, )+7'4 #
%-04'3 (''-+/) (03 5*' +/53+/4+% 1'3(03.#/%' 0( # )+7'/ 5'%*=
/0-0): 03 $05* $'/%*.#3,4 8+3' -'/)5* #/& )#5' (#/065
%#1#%+5#/%' 4%#-' 8+5* 5'%*/0-0): 03 +/45#/%' +( .'5#1+5%*'4 $'%0.' 4.#--'3 8*'/ .07+/) 50 5*' -'#&+/)='&)'
5'%*/0-0): 8+3' -'/)5*4 4*06-& $' 4*035'3 +,'8+4' )#5'
(#/065 %#1#%+5#/%' 4*06-& 53#%, 8*'/ .07+/) 50 4.#--'3
4530/)'3 53#/4+45034 +/ # -'#&+/)='&)' 5'%*/0-0):
"' 0$5#+/'& %0.1-'5' 1#5* &'-#:4 (03 5'%*/0-0=
)+'4 (03 &+(('3'/5 4611-+'34 +/%-6&+/) +/5'3/#- #/&
1#5* 3+4+/) #/& (#--+/) &'-#:4 (03 '/%*.#3, #/& .#9+=
.6. 01'3#5+/) (3'26'/%: (03 '/%*.#3, '/'3#--: 461=
1-+'34 64'& .0&'-4 0( 5*'+3 5'%*/0-0): 50 '45+.#5' 1#5* &'=
-#:4 3#5*'3 5*#/ .'#463'.'/54 0( #%56#- %+3%6+54 *' &#5#
%0--'%5'& +4 4*08/ +/ #$-' Table I
ASIC Supplier Sample Data
3#8/ 53#/4+4503 )#5' -'/)5* µ.
(('%5+7' 53#/4+4503 )#5' -'/)5* µ.
3#/4+4503 )#5' 09+&' 5*+%,/'44 <
+5%* (03 '#%* .'5#- -#:'3 µ.
08'3 4611-: 70-5#)' 64'& (03 $'/%*.#3,4 !
6/%5+0/ 5'.1'3#563' 64'& (03 $'/%*.#3,4 °
30%'44 %0/&+5+0/ 64'& (03 $'/%*.#3,4 (SLOW/NOM/FAST)
/165 '&)' 3#5' 64'& (03 $'/%*.#3,4 /4
'/%*.#3, %0.1-'5' 1#5* 1 &'-#: /4
'/%*.#3, %0.1-'5' 1#5* 1 &'-#: /4
'/%*.#3, +/5'3/#- 1#5* 1 &'-#: /4
'/%*.#3, +/5'3/#- 1#5* 1 &'-#: /4
'/%*.#3, .#9+.6. 01'3#5+/) (3'26'/%: ;
611-+'34 8'3' 3'26+3'& 50 1307+&' '/06)* 130%'44 &'5#+-4 50
'7#-6#5' 5*' #%%63#%: 0( 1'3(03.#/%' %-#+.4 "' 8#/5'& 50
7'3+(: 1'3(03.#/%' 64+/) (+345=03&'3 (+)63'4 0( .'3+5 #/&
%0.1#3+40/4 $'58''/ 4611-+'34 0 5*#5 '/& 8' %0/4+&'3'&
130%'44 #/& &'7+%' 1#3#.'5'34 5*#5 4530/)-: #(('%5 %+3%6+5
1'3(03.#/%' /#.'-: 53#/4+4503 '(('%5+7' )#5' -'/)5* '((
transistor oxide thickness (Tox), junction temperature, power
supply voltage, and pitch for all metal layers. These parameĆ
ters are shown in Table I.
shown in Table II. Simulations were done with HP SPICE for
a circuit deck equivalent to Benchmark 2 using 0.5Ƶm
CMOS SPICE models.
We evaluate supplier performance claims by relating delay
or frequency numbers to manufacturing process specifics.
Roughly speaking, propagation delay td is proportional to
Leff, Tox, and temperature, and inversely proportional to
VDD, as shown in equation 3 below. We arrived at equation
3, a firstĆorder constant relationship, by equating the rate of
capacitive discharge current (equation 1) to transistor saturaĆ
tion current IDSAT (equation 2). Equation 1 models the caĆ
pacitive discharge of a node in terms of the power supply
voltage, current, and rate of discharge (roughly proportional
to delay). Equation 2 relates transistor saturation current to
transistor effective gate length Leff, oxide thickness Tox (inĆ
versely proportional to oxide capacitance Cox), mobility uo
(related to temperature in Kelvin), threshold voltage Vto,
transistor width Weff, and power supply voltage VDD. For
simplicity, Vto is assumed to be proportional to VDD, while
temperature is inversely proportional to uo.
Table II
Maximum Percent Error for Linear Fit of Delay as a Function of
Various Variables
I C dV
dt
I DSAT (1)
u oC oxW eff
2
(V DD V to)
2 L eff
Technology Constant (2)
t dV DD
.
L effT oxTemp
(3)
Equation 3 is not very precise, and is valid only over narrow
regions of operation. However, detailed SPICE simulations
showed that there is a surprising amount of linearity, as
shown in Fig. 2. The largest error was 6.4% for Leff variaĆ
tions from 0.4 µm to 0.9 µm. The largest percent errors are
1
4-Input
NAND
1
1
TTL Input
4 Input
NOR
0
0
U2
b
CIN
U3
U1
In
Pad
Maximum Error
Leff
Tox
Temperature
VDD
0.4 µm to 0.9 µm
57 nm to 228 nm
0°C to 135°C
2.7V to 5.7V
-6.4%
-4.0%
-1.2%
5.8%
We first charted all performance numbers for various suppliĆ
ers as shown in Fig. 3. For each supplier, Leff decreases as
we move from left to right. Suppliers are generally quite
competitive with their leadingĆedge technology, but some
suppliers' leadingĆedge technologies appear slower than
another supplier's mature technology. Some suppliers appear
to do quite well in the total path delay for Benchmark 1 but
do not perform as well in the maximum operating frequency
for Benchmark 2.
We applied equation 3 to all delay and frequency numbers,
computing a value for each supplier's
technology performance claim. However, since the
technology constant is only a constant under an idealized
firstĆorder approximation, we looked for patterns and trends.
We computed the mean and standard deviation for all
suppliers across all technologies for each Benchmark 1 and
2 constant. After plotting technology constants for each
benchmark for all suppliers and their technologies, we
placed guardbands one standard deviation from the mean as
shown in Fig. 4. Technology constants falling above the
upper guardband were labeled conservative and technology
constants falling below the lower guardband were labeled
COUT
a
U4
0
Range
4-Input
MUX
1-Bit
Adder
Fanout=2
Variable
Fanout=3
0
0
0
XOR
0
1
2
3
U5
y
S0
S1
0
0
0
U6
TTL
Output
Out
U7
Pad
50-pF
Load
(a)
A
B
Zn
D
D
Q
CLK
–Q
CLR
Q
CLK
–Q
CLR
CLK
CLR
(b)
(a) Benchmark 1 includes a complete path of internal and I/O delays. (b) Benchmark 2 includes D flipĆflops with reset.
August 1995 HewlettĆPackard Journal
2.4
1.2
2
Delay (ns)
Delay (ns)
1
1.6
1.2
0.8
0.8
0.4
0.35
0.55
0.75
Leff (m)
(a)
0.6
0.35
0.95
90
120
150
Tox (nm)
(b)
180
210
240
1.6
0.85
0.8
1.4
1/Delay (1/ns)
Delay (ns)
60
0.75
0.7
1.2
1
0.65
0.6
0.8
0
35
70
Temperature (C)
105
140
(c)
2
3
4
VDD (volts)
(d)
5
6
0,/4 /' %&,"9 "3 " '5.$4*/. /' " &'' # /8 $ 4&-0&2"452& ".% % !
/04*-*34*$ 4 3)/5,% #& ./4&% 4)"4 4&$)./,/(9 $/.34".4
6",5&3 "2& %*''&2&.4 '/2 %*''&2&.4 #&.$)-"2+3 /2 0/24*/.3 /' "
#&.$)-"2+
2/- ". &8"-*."4*/. /' *( 3/-& 42&.%3 ".% 0"44&2.3
&-&2(& /2 *.34".$& -".9 3500,*&23 4&.% 4/ #& -/2& $/.;
3&26"4*6& '/2 4)&*2 ,&"%*.(;&%(& 4&$)./,/(9 )*3 -*()4 2&;
35,4 '2/- *.)&2&.4 4&.%&.$*&3 4/ #& -/2& $/.3&26"4*6& 4
$/5,% ",3/ #& 4)"4 42".3*34/2 0&2'/2-".$& "3 -&"352&%
4)2/5() &,&$42/. 6&,/$*49 3"452"4*/. 7*,, 4&.% 4/ ,&6&, /'' '/2
3-",,&2 &''
/-& 3500,*&23 $,&"2,9 $,"*-&% 0&2'/2-".$& 4)"4 *3 3*-0,9
5."44"*."#,& (*6&. 4)&*2 4&$)./,/(9 %&3$2*04*/. "3 3&&. *.
*( 3 7& *.6&34*("4&% '524)&2 7& '/5.% /54 7)9 4)&9
"00&"2&% $/.3&26"4*6& /2 /04*-*34*$ /2 *.34".$& 3500,*&2
53&% " ;*.054 NAND ("4& *.34&"% /' " ;*.054 NAND ("4&
$,"*-*.( 4)"4 4)&9 7&2& /04*-*:*.( 4)& $2*4*$", 0"4) 53*.( "
;*.054 NAND ("4& '/2 4)& $2*4*$", 0"4) ".% " ;*.054 AND ("4&
'/2 4)& 2&34 /' 4)& ./.$2*4*$", 0"4) 500,*&2 53&% )",' 4)&
490*$", 5.*4 7*2& $"0"$*4".$& $/.34".4 '/2 $/-054*.( *.4&2.",
.&4 $"0"$*4".$&3 'µ- *.34&"% /' 'µ- . 4)&
/4)&2 &842&-& 3500,*&2 7)*,& )"6*.( $/-0&4*4*6& 0&2'/2;
-".$& $,&"2,9 7"3 $"0"#,& /' %/*.( 35#34".4*",,9 #&44&2
'4&2 %&4"*,&% $/.6&23"4*/.3 *4 #&$"-& "00"2&.4 4)"4 4)&*2
4&$)./,/(9 *3 *--"452& ".% 0//2,9 %&'*.&% 7*4) )*() .&4
24
800
Delay (ns)
20
*
16
*
12
*
*
+
*
+
+
8
+
+
+
+
+
*
+
+
+
+
4
Maximum Frequency (MHz)
*
*
+
600
+
+
+
+
+ +
+
+
+
+
400
+
*
200
*
*
*
* *
0
0
A
B C D
E
F G
H
I
J K
L
A
M
B C D
E
F G
Supplier
Internal Delay
I/O Delay
* Rechar 3V
(a)
H
I
J K
L
M
Supplier
Odd 4V + True 3V
* Rechar 3V
Odd 4V
+ True 3V
(b)
Fig. 3. /4", 0"4) %&,"9 *.$,5%*.( " &.$)-"2+ *.4&2.", 0,53 %&,"9 ".% # &.$)-"2+ -"8*-5- '2&15&.$9 '/2 6"2*/53 4&$)./,/;
(*&3 ".% 3500,*&23 /2 &"$) 3500,*&2 &'' %&$2&"3&3 '2/- ,&'4 4/ 2*()4 '/2 4)&*2 2&30&$4*6& 4&$)./,/(9 /''&2*.(3 /-& 4&$)./,/(*&3 "2&
3*-0,9 2&$)"2"$4&2*:"4*/.3 '2/- ! 4/ ! 7)*,& /4)&23 "2& 425& ! 5(534 &7,&44;"$+"2% /52.",
2
Conservative
+
*
2
+
+
* +
+
*
*
*
1
+
+
+
+
++
* *
Optimistic
Technology Constant
(Thousandths)
Technology Constant
(Thousandths)
3
0
Conservative
1.5
+
*
1
+
+
*
0.5
+
+
++
+
* *
+
Optimistic
B C D
E
F G
H
I
J K
L
M
A
B C D
E
F G
Supplier
(a)
* Rechar 3V
Odd 4V
+ True 3V
(b)
+
* +
1
+
0.5
* *+
+
+
+
*
*
* *
*+
+
+
+
+
Optimistic
Technology Constant
(Millionths)
Conservative
1.5
0
A
B C D
E
F G
H
I
J K
L
* Rechar 3V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
J K
L
M
Odd 4V
+ True 3V
+
+
+
+
*
* + +
*
* * *
* +
+
++
++
Optimistic
A
M
Odd 4V
Conservative
B C D
E
F G
Supplier
* Rechar 3V
H
Supplier
2
Technology Constant
(Thousandths)
+
*
*
0
A
(c)
+
*
+
H
I
J K
L
M
Supplier
+ True 3V
(d)
* Rechar 3V
Odd 4V
+ True 3V
Optimistic versus conservative technology constants for (a) Benchmark 1 total path delay, (b) Benchmark 1 I/O path delay, (c)
Benchmark 1 internal path delay, and (d) Benchmark 2 maximum frequency for various technologies and suppliers. For each supplier,
Leff decreases from left to right for their respective technology offerings. Some technologies are simply recharacterizations from 5V to 3V
(*) while others are true 3V (+).
capacitances computed based on previous technology offerĆ
ings and less than compact layout. Comparisons through the
technology constant method also allow us to determine if
suppliers have potentially optimized I/O or internal cells as
seen in Figs. 4b, 4c, and 4d, respectively.
Table III compares supplier K to another with very similar
gate array technology, supplier H. Both suppliers offer gate
array products. Supplier K used a wire capacitance constant
of 0.1 fF/µm, which explains partly why they claimed higher
performance. In fact, supplier K has larger metal pitches
than supplier H, which should result in substantially longer
net wire lengths after place and route, further increasing net
wire capacitances and decreasing overall performance. Both
suppliers use Cadence's Gate Ensemble for layout, so it is
unlikely there would be substantial wire length differences
even if they had the same metal pitches. As stated preĆ
viously, supplier K was found to have overly optimistic perĆ
formance claims. Comparisons through the technology conĆ
stant method allowed us to home in quickly on the reasons
why, chief among them being the unrealistically low wire
capacitance constant of 0.1 fF/µm.
For the sake of expediting the process of ASIC technology
benchmarking, we used a simplified approach that we can
improve upon for future supplier analysis. Our detailed
questions did not ask for wire unit capacitance; one supplier
used wire capacitance values half those given by convenĆ
tional wire capacitance statistical modeling. Neither did we
include wire unit resistance effects. However, the benchĆ
marks have relatively short wire lengths so it is unlikely that
RC delays contribute significantly to total delay. In the fuĆ
ture, we can specify gate array and standard cell height as
Table III
Comparison of Supplier Technologies
Supplier
Effective transistor gate
length(µm)
Transistor gate oxide thickness
(Å)
Pitch for each metal layer (µm)
Power supply used for
benchmarks (V)
Junction temperature used for
benchmarks (°C)
Process condition used for
benchmarks (SLOW/NOM/FAST)
Input edge rate used for
benchmarks (ns)
Benchmark 1 complete path
TpLH delay (ns)
Benchmark 1 complete path
TpHL delay (ns)
Benchmark 1 internal path
TpLH delay (ns)
Benchmark 1 internal path
TpHL delay (ns)
Benchmark 2 maximum
operating frequency (MHz)
H
0.7
K
0.7
150
150
2.0,2.8,2.8
4.5
3.2,3.2,3.2
4.75
85
85
SLOW
SLOW
1
1
14.4
8.04
12.2
8.72
7.3
4.8
7.1
4.4
317
460
August 1995 HewlettĆPackard Journal
the unit of length. We can also include the effects of transisĆ
tor mobility, in particular threshold drops (Vto), which beĆ
come important as we scale down to lower power supply
voltage levels.
We also should specify more precise input signal edge rates,
power supply voltage, and junction temperature, such as
1Ćns 10ĆtoĆ90% rise and fall times, 10% off nominal power
supply (4.5V for 5V or 3.0V for 3.3V), and 85°C junction
temperature. The benchmarks left these numbers to the
discretion of each supplier. Sometimes junction temperatures
varied from 70°C to 125°C while power supply voltage varĆ
ied from 5% to 20% off nominal. In the near future, we want
to get supplier electrical and SPICE models, and ultimately
verify performance through actual silicon.
Equation 3 is only a firstĆorder approximation. Curve fit analĆ
ysis shows the best fit for the SPICE simulation data is not
necessarily always linear. Equation 3 might be better evaluĆ
ated as equation 4 below for some situations:
Technology Constant
[
t dlnǒV DDǓ
ǒLeffǓ
1.25
eTox
Temp
(4)
We are also currently evaluating other issues such as optimal
metal pitch as a function of transistor Leff, and library richĆ
ness. Although having smaller metal pitches is advantageous
in terms of routability and increased interconnection, there is
a balance between transistor onĆresistance and metal wire
resistance, and between routing density and process cost
and manufacturability. If wire pitch is too fine, wire resisĆ
tance will dominate over transistor output drive. FurtherĆ
more, finer metal pitches increase process cost and reduce
yield as well as longĆterm reliability.
Library richness is another area considered critical by many
designers. In particular, designers want a rich and complete
set of library functions to allow maximum flexibility in imĆ
plementing chip designs. The library must be wellĆmodeled
and compatible with various CAD tools, especially mainĆ
stream synthesis and simulation tools. This includes optimizĆ
ing cell drives and functionality for synthesis.
In the future, we need to review synthesis and simulation
libraries for a number of ASIC technologies using small to
mediumĆsize benchmarks. Critical path timing and gate
count should be evaluated after synthesis. We need to have
commonly agreedĆto benchmarks to evaluate and compare
all major ASIC supplier libraries. These benchmarks should
cover areas such as scan insertion, error correction and
detection, RAM models, and others in addition to critical
path timing and area optimization. The benchmarks should
not include HP proprietary information so they can be freely
used with external suppliers. This allows suppliers to run
evaluations using their resources. HP divisions would simply
have to corroborate ASIC supplier results. The benchmarks
should be available in both VHDL and Verilog hardware
description languages since both are being used within the
HP community.
August 1995 HewlettĆPackard Journal
Part of the survey asked for detailed power dissipation for
various portions of Benchmark 1 and Benchmark 2. Often,
simulated power dissipation numbers were significantly out
of line with common sense analysis, giving us an indication
of the limitations of power estimation CAD tools for some
suppliers. We are investigating the area of power estimation
as it relates to mainstream CAD tools and supplier
methodologies.
We have developed a simple, firstĆorder method for quickly
determining the degree of optimism or conservatism of ASIC
technology performance claims from various suppliers. We
found suppliers that are not capable of delivering perforĆ
mance as promised because of circuit tricks played with the
benchmark or tooĆaggressive wire capacitances (0.1 fF/µm
instead of 0.2 fF/µm). We also found suppliers that may have
immature, poorly defined technology and design libraries.
Our method helps designers choose appropriately characterĆ
ized ASIC technology while avoiding the disastrous conseĆ
quences of choosing an ASIC supplier not capable of delivĆ
ering the promised performance. On the other hand, it
points out inefficient or immature suppliers that may be inĆ
curring extra costs because of suboptimal utilization of cirĆ
cuit performance and area. The technology constant method
also allows us to identify suppliers with potentially superior
or optimized I/O or internal design libraries.
The method is adaptable to any number of circuit benchĆ
marks and ASIC suppliers. However, it is only a first step in
the process of evaluating ASIC technologies. There are many
other factors that should be considered when selecting ASIC
technologies.
The authors would like to thank Hyoung Jo Youn for conĆ
tributing his CMOS26 and CMOS14 SPICE decks. Also,
thanks to Robin Purohit and Noori Din for discussions and
enlightenment on the issues of library evaluation through
synthesis. Our heartfelt gratitude goes to Sharon Fingold,
wife of one of the team members, whose keen eye and clear
mind kept our ideas and writing focused. Finally, we would
like to mention the names of many other dedicated and
creative people who contributed directly or indirectly
through their discussions and otherwise, including but not
limited to: Fritz Stafford, Harold Noyes, Theresa Prenn
(Tideswell), Greg Marten, Bruce Schober, Rob Mankin, Scott
Trosper, Gulu Advani, Atul Goel, John Jacobi, Donovan
Nickel, Steve Chalmers, Margie Evashenk, Mike Stewart,
Dave Fotland, Dave Goldberg, Bob Schuchard, Todd
Spencer, Jon Riesberg, David Stewart, Paul Dembiczak, DaĆ
vid Bond, Jeff Dawkins, Oren Rubinstein, and Alex WarĆ
shawsky.
1. L. Vereen and M. Jain, Benchmarks Define ASIC Performance,"
, September 1993.