International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Power Analysis of Different Full Adders with
Different CMOS Logic Design
Palleti Pavan Kumar Reddy 1, k.v satyanarayana 2,
1
M.tech Student, Specialization VLSI,
M.tech, Associate professor Of Department Of E.C.E.
1,2,
Department Of E.C.E, sir c.v raman Institute of Technology And Sciences, tadipatri-515411, Andhra Pradesh, India.
2
Abstract— Multipliers are used in a wide range of devices, from
large scale processors to small embedded DSP chips. As
multipliers are large, slow and complex components, a lot of
research has been done to make the components smaller and
faster. As more of the electronic devices become embedded or
handheld, they become more dependent on battery as a power
source. To improve battery life-time, the research focus has
shifted to improve power consumption. By reducing powerusage, it is possible to drastically improve the battery-life of
handheld devices. Since tree multipliers, like Wallace and Dadda,
are faster and use less power than traditional array multipliers
(though have larger area), this thesis concentrates its focus on
tree multipliers. The Wallace algorithm is the oldest of the
algorithms presented here. It reduces the input matrix by
grouping the rows together, and performs reductions on each
group. Rows that are not part of any group are just transferred
to the next stage of the algorithm. Our main aim is designing of
full adder and reducing the leakage by using the T-Spice
simulation. This paper we proposed to reduce the leakage in
different full adder techniques.
Keywords— Wallace, Full Adder, Leakage, T-Spice, Low Power.
the essential multiplication principle is 2 folds i.e.,
analysis of partial product and accumulation of the shifted
partial product. it's performed by the ordered additions of the
columns of the shifted partial product matrix. The ‘multiplier’
is with success shifted and gets the acceptable little bit of the
‘multiplicand’. The delayed, instance of the number should all
be within the same column of the shifted partial product
matrix. they're then extra kind|to make|to create} the
merchandise bit for the actual form. Multiplication is thus a
multi quantity operation.
Multiplication methods:
Multiplication (often denoted by the cross symbol "×", or by
the absence of symbol) is the third basic mathematical
operation of arithmetic, the others being addition, subtraction
and division (the division is the fourth one, because it requires
multiplication to be defined).
II. DESIGN TECHNOLOGIES
There are many sorts of techniques that intend to solve the
I. INTRODUCTION
problems mentioned above.
The various multiplier factor architectures are printed
within the literature, throughout the past few decades. The
Full Adder Design:
multiplier factor is one amongst the key hardware blocks in
So = H′Ci + HC′o (1)
most of the digital and high performance systems like digital
signal processors and microprocessors. With the recent Co = HCi + H′A (2)
advances in technology, several researchers have worked on Where H = A Xor B and H′ = A Xnor B.
the look of progressively} more economical multipliers [1].
A Full Adder is made up of an XOR–XNOR module, a sum
They aim at giving higher speed and lower power
module and a carry module. The XOR–XNOR module
consumption even whereas occupying reduced chemical
performs XOR and XNOR logic operations on inputs A and
element space. This makes them compatible for varied
advanced and transportable VLSI circuit implementations. B, and then generates the outputs H and H′. Subsequently, H
and H′ both are applied to the sum and the carry modules for
However, the actual fact remains that square measurea| the
world|the realm} and speed are 2 conflicting performance generation of sum output So and carry output Co.
constraints. Hence, innovating inflated speed continuously
leads to larger space. during this paper, we have a tendency to A. Transmission gate CMOS (TG)
reach a much better trade-off between the 2, by realizing a
It uses transmission gate logic to realize complex logic
touch inflated speed performance through atiny low rise
functions using a small number of complementary transistors.
within the range of transistors [2]. The new design enhances
It solves the problem of low logic level swing by using pMOS
the speed performance of the wide acknowledged Wallace tree
as well as nMOS.
multiplier factor. The structural optimisation is performed on
the standard Wallace multiplier factor, in such the way that
the latency of the whole circuit reduces significantly.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Figure: 3 GDI XNOR Full Adder Circuit
D.
Figure: 1 Transmission Gate Full Adder
B. Zhuang Full Adder
Zhuang full adder (ZFA) is also made by transmission
gate. In this design uses transmission gate to form a
multiplexer and XORs. Figure 2 shows the transistor-level
schematic using 22 transistors. The design can be understood
by parsing the transmission gate structure in to multiplexer
and an “invertible inverter”.
SR-CPL Full Adder Design
A SR-CPL is designed using a combination of pass
transistor logic (PTL) and static CMOS design techniques to
provide high energy efficiency and improve driving
capability. An energy efficient CMOS FA is implemented
using swing restored complementary pass-transistor logic
(SR-CPL) and PTL techniques to optimize its PDP.
Figure: 4 SR-CPL Full Adder Design
E. Simulation Analysis
Full Adder was designed with different logic using
Tanner Tools and simulated as shown below:
Figure: 2 Zhuang Full Adder
C.
Gated Diffusion Index
The GDI method is based on the use of a simple cell. At
first glance, the basic cell reminds one of the standard CMOS
inverter, but there are some important differences.
1) The GDI cell contains three inputs: G (common gate
input of nMOS and pMOS), P (input to the source/drain of
pMOS), and N (input to the source/drain of nMOS).
2) Bulks of both nMOS and pMOS are connected to N or P
(respectively), so it can be arbitrarily biased at contrast with a
CMOS inverter.
Figure: 5 Transmission Gate Full Adder Design
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
Figure: 6 Transmission Gate Full Adder simulation
Figure: 7 Zhuang Full Adder Design
Figure: 10 GDI Full Adder Simulation
Figure: 8 Zhuang Full Adder simulation
ISSN: 2231-5381
Figure: 9 GDI Full Adder Design
Figure: 11 SR-CPL Full Adder Design
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International Journal of Engineering Trends and Technology (IJETT) – Volume 16 Number 3 – Oct 2014
[4]C. Jaya Kumar, R. Saravanan, “VLSI Design for Low Power Multiplier
using Full Adder”, European Journal of Scientific Research, ISSN 1450216XVol.72 No.1 (2012), pp. 5-16
[5]Ravi Nirlakalla, Thota Subba Rao, Talari Jayachandra Prasad,
“Performance Evaluation of High Speed Compressors for High Speed
Multipliers”, Serbian Journal of Electrical Engineering, Vol. 8, No. 3,
November 2011, 293-306
[6] C. H. Chang, J. Gu, M. Zhang, “A review of 0.18µm full adder
performances for tree structured arithmetic circuits”, IEEE Transactions Very
Large Scale Integration System., Vol. 13, No. 6, June 2005, pp. 686 - 695.
[7] E. Abu-Sharma, M.B. Mazz, M.A Bayoumi, “A Fast and Low Power
Multiplier Architecture”, Circuits and Systems, IEEE 39th Midwest
symposium,18-21 August, 1996, Vol. 1, pp. 53-56.
[8] Dan Wang, Maofeng Yang, Wu C heng, Xuguang Guan, Zhangming
Zhu, Yintang Yang," Novel Low Power
Full Adder
Cells in
180nm CMOS Technology”, National Natural Science Foundation of
China, 2009 IEEE, pp. 430 -433.
Figure:12 SR-CPL Full Adder Simulation
TABLE I
The above four circuits of full adder
Tanner Tools using TSMC025 and its
individual circuits are tabulated.
Circuit
Power Dissipation
Transmission
8.378055e-008W
Gate
Zhuang Full 5.642831e-008W
Adder
GDI
Full 7.169277e-005W
Adder
SR-CPL Full 1.619856e-009W
Adder
are simulated using
delay and power of
Delay
6.0857e-012Sec
2.3267e-010sec
1.6816e-010
8.1078e-012sec
III. CONCLUSION
As the core of an arithmetic circuit, that is a key module in a
large number of portable electronic systems, a High Speed
Full Adders presented in this Letter as a way to simplify the
circuit architecture and hence improve the performance. For
performance validation, Tanner simulations were conducted
on FAs implemented with TSMC 0.18µm CMOS process
technology in aspects of power consumption, delay time In
contrast to other types of FAs with drivability, a SR-CPL-FA
is superior to the other ones and can be applied to design
related adder-based portable electronic products in practical
applications in today’s competitive markets.
REFERNCES
[1] Neil H. E. Weste & David Harris, “CMOS VLSI Design- A circuit and
Systems Perspective”, 4th edition, Addison Wesley, 2010
[2] C. N.Marimuthu, Dr. P. Thangaraj, Aswathy Ramesan, "
shift and add multiplier design", International Journal of
Science and Information Technology, June 2010, Vol. 2,
Number
[3]Marc Hunger, Daniel Marienfeld, “New Self-Checking Booth Multipliers”,
International Journal of Applied Mathematics Computer Sci., 2008, Vol. 18,
No. 3, 319–328
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