International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
M.Tech Student, Jr.Associate Professor,Professor and Head of DepartmentECE,Integral University Lucknow
Integral Univesity , Dasauli ,Kursi Road , Lucknow-226026,India
Abstract
The word ‘Vedic’ is extracted from the word ‘Veda’ i.e. the store-house of all knowledge. Mathematics, derived from the Veda provides one line, super fast and mental methods along with quick cross checking systems. The Vedic mathematics was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). What we call VEDIC MATHEMATICS is a mathematical elaboration of 'Sixteen Simple Mathematical formulae from the Vedas' as brought out by Sri Bharati Krishna
Tirthaji. Vedic Multiplication Technique will be used to implement Floating point multiplier. For mantissa multiplication
I am using Urdhva-Tiryagbhyam sutra. The underflow and over flow cases will be handled. The inputs to the multiplier in 32 bit
IEEE 754 format. In this paper, I proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. For mantissa multiplication I am using Urdhva-triyakbhyam sutra for the underflow and over flow cases are handled. The multiplier’s inputs are provided in IEEE 754, 32 bit format. The Vedic
Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. My work has proved the efficiency of Urdhva-Tiryagbhyam, Vedic method for multiplication which strikes a difference in the actual process of multiplication. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. The Urdhva-
Tiryagbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. I implement this multiplier using VHDL. I implement my work by Xilinx ISE tool i.e. responsible for synthesis also. For simulation I am using Modelsim 10.2a.
Keywords: Vedic Mathematics, VHDL, Urdhva-Tiryagbhyam
Sutra . areas. A whole spectrum of multipliers with different areaspeed constraints has been designed with fully serial multipliers at one end of the spectrum and fully parallel
Multipliers at the other end. Multipliers have moderate performance in both speed and area. Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. The IEEE 754 standard provides the format for representation of Binary
Floating point numbers in computers. The Binary Floating point numbers are represented in Single and Double formats.
The Single precision format consists of 32 bits and the Double precision format consists of 64 bits. The formats are composed of 3 fields; Sign, Exponent and Mantissa. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Reducing the time delay and power consumption are very essential requirements for many applications [1, 2]. This paper presents different multiplier architectures. Multiplier based on Vedic
Mathematics is one of the fast and low power multiplier.
Digital multipliers are the core components of all the digital signal processors (DSPs) and the speed of the DSP is largely determined by the speed of its multipliers [3]. Fig1. shows
IEEE Format for single and double.
1BIT 8BIT 23BIT
SIGN EXPONENT MANTISSA
MSB LSB MSB LSB
1BIT 11BIT 52BIT
SIGN EXPONENT MANTISSA
I.
I NTRODUCTION
Multipliers are key components of many high performance systems such as microprocessors, FIR filters, digital signal processors, etc. Performance of a system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system.
Since multiplication dominates the execution time of most
DSP application so there is need of high speed multiplier.
Furthermore, it is generally the most area consuming. Hence, optimizing the area and speed of the multiplier is a major design issue. However, speed and area are usually conflicting constraints so that improving speed results mostly in larger
2
MSB LSB MSB LSB
Fig 1: IEEE Format for single and double
Vedic Mathematics:
Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya- Veda (book on civil engineering and architecture), which is an upa-veda (supplement) of Atharva
Veda. It gives explanation of several mathematical terms including arithmetic, geometry (plane, co-ordinate),
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014 trigonometry, quadratic equations, factorization and even calculus.
3. Urdhva-Tiryagbhyam Sutra:
“Urdhva” and “Tiryagbhyam” words are derived from
Sanskrit literature. Urdhva means “Vertically” and
Tiryagbhyam means “crosswise”. It is based on a novel concept, where the generation of all partial products can be done with the concurrent addition of partial products. Anyone can easily realize that this Vedic method probably makes difference for mental calculations [5, 6].
4. Floating Point Multiplication:
The multiplier for the floating point numbers represented in
IEEE 754 format can be divided in four different units:-
Mantissa Calculation Unit
Exponent Calculation Unit
Sign Calculation Unit
Control Unit
The standard format for representation of floating point number is
( −1) S 2E (b0 · b1b2 … bp−1).
Let us Consider the multiplication of two floating point numbers A and B, where A = -19.0 and B = 9.5. The normalized binary representation are A = -1.0011x24 and B =
1.0011x23. IEEE representations of operands are
Sign Exponent Mantissa
A = 1 10000011 00110000000000000000000
B = 0 10000010 00110000000000000000000
5. Work:
The performance of Mantissa calculation Unit dominates whole performance of the Floating Point Multiplier. This unit requires unsigned multiplier for multiplication of 24x24 BITs.
The Vedic Multiplication technique is chosen for the implementation of this unit. This technique gives promising result in terms of speed and power [4]. The Vedic multiplication system is based on 16 Vedic sutras or aphorisms, which describes natural ways of solving whole range of mathematical problems. Out of these 16 Vedic Sutras the Urdhva-Tiryagbhyam sutra is suitable for this purpose. In this method the partial products are generated simultaneously which itself reduces delay and makes this method fast.
a2 a1 a0 a2 a1 a0 a2 a1 a0
b2 b1 b0 b2 b1 b0 b2 b1 b0
6. Simulation Results:
I have taken two inputs ‘A’ and ‘B’ as a multiplier and multiplicand these are floating point signed value I perform multiplier using Vedic Algorithm between these inputs and will be stored in other output port which I have taken as ‘Z’ all operations are performing on positive edge of clock.
For case I, I have taken value of ‘A’ is 134.0625 and value of
‘B’ is -2.25. Here ‘A’ is unsigned floating pint number and
‘B’ is Signed Floating Point Number. Now I have to convert value of ‘A’ to binary format after normalize I get
1.00001100001x2^7 then I have to convert it into IEEE-32 floating point format then I get 0 10000110
00001100001000000000000 then convert it into hexadecimal format I will get 0x43061000. Now I have to convert value of
‘B’ to binary format after normalize I get -1.001x2^1 then I have to convert it into IEEE-32 floating point format then I get 1 10000000 00100000000000000000000 then convert it into hexadecimal format I get 0xC0100000. After multiplication using Vedic Multiplier I get 0xC396D200 the value of this hexadecimal no. is -301.640625 fig 3. Shows the simulation result of this data.
a2 a1 a0 a2 a1 a0
.
b2 b1 b0 b2 b1 b0
Fig 3: Simulation Result of Case1
7. Synthesis Results:
Fig 4. Shows the RTL of my code, fig 5. Shows the internal
RTL and fig 6. Shows the devices utilization in my paper.
Fig 2: The Vedic Multiplication method
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014
Fig 4: Main RTL
Fig 5: Internal RTL
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 3 - May 2014 floating point number multipliers are much faster than the conventional multipliers. This gives us method for hierarchical floating point multiplier design. So the design complexity gets reduced for inputs of large number of bits and modularity gets increased. Urdhva-Tiryagbhyam sutra algorithm is been used which can reduce the delay and hardware requirements for multiplication of Floating point numbers. FPGA based simulation and Synthesis of this floating point multiplier shows that hardware realization of the
Vedic mathematics algorithms is easily possible. The high speed multiplier algorithm exhibits improved efficiency in terms of speed.
Fig 6: Device utilization
8. Conclusion:
The Floating Point numbers are the basic necessity in the current scenario of digital design based systems. Hence we implemented, the design of Floating point number in IEEE32 bit format, on Spartan 3E- XC3S250-5-CP132. The design is based on Vedic method of multiplication. The worst case propagation delay in the Optimized Vedic floating point multiplier case is 4.788 ns. It is therefore seen that the Vedic
ACKNOWLEDGEMENT
First of all I am grateful to God, The most beneficent and merciful who provides me confidence and determination in accomplishing this work. I wish to express my deep sense of gratitude and profound thanks to Mr. Shailendra Kumar (Jr.Associate
Professor), Integral University, Lucknow for providing me the opportunity to work on this topic under his guidance. The encouragement and support he provided throughout, despite his busy schedule, was invaluable and truly acknowledgeable. His feedback, constructive criticism and encouragement were the driving force behind the successful completion of this dissertation. I would also like to offer my thanks to Head of The Department Prof (Dr.)
S.H. Saeed, Department of ECE, Integral University for their throughout guidance and support whenever required. I would also grateful to the author and scholars whose work I have referred as a guiding stone in my dissertation. Finally I would like to express my sincere Gratitude to my friends, seniors, parents, family and well wishers for extending help to carry out the dissertation work.
References
[1] Booth, A.D., “A signed binary multiplication technique,”
Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, pt. 2, pp. 236– 240, 1951.
[2] Jagadguru Swami Sri Bharath, Krsna Tirathji, “Vedic Mathematics or Sixteen Simple Sutras From The Vedas”, Motilal Banarsidas,
Varanasi (India),1986.
[3] Shripad Kulkarni, “Discrete Fourier Transform (DFT) by using
Vedic Mathematics”Papers on implementation of DSP algorithms/VLSI structures using Vedic Mathematics, 2006, www.edaindia.com, IC Design portal.
[4] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic,
2008.
[5] Tariquzzaman et al,“ FPGA implementation of 64 bit RISC processor with Vedic multiplier using VHDL” IOSR Journal of
Electrical and Electronics Engineering (IOSR-JEEE) e-ISSN:
2278-1676, p-ISSN: 2320-3331 PP 12-16.
[6] BHAGYASHREE HARDIYA et al “IMPLEMENTATION OF
FLOATING POINT MULTIPLIER USING VHDL” Technology and Engineering (BEST: IJMITE) Vol. 1, Issue 3, Dec 2013, 199-
204 © BEST Journals.
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