Integrated Low Power Potentiostat circuit using Nano Electrodes Rollakanti Raju

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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 1 - May 2014

Integrated Low Power Potentiostat circuit using Nano Electrodes

Rollakanti Raju

1

, M.Vishwanath

2

, Chandra Shekar

3 ,

M.Gopala Krishna

4

1 Associate Professor, Electronics & Communication Engineering, MLRITM, HyderabadTelangana, India 2,3 Assistant Professor, Electronics & Communication Engineering, MLRITM, Hyderabad, Telangana, India 4 Assistant Professor, Electronics & Communication Engineering, MIC College of Technology,Vijayawada, AP, India Abstract

An electrochemical microanalysis system for reversible redox species determination has been presented. This system consists of a nanoelectrochemical sensor and a complimentary metal–oxide– semiconductor (CMOS) chip for sensor signal interfacing and conditioning. The nanoelectrochemical sensor is an interdigitated array nanoelectrode fabricated using e-beam lithography and ultraviolet lithography. The CMOS chip is designed and fabricated to realize the electrochemical analysis method of sensing, which is a switch-based method. Using this switch-based method, the potential dynamics of the nanoelectrodes is recorded to evaluate the species concentration. Experimental results have shown that the detection limit of this microanalysis system on reversible redox species is in the range of 1–10 nM..

Keywords

electrodes

.

Low power, Potentiostat, circuit, integrated, nano,

property of the IDA electrodes but greatly simplifies the instrumentation circuit design. In the succeeding sections of this paper, the overall analysis system and its two main functional units will be explained in detail. In addition, electrochemical measurements using this system will be presented in the experimental results section, and the system’s application potential will be discussed in the conclusion.

I.

I NTRODUCTION

This paper describes a CMOS integrated potentiostatic control circuit. The design maintains a constant bias potential between the reference and working electrodes for an amperometric chemical sensor. A technique of converting input currents into time for amperometric measurements is proposed. Redox currents ranging from 1pA to 200nA can be measured with a maximum non-linearity of ±

0

.

1%

over this range. The design can be used to generate a cyclic voltammogram for an electrochemical reaction by sweeping the voltages across the range specified by the user. Analog inputs are processed and digital outputs are generated without requiring a power-hungry A/D converter. A prototype chip has been fabricated in the

0

.

5

μm AMI CMOS process. Experimental results are reported showing the performance of the circuit as a chemical sensor. we present a new potentiostat topology employing a resistive T-network to increase gain anda novel input stage to guarantee ultra low-input impedance over high dynamic gain as both stages are uncoupled.

The CMOS circuit is designed to apply electrical excitation to IDA nanoelectrodes, sample electrochemical reaction signal from the sensor, convert the sampled analog signal to a digital number, and then communicate with a computer (with the LabView software installed). Instead of directly measuring the limiting reaction current, the CMOS circuit adopts a switch-based electrochemical analysis method to indirectly acquire the limiting reaction current to know the species concentration. This switchbased analysis method still keeps the redox-cycling

Figure 1:Schematic view of the proposed potentiostat showing low-input

II.

P OTENTIOSTAT C IRCUIT

The gain and the input impedance of the conventional TIA are given by and , respectively. The larger resistance of the TIA increases the gain at the expense of higher input impedance. Also, for CV measurement, it is typically required to control the bias at the WE and consequently the potential applied between WE–RE. This will affect the input common mode and the output common mode of the TIA. Such a change will affect the gain and signal swing of the circuit. This degrades dynamic range of the potentiostat. Fig. 1 shows the proposed input stage consisting of a Wilson current mirror structure (M1–M4) serving as a current buffer with an additional operational amplifier (OTA) in feedback around

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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 1 - May 2014

M1. The Wilson current mirror feedback loop guarantees that all input current goes into drain of M2, allowing for a bidirectional measurement. By using OTA in negative feedback around M1, it will force the inputs of the OTA to track each other; we can therefore apply and control voltages at WE node. It allows us to sweep the potential between WE and RE (typically a triangular waveform as seen in Fig. 1) for CV measurement without scarifying dynamic range. The input impedance (Z in ) of the input stages is given by 200nA can be detected with maximum error of

±

0

.

1% due to nonlinearity. Minimum current detected using the design with PMOS transistor at the input was 300fA. where A Wilson is the feedback loop gain of the Wilson current mirror and A 1 is the gain of the OTA around M1. As seen in (1), the input stage can be independently set for low input impedance by controlling A 1 . Also, the TIA gain can now be increased (higher effective transresistance) without affecting the input impedance. For the gain stage, we propose the TIA with resistive T network as seen in Fig. 1. The gain is given by According to (2), when R1 and R3 are much greater than R2, the TIA can achieve high gain using only small resistors while maintaining the bandwidth of the TIA. III.

E XPERIMENTAL R ESULTS

The prototype chip was fabricated through MOSIS in the AMI 0

.

5

μm

CMOS process. For testing flexibility, offchip components were used for reference currents and noncritical digital circuits. Figure 2 shows the comparison of the time taken to charge the capacitor calculated analytically using equation 1 and the actual time taken by the fabricated chip. It is observed that the actual chip performs as designed for current inputs above 1pA, while it takes a relatively long time to charge the capacitor as the input current reaches 1pA and below. The difference between the measured and ideal results below 1pA input current is attributed to parasitic capacitance of comparator and buffer added in the chip for testability of the design. As the gate voltage of the input transistors of the comparator reaches saturation, the input gate capacitance increases which causes the input current to take more time to charge or discharge the capacitor. This increase in capacitance is equivalent to requiring 100fA of extra current to charge or discharge the capacitor in the desired time according to equation 1 and has a noticeable effect when input currents less than 2pA are measured. It is observed that a little extra delay at each data point remains a constant percent of input current which can be easily eliminated by calibrating the capacitor at the output of the current conveyor. Currents from 1pA to Figure 2: Discharging time vs. Input current We can go for multiple application areas of using this low power potentiostat. A.

Environmental sensing: Fig. 3 shows the chip micrograph of the proposed potentiostat. The comparison of the input referred current noise is shown in Fig. 3(b). The all electrical performances of the prototype chip are summarized in Table I. The CV experiments were performed to verify electrochemical sensing operation of this chip by comparing results with a commercial potentiostat. Commercial 10um diameter platinum microelectrode was used as working electrode with platinum counter electrode and Ag/AgCl reference electrode. Fig. 4 shows comparisons between commercial potentiostat and implemented potentiostats. Fig. 4(b) shows the plot of the measured CV curve in 10 mM, 25 mM, and 50 mM ferricyanide solution. We can see that the magnitude of output current varies accurately with the change in the concentration with the redox potential of 0.3 V indicative of the ferricyanide solution with the S-shaped curve indicative of microelectrode array behavior. The results have been compared to commercial potentiostat with only 7% offset error and negligible gain error. Figure 3: (a) Die micrograph of proposed potentiostat and (b) noise performances

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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 1 - May 2014

Figure 4: Plot of CV measurement of T2: (a) comparison of commercial potentiostat IV.

USE OF E LECTROCHEMICAL D ETECTOR A RRAYS We fabricated a test chip containing a detector array in a 0.5- m, 5-V CMOS process through MOSIS in order to verify the basic operation of the detector and the shared amplifier circuit technique, shown in Fig 5. The area of a single detector was

10u

m 2 and the pitch was m. Fig.

6

shows the test results from a single detector. Each unit contained a 50-fF integration capacitor. We set the amplifier bias current to 100 nA for these measurements. The power consumption of each unit is 1 W.

For these tests, we supplied the input current through an nMOS current mirror.We varied the input current from 10– 600 pA and

used an integration time of 400 s. Throughout, we held the

reference voltage constant at 0.7 V, which is a typical electrode potential for amperometric experiments. It should be noted that the output voltage does not extend all the way to the positive supply rail, because it was buffered by an amplifier whose maximum output voltage was 4.85 V. Thus, for the smallest input currents, the final output voltage is not discernable. A rail-to-rail buffer design would make measuring small currents possible.

Figure 5: Micrograph of the die showing the 5 5 array of electrodes. The electrodes As the input current increases, the final output voltage

increases

linearly. With a 50-fF integration capacitor and a 400- s integration time, the output voltage saturates at about 0.8 V for an input current of 500 pA. An improved buffer design will make it possible to record smaller currents down to the noise limit, such a design is required to record amperometric foot signals. Fig.

7

shows the current–voltage (

I–V

) characteristic of a unit detector after the correlated double sampling circuit. The fit and the measured data are in good agreement verifying the linear behavior

of the potentiostat. The transimpedance gain of the potentiostat

detector is 9.3 mV/pA. The coefficient of determination of the

I–V

characteristic is 0.99 in the current range of 20–400 pA. The charge resolution is set by the noise. The noise at the output of the detector, for measurements at input current of 20 pA is shown in Fig. 8. The figure shows thousand superimposed measurements of the output voltage. The rms noise of the measurements is 110 fA or 274 electrons. Figure 6: Measurement results showing the output voltage of the unit potentiostat

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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 1 - May 2014

The maximum charge storage capacity is approximately 1.26x10

6 electrons. Current commercially available amplifiers used for amperometry include the VA10 (NPI Electronics), which specifies current noise less than 1 pA as well as the high-end low-noise patch clamp amplifiers EPC7/8 (HEKA Electronics) and Axopatch 200B (Molecular Devices). For the EPC7/8 noise less than 0.1 pA is specified at 3-kHz bandwidth, which is close to the 0.11 pA at 2-kHz bandwidth of our circuit. The lowest noise is achieved by the Axopatch 200B (0.06 pA at 5 kHz). Our circuit uses very few components and incorporates a scalable array of amplifiers and compares overall favorably with current state-of-the-art instruments. Based on the circuit design, we expect that the noise performance of our circuit may be optimized eventually approaching that of the Axopatch 200B amplifier. Figure 7: Measured data showing the output of the correlated double sampling Fig. 7 shows the output of the CDS circuit of a single detector in the prototype 5 5 array. Here again, the CDS output is seen to vary linearly with the input current. The transimpedance gain of the detector circuit after the CDS stage is 9 mV/pA. The

I

V

characteristic of the CDS output of several pixels in a row is shown in Fig 9. Experimental data and linear fit are in good agreement verifying linear operation.

Figure 9: Measured data showing (a) varying voltage applied to the gate of the

The mismatch between potentiostats in a row varied from 6%–14%. It is important to note that one of the factors that contributes to the mismatch is the use of current mirrors of minimum dimensions to inject current. Current mirrors would not be necessary in the electrochemical setup, whichwould reduce the mismatch. Dynamic current measurements are shown in Fig. 8. A slow-moving sine wave is applied to the gate of the current mirror. At sampling frequency of 6 kHz, the output follows the input voltage above the threshold voltage of the nMOS transistor. V.

C ONCLUSION A CMOS potentiostat with novel low power, low-input Impedance front end has been proposed and characterized experimentally using a standard ferricyanide solution. The chip is ideally suited for detection of trace metal ions in drinking water for commercial deployment. Further improvement in detection limits towards nanomolar range is expected using an array of microelectrodes and using averaging over multiple scan cycles because the array of microelectrodes can be integrated with the proposed potentiostat on silicon substrate for a higher SNR detection.

Figure 8: Measured data showing the IV characteristic of several potentiostats

1.

2.

3.

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Rollakanti Raju, Associate Professor, MLRITM

Author’s Profile

Mr. Rollakanti Raju has completed B.E from ANDHRA UNIVERSITY and M.Tech from JNTU ANANTHAPUR in DSCE. He is pursuing Ph.D in the area of VLSI from JNTUH. He has guided over 40 projects.

M.Vishwanath, Assistant Professor, MLRITM Mr. M.Vishwanath has completed his Masters degree in VLSI from MITS College of Technology, JNTUH. His reserch areas are VLSI, low power emerging trends in VLSI. Mr. Chandra Shekar has completed his M.Tech in vlsi system design from JNTUH. His research areas are microelectronics, low power vlsi, digital design. Currently he is working as a assistant professor in MLRITM. Mr. Chandra Shekar, Assistant Professor, MLRITM M.Gopala Krishna, Assistant Professor, MIC College of Technology Mr. M.Gopala Krishna has completed his B.Tech from ANURAG engineering college in ECE and M.Tech from MITS, Kodad. Presently working as Assistant professor in MIC College of technology, Kanchikacherla, Vijayawada. He has 5 years of teaching experience.

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